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This commit is contained in:
laurent
2020-04-13 18:04:18 +02:00
parent 6bbf9011ba e197824e20
commit 861caa735d
242 changed files with 27021 additions and 18729 deletions
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nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h
+5 -2
View File
@@ -8,6 +8,9 @@
#define FAPI_NR_MAX_NUM_ZP_CSI_RS_RESOURCE_PER_SET 16
#define FAPI_NR_MAX_NUM_CANDIDATE_BEAMS 16
#define FAPI_NR_MAX_RA_OCCASION_PER_CSIRS 64
// Constants Defined in 38.213
#define FAPI_NR_MAX_CORESET_PER_BWP 3
#define FAPI_NR_MAX_SS_PER_CORESET 10
/// RX_IND
@@ -41,8 +44,8 @@
#define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02
#define CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01
#define CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02
#define FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01
#define FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02
#define PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE 0x01
#define PRECODER_GRANULARITY_ALL_CONTIGUOUS_RBS 0x02
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
+142 -113
View File
@@ -1,5 +1,4 @@
/*
* Copyright 2017 Cisco Systems, Inc.
/*Copyright 2017 Cisco Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -32,77 +31,7 @@
typedef signed char int8_t;
*/
typedef struct {
uint8_t identifier_dci_formats ; // 0 IDENTIFIER_DCI_FORMATS:
uint8_t carrier_ind ; // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1:
uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND:
uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND:
uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND:
uint8_t short_messages ; // 9 SHORT_MESSAGES:
uint16_t freq_dom_resource_assignment_UL; // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
// (NOTE 1) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding
// is larger than the payload size of the DCI format 1_0 monitored in common search space
// the bitwidth of the frequency domain resource allocation field in the DCI format 0_0
// is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0
uint16_t freq_dom_resource_assignment_DL; // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
uint8_t time_dom_resource_assignment ; // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
// where I the number of entries in the higher layer parameter pusch-AllocationList
uint8_t vrb_to_prb_mapping ; // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
uint8_t prb_bundling_size_ind ; // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
uint8_t rate_matching_ind ; // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
uint8_t zp_csi_rs_trigger ; // 16 ZP_CSI_RS_TRIGGER:
uint8_t freq_hopping_flag ; // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
uint8_t tb1_mcs ; // 18 TB1_MCS:
uint8_t tb1_ndi ; // 19 TB1_NDI:
uint8_t tb1_rv ; // 20 TB1_RV:
uint8_t tb2_mcs ; // 21 TB2_MCS:
uint8_t tb2_ndi ; // 22 TB2_NDI:
uint8_t tb2_rv ; // 23 TB2_RV:
uint8_t mcs ; // 24 MCS:
uint8_t ndi ; // 25 NDI:
uint8_t rv ; // 26 RV:
uint8_t harq_process_number ; // 27 HARQ_PROCESS_NUMBER:
uint8_t dai ; // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
// 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
// 0 otherwise
uint8_t first_dai ; // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK
uint8_t second_dai ; // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
uint8_t tb_scaling ; // 31 TB_SCALING:
uint8_t tpc_pusch ; // 32 TPC_PUSCH:
uint8_t tpc_pucch ; // 33 TPC_PUCCH:
uint8_t pucch_resource_ind ; // 34 PUCCH_RESOURCE_IND:
uint8_t pdsch_to_harq_feedback_time_ind ; // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
uint8_t srs_resource_ind ; // 36 SRS_RESOURCE_IND:
uint8_t precod_nbr_layers ; // 37 PRECOD_NBR_LAYERS:
uint8_t antenna_ports ; // 38 ANTENNA_PORTS:
uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
uint8_t srs_request ; // 40 SRS_REQUEST:
uint8_t tpc_cmd ; // 41 TPC_CMD:
uint8_t csi_request ; // 42 CSI_REQUEST:
uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
uint8_t ptrs_dmrs ; // 45 PTRS_DMRS:
uint8_t beta_offset_ind ; // 46 BETA_OFFSET_IND:
uint8_t dmrs_seq_ini ; // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding
// is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
uint8_t ul_sch_ind ; // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
uint16_t padding_nr_dci ; // 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding
// is less than the payload size of the DCI format 1_0 monitored in common search space
// zeros shall be appended to the DCI format 0_0
// until the payload size equals that of the DCI format 1_0
uint8_t sul_ind_0_0 ; // 50 SUL_IND_0_0:
uint8_t ra_preamble_index ; // 51 RA_PREAMBLE_INDEX:
uint8_t sul_ind_1_0 ; // 52 SUL_IND_1_0:
uint8_t ss_pbch_index ; // 53 SS_PBCH_INDEX
uint8_t prach_mask_index ; // 54 PRACH_MASK_INDEX
uint8_t reserved_nr_dci ; // 55 RESERVED_NR_DCI
} fapi_nr_dci_pdu_rel15_t;
@@ -121,16 +50,14 @@ typedef struct {
typedef struct {
/// frequency_domain_resource;
//uint32_t rb_start;
//uint32_t rb_end;
uint64_t frequency_domain_resource;
uint16_t rb_offset;
uint8_t frequency_domain_resource[6];
uint8_t StartSymbolIndex;
uint8_t duration;
uint8_t cce_reg_mapping_type; // interleaved or noninterleaved
uint8_t cce_reg_interleaved_reg_bundle_size; // valid if CCE to REG mapping type is interleaved type
uint8_t cce_reg_interleaved_interleaver_size; // valid if CCE to REG mapping type is interleaved type
uint8_t cce_reg_interleaved_shift_index; // valid if CCE to REG mapping type is interleaved type
uint8_t CceRegMappingType; // interleaved or noninterleaved
uint8_t RegBundleSize; // valid if CCE to REG mapping type is interleaved type
uint8_t InterleaverSize; // valid if CCE to REG mapping type is interleaved type
uint8_t ShiftIndex; // valid if CCE to REG mapping type is interleaved type
uint8_t CoreSetType;
uint8_t precoder_granularity;
uint16_t pdcch_dmrs_scrambling_id;
@@ -155,13 +82,16 @@ typedef struct {
int n_CCE;
// N_CCE is L, or number of CCEs for DCI
int N_CCE;
fapi_nr_dci_pdu_rel15_t dci;
uint8_t payloadSize;
uint8_t payloadBits[16];
//fapi_nr_dci_pdu_rel15_t dci;
} fapi_nr_dci_indication_pdu_t;
///
typedef struct {
uint32_t sfn_slot;
uint16_t SFN;
uint8_t slot;
uint16_t number_of_dcis;
fapi_nr_dci_indication_pdu_t dci_list[10];
} fapi_nr_dci_indication_t;
@@ -199,7 +129,8 @@ typedef struct {
///
#define NFAPI_RX_IND_MAX_PDU 100
typedef struct {
uint32_t sfn_slot;
uint16_t sfn;
uint16_t slot;
uint16_t number_pdus;
fapi_nr_rx_indication_body_t rx_indication_body[NFAPI_RX_IND_MAX_PDU];
} fapi_nr_rx_indication_t;
@@ -218,7 +149,8 @@ typedef struct {
///
typedef struct {
uint32_t sfn_slot;
uint16_t sfn;
uint16_t slot;
fapi_nr_tx_config_t tx_config;
uint16_t number_of_pdus;
fapi_nr_tx_request_body_t *tx_request_body;
@@ -374,7 +306,8 @@ typedef struct {
} fapi_nr_ul_config_request_pdu_t;
typedef struct {
uint32_t sfn_slot;
uint16_t sfn;
uint16_t slot;
uint8_t number_pdus;
fapi_nr_ul_config_request_pdu_t ul_config_list[FAPI_NR_UL_CONFIG_LIST_NUM];
} fapi_nr_ul_config_request_t;
@@ -382,16 +315,15 @@ typedef struct {
typedef struct {
uint16_t rnti;
uint16_t BWPSize;
uint16_t BWPStart;
uint8_t SubcarrierSpacing;
fapi_nr_coreset_t coreset;
uint16_t N_RB_BWP;
uint32_t duration;
uint8_t number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
uint16_t monitoring_symbols_within_slot;
// DCI foramt-specific
uint8_t format_2_0_number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
uint8_t format_2_3_monitorying_periodicity;
uint8_t format_2_3_number_of_candidates;
uint8_t number_of_candidates;
uint16_t CCE[64];
uint8_t L[64];
uint8_t dci_length;
uint8_t dci_format;
} fapi_nr_dl_config_dci_dl_pdu_rel15_t;
typedef struct {
@@ -404,12 +336,16 @@ typedef struct{
typedef enum{vrb_to_prb_mapping_non_interleaved = 0, vrb_to_prb_mapping_interleaved = 1} vrb_to_prb_mapping_t;
//typedef fapi_nr_dci_pdu_rel15_t fapi_nr_dl_config_dlsch_pdu_rel15_t;
typedef struct {
uint8_t bandwidth_part_ind;
uint16_t BWPSize;
uint16_t BWPStart;
uint8_t SubcarrierSpacing;
uint16_t number_rbs;
uint16_t start_rb;
uint8_t frame_offset;
uint16_t number_symbols;
uint16_t start_symbol;
uint16_t dlDmrsSymbPos;
uint8_t dmrsConfigType;
uint8_t prb_bundling_size_ind;
uint8_t rate_matching_ind;
uint8_t zp_csi_rs_trigger;
@@ -450,7 +386,8 @@ typedef struct {
} fapi_nr_dl_config_request_pdu_t;
typedef struct {
uint32_t sfn_slot;
uint16_t sfn;
uint16_t slot;
uint8_t number_pdus;
fapi_nr_dl_config_request_pdu_t dl_config_list[FAPI_NR_DL_CONFIG_LIST_NUM];
} fapi_nr_dl_config_request_t;
@@ -544,20 +481,6 @@ typedef struct {
uint8_t p0_nominal;
} fapi_nr_pucch_config_common_t;
typedef struct {
uint8_t subcarrier_spacing_common;
uint8_t ssb_subcarrier_offset;
uint8_t dmrs_type_a_position;
uint8_t pdcch_config_sib1;
uint8_t cell_barred;
uint8_t intra_frequency_reselection;
uint16_t system_frame_number;
uint8_t ssb_index;
uint8_t half_frame_bit;
} fapi_nr_pbch_config_t;
typedef struct {
fapi_nr_pdcch_config_common_t pdcch_config_common;
@@ -907,10 +830,115 @@ typedef struct {
#define FAPI_NR_CONFIG_REQUEST_MASK_DL_BWP_DEDICATED 0x08
#define FAPI_NR_CONFIG_REQUEST_MASK_UL_BWP_DEDICATED 0x10
typedef struct
{
uint16_t dl_bandwidth;//Carrier bandwidth for DL in MHz [38.104, sec 5.3.2] Values: 5, 10, 15, 20, 25, 30, 40,50, 60, 70, 80,90,100,200,400
uint32_t dl_frequency; //Absolute frequency of DL point A in KHz [38.104, sec5.2 and 38.211 sec 4.4.4.2] Value: 450000 -> 52600000
uint16_t dl_k0[5];//𝑘_{0}^{𝜇} for each of the numerologies [38.211, sec 5.3.1] Value: 0 ->23699
uint16_t dl_grid_size[5];//Grid size 𝑁_{𝑔𝑟𝑖𝑑}^{𝑠𝑖𝑧𝑒,𝜇} for each of the numerologies [38.211, sec 4.4.2] Value: 0->275 0 = this numerology not used
uint16_t num_tx_ant;//Number of Tx antennas
uint16_t uplink_bandwidth;//Carrier bandwidth for UL in MHz. [38.104, sec 5.3.2] Values: 5, 10, 15, 20, 25, 30, 40,50, 60, 70, 80,90,100,200,400
uint32_t uplink_frequency;//Absolute frequency of UL point A in KHz [38.104, sec5.2 and 38.211 sec 4.4.4.2] Value: 450000 -> 52600000
uint16_t ul_k0[5];//𝑘0 𝜇 for each of the numerologies [38.211, sec 5.3.1] Value: : 0 ->23699
uint16_t ul_grid_size[5];//Grid size 𝑁𝑔𝑟𝑖𝑑 𝑠𝑖𝑧𝑒,𝜇 for each of the numerologies [38.211, sec 4.4.2]. Value: 0->275 0 = this numerology not used
uint16_t num_rx_ant;//
uint8_t frequency_shift_7p5khz;//Indicates presence of 7.5KHz frequency shift. Value: 0 = false 1 = true
} fapi_nr_ue_carrier_config_t;
typedef struct
{
uint8_t phy_cell_id;//Physical Cell ID, 𝑁_{𝐼𝐷}^{𝑐𝑒𝑙𝑙} [38.211, sec 7.4.2.1] Value: 0 ->1007
uint8_t frame_duplex_type;//Frame duplex type Value: 0 = FDD 1 = TDD
} fapi_nr_cell_config_t;
typedef struct
{
uint32_t ss_pbch_power;//SSB Block Power Value: TBD (-60..50 dBm)
uint8_t bch_payload;//Defines option selected for generation of BCH payload, see Table 3-13 (v0.0.011 Value: 0: MAC generates the full PBCH payload 1: PHY generates the timing PBCH bits 2: PHY generates the full PBCH payload
uint8_t scs_common;//subcarrierSpacing for common, used for initial access and broadcast message. [38.211 sec 4.2] Value:0->3
} fapi_nr_ssb_config_t;
typedef struct
{
uint32_t ssb_mask;//Bitmap for actually transmitted SSB. MSB->LSB of first 32 bit number corresponds to SSB 0 to SSB 31 MSB->LSB of second 32 bit number corresponds to SSB 32 to SSB 63 Value for each bit: 0: not transmitted 1: transmitted
} fapi_nr_ssb_mask_size_2_t;
typedef struct
{
int8_t beam_id[64];//BeamID for each SSB in SsbMask. For example, if SSB mask bit 26 is set to 1, then BeamId[26] will be used to indicate beam ID of SSB 26. Value: from 0 to 63
} fapi_nr_ssb_mask_size_64_t;
typedef struct
{
uint16_t ssb_offset_point_a;//Offset of lowest subcarrier of lowest resource block used for SS/PBCH block. Given in PRB [38.211, section 4.4.4.2] Value: 0->2199
uint8_t beta_pss;//PSS EPRE to SSS EPRE in a SS/PBCH block [38.213, sec 4.1] Values: 0 = 0dB
uint8_t ssb_period;//SSB periodicity in msec Value: 0: ms5 1: ms10 2: ms20 3: ms40 4: ms80 5: ms160
uint8_t ssb_subcarrier_offset;//ssbSubcarrierOffset or 𝑘𝑆𝑆𝐵 (38.211, section 7.4.3.1) Value: 0->31
uint32_t MIB;//MIB payload, where the 24 MSB are used and represent the MIB in [38.331 MIB IE] and represent 0 1 2 3 1 , , , ,..., A− a a a a a [38.212, sec 7.1.1]
fapi_nr_ssb_mask_size_2_t ssb_mask_list[2];
fapi_nr_ssb_mask_size_64_t* ssb_beam_id_list;//64
uint8_t ss_pbch_multiple_carriers_in_a_band;//0 = disabled 1 = enabled
uint8_t multiple_cells_ss_pbch_in_a_carrier;//Indicates that multiple cells will be supported in a single carrier 0 = disabled 1 = enabled
} fapi_nr_ssb_table_t;
typedef struct
{
uint8_t slot_config;//For each symbol in each slot a uint8_t value is provided indicating: 0: DL slot 1: UL slot 2: Guard slot
} fapi_nr_max_num_of_symbol_per_slot_t;
typedef struct
{
fapi_nr_max_num_of_symbol_per_slot_t* max_num_of_symbol_per_slot_list;
} fapi_nr_max_tdd_periodicity_t;
typedef struct
{
uint8_t tdd_period;//DL UL Transmission Periodicity. Value:0: ms0p5 1: ms0p625 2: ms1 3: ms1p25 4: ms2 5: ms2p5 6: ms5 7: ms10 8: ms3 9: ms4
fapi_nr_max_tdd_periodicity_t* max_tdd_periodicity_list;
} fapi_nr_tdd_table_t;
typedef struct
{
uint8_t num_prach_fd_occasions;
uint16_t prach_root_sequence_index;//Starting logical root sequence index, 𝑖, equivalent to higher layer parameter prach-RootSequenceIndex [38.211, sec 6.3.3.1] Value: 0 -> 837
uint8_t num_root_sequences;//Number of root sequences for a particular FD occasion that are required to generate the necessary number of preambles
uint16_t k1;//Frequency offset (from UL bandwidth part) for each FD. [38.211, sec 6.3.3.2] Value: from 0 to 272
uint8_t prach_zero_corr_conf;//PRACH Zero CorrelationZone Config which is used to dervive 𝑁𝑐𝑠 [38.211, sec 6.3.3.1] Value: from 0 to 15
uint8_t num_unused_root_sequences;//Number of unused sequences available for noise estimation per FD occasion. At least one unused root sequence is required per FD occasion.
uint8_t* unused_root_sequences_list;//Unused root sequence or sequences per FD occasion. Required for noise estimation.
} fapi_nr_num_prach_fd_occasions_t;
typedef struct
{
uint8_t prach_sequence_length;//RACH sequence length. Only short sequence length is supported for FR2. [38.211, sec 6.3.3.1] Value: 0 = Long sequence 1 = Short sequence
uint8_t prach_sub_c_spacing;//Subcarrier spacing of PRACH. [38.211 sec 4.2] Value:0->4
uint8_t restricted_set_config;//PRACH restricted set config Value: 0: unrestricted 1: restricted set type A 2: restricted set type B
uint8_t num_prach_fd_occasions;//Corresponds to the parameter 𝑀 in [38.211, sec 6.3.3.2] which equals the higher layer parameter msg1FDM Value: 1,2,4,8
fapi_nr_num_prach_fd_occasions_t* num_prach_fd_occasions_list;
uint8_t ssb_per_rach;//SSB-per-RACH-occasion Value: 0: 1/8 1:1/4, 2:1/2 3:1 4:2 5:4, 6:8 7:16
uint8_t prach_multiple_carriers_in_a_band;//0 = disabled 1 = enabled
} fapi_nr_prach_config_t;
typedef struct {
uint32_t config_mask;
fapi_nr_pbch_config_t pbch_config; // MIB
fapi_nr_ue_carrier_config_t carrier_config;
fapi_nr_cell_config_t cell_config;
fapi_nr_ssb_config_t ssb_config;
fapi_nr_ssb_table_t ssb_table;
fapi_nr_tdd_table_t tdd_table;
fapi_nr_prach_config_t prach_config;
fapi_nr_dl_bwp_common_config_t dl_bwp_common;
fapi_nr_dl_bwp_dedicated_config_t dl_bwp_dedicated;
@@ -921,3 +949,4 @@ typedef struct {
} fapi_nr_config_request_t;
#endif
nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h
+93 -206
View File
@@ -10,44 +10,18 @@
#define _NFAPI_NR_INTERFACE_H_
#include "nfapi_interface.h"
#include <nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h>
#define NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS 5
#define NFAPI_NR_MAX_NB_TCI_STATES_PDCCH 64
#define NFAPI_NR_MAX_NB_CORESETS 12
#define NFAPI_NR_MAX_NB_SEARCH_SPACES 40
// Extension to the generic structures for single tlv values
typedef struct {
nfapi_tl_t tl;
int32_t value;
} nfapi_int32_tlv_t;
typedef struct {
nfapi_tl_t tl;
uint32_t value;
} nfapi_uint32_tlv_t;
/*typedef struct {
nfapi_tl_t tl;
int64_t value;
} nfapi_int64_tlv_t;*/
typedef struct {
nfapi_tl_t tl;
uint64_t value;
} nfapi_uint64_tlv_t;
// nFAPI enums
typedef enum {
NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE = 0,
NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_PCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_NBCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_NPDCCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_NDLSCH_PDU_TYPE
} nfapi_nr_dl_config_pdu_type_e;
//These TLVs are used exclusively by nFAPI
typedef struct
@@ -106,37 +80,6 @@ typedef struct
// P5 Message Structures
typedef struct{
nfapi_tl_t tl;
uint16_t corset_ID; ///// L1 parameter 'CORESET-ID'
uint16_t freq_dom; ///// L1 parameter 'CORESET-freq-dom'
uint16_t duration; ///// L1 parameter 'CORESET-time-duration'
uint16_t reg_type; ///// L1 parameter 'CORESET-CCE-REG-mapping-type'
uint16_t reg_bundlesize; ///// L1 parameter 'CORESET-REG-bundle-size'
uint16_t interleaversize; ///// L1 parameter 'CORESET-interleaver-size'
uint16_t shiftindex; ///// L1 parameter 'CORESET-shift-index'
uint16_t precodergranularity; ///// L1 parameter 'CORESET-precoder-granuality'
uint16_t tci_stateId; ///// L1 parameter 'TCI-StatesPDCCH'
uint16_t tci_present; ///// L1 parameter 'TCI-PresentInDCI'
uint16_t dmrs_scramblingID; ///// L1 parameter 'PDCCH-DMRS-Scrambling-ID'
} nfapi_nr_ControlResourcesSet_t;
typedef struct{
nfapi_tl_t tl;
nfapi_nr_ControlResourcesSet_t coreset;
uint16_t monitoringSlotPeriodicityAndOffset; ///// L1 parameters 'Montoring-periodicity-PDCCH-slot'
uint16_t monitoringSymbolsWithinSlot; ///// L1 parameter 'Montoring-symbols-PDCCH-within-slot'
uint16_t nrofCand_aggLevel1; ///// L1 parameter 'Aggregation-level-1'
uint16_t nrofCand_aggLevel2; ///// L1 parameter 'Aggregation-level-2'
uint16_t nrofCand_aggLevel4; ///// L1 parameter 'Aggregation-level-4'
uint16_t nrofCand_aggLevel8; ///// L1 parameter 'Aggregation-level-8'
uint16_t nrofCand_aggLevel16; ///// L1 parameter 'Aggregation-level-16'
uint16_t sfi_agg_fmt2_0; ///// L1 parameters 'SFI-Num-PDCCH-cand' and 'SFI-Aggregation-Level'
uint16_t monitoringperiodicity_fmt2_3; ///// L1 parameter 'SRS-monitoring-periodicity'
uint16_t nrof_candidates_fmt_2_3; ///// L1 parameter 'SRS-Num-PDCCH-cand'
} nfapi_nr_SearchSpace_t;
typedef struct {
nfapi_uint16_tlv_t numerology_index_mu;
nfapi_uint16_tlv_t duplex_mode;
@@ -154,10 +97,6 @@ typedef struct {
typedef struct {
nfapi_uint16_tlv_t dl_carrier_bandwidth;
nfapi_uint16_tlv_t ul_carrier_bandwidth;
nfapi_uint16_tlv_t dl_bwp_subcarrierspacing;
nfapi_uint16_tlv_t ul_bwp_subcarrierspacing;
nfapi_uint16_tlv_t dl_locationandbandwidth;
nfapi_uint16_tlv_t ul_locationandbandwidth;
nfapi_uint16_tlv_t dl_absolutefrequencypointA;
nfapi_uint16_tlv_t ul_absolutefrequencypointA;
nfapi_uint16_tlv_t dl_offsettocarrier;
@@ -173,6 +112,8 @@ typedef struct {
#define NFAPI_NR_RF_CONFIG_UL_CARRIER_BANDWIDTH_TAG 0x500B
#define NFAPI_NR_RF_CONFIG_DL_SUBCARRIERSPACING_TAG 0x500C
#define NFAPI_NR_RF_CONFIG_UL_SUBCARRIERSPACING_TAG 0x500D
#define NFAPI_NR_RF_CONFIG_DL_OFFSETTOCARRIER_TAG 0x500E
#define NFAPI_NR_RF_CONFIG_UL_OFFSETTOCARRIER_TAG 0x500F
typedef struct {
nfapi_uint16_tlv_t physical_cell_id;
@@ -183,9 +124,25 @@ typedef struct {
nfapi_uint16_tlv_t ssb_periodicity;
nfapi_uint16_tlv_t ss_pbch_block_power;
nfapi_uint16_tlv_t n_ssb_crb;
nfapi_uint16_tlv_t rmsi_pdcch_config;
} nfapi_nr_sch_config_t;
typedef struct {
nfapi_uint16_tlv_t dl_bandwidth;
nfapi_uint16_tlv_t ul_bandwidth;
nfapi_uint16_tlv_t dl_offset;
nfapi_uint16_tlv_t ul_offset;
nfapi_uint16_tlv_t dl_subcarrierSpacing;
nfapi_uint16_tlv_t ul_subcarrierSpacing;
} nfapi_nr_initialBWP_config_t;
#define NFAPI_INITIALBWP_DL_BANDWIDTH_TAG 0x5010
#define NFAPI_INITIALBWP_DL_OFFSET_TAG 0x5011
#define NFAPI_INITIALBWP_DL_SUBCARRIERSPACING_TAG 0x5012
#define NFAPI_INITIALBWP_UL_BANDWIDTH_TAG 0x5013
#define NFAPI_INITIALBWP_UL_OFFSET_TAG 0x5014
#define NFAPI_INITIALBWP_UL_SUBCARRIERSPACING_TAG 0x5015
#define NFAPI_NR_SCH_CONFIG_PHYSICAL_CELL_ID_TAG 0x501E
#define NFAPI_NR_SCH_CONFIG_HALF_FRAME_INDEX_TAG 0x501F
#define NFAPI_NR_SCH_CONFIG_SSB_SUBCARRIER_OFFSET_TAG 0x5020
@@ -193,25 +150,15 @@ typedef struct {
#define NFAPI_NR_SCH_CONFIG_SSB_PERIODICITY 0x5022
#define NFAPI_NR_SCH_CONFIG_SS_PBCH_BLOCK_POWER 0x5023
#define NFAPI_NR_SCH_CONFIG_N_SSB_CRB 0x5024
#define NFAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS 16
#define NFAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS 16
typedef struct {
nfapi_uint16_tlv_t data_scrambling_id;
nfapi_uint16_tlv_t dmrs_typeA_position;
nfapi_uint16_tlv_t dmrs_additional_position;
nfapi_uint16_tlv_t dmrs_type;
nfapi_uint16_tlv_t dmrs_max_length;
nfapi_uint16_tlv_t mapping_type;
nfapi_uint16_tlv_t resource_allocation;
nfapi_uint16_tlv_t time_allocation_list;
nfapi_uint16_tlv_t mcs_table;
nfapi_uint16_tlv_t aggregation_factor;
nfapi_uint16_tlv_t prb_bundling_type;
nfapi_uint16_tlv_t rbg_size;
nfapi_uint16_tlv_t vrb_to_prb_interleaver;
nfapi_uint16_tlv_t code_block_groug_transmission;
nfapi_uint16_tlv_t x_overhead;
nfapi_uint16_tlv_t max_dci_codewords;
nfapi_uint16_tlv_t dmrs_TypeA_Position;
nfapi_uint16_tlv_t num_PDSCHTimeDomainResourceAllocations;
nfapi_uint16_tlv_t PDSCHTimeDomainResourceAllocation_k0[NFAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS];
nfapi_uint16_tlv_t PDSCHTimeDomainResourceAllocation_mappingType[NFAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS];
nfapi_uint16_tlv_t PDSCHTimeDomainResourceAllocation_startSymbolAndLength[NFAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS];
} nfapi_nr_pdsch_config_t;
#define NFAPI_NR_PDSCH_CONFIG_TAG
@@ -221,43 +168,64 @@ typedef struct {
nfapi_uint16_tlv_t prach_msg1_SubcarrierSpacing; ///// L1 parameter 'prach-Msg1SubcarrierSpacing'
nfapi_uint16_tlv_t restrictedSetConfig;
nfapi_uint16_tlv_t msg3_transformPrecoding; ///// L1 parameter 'msg3-tp'
nfapi_uint16_tlv_t ssb_perRACH_OccasionAndCB_PreamblesPerSSB;
nfapi_uint16_tlv_t ra_ContentionResolutionTimer;
nfapi_uint16_tlv_t rsrp_ThresholdSSB;
/////////////////--------------------NR RACH-ConfigGeneric--------------------/////////////////
nfapi_uint16_tlv_t prach_ConfigurationIndex; ///// L1 parameter 'PRACHConfigurationIndex'
nfapi_uint16_tlv_t prach_msg1_FDM; ///// L1 parameter 'prach-FDM'
nfapi_uint16_tlv_t prach_msg1_FrequencyStart; ///// L1 parameter 'prach-frequency-start'
nfapi_uint16_tlv_t zeroCorrelationZoneConfig;
nfapi_uint16_tlv_t preambleReceivedTargetPower;
nfapi_uint16_tlv_t preambleTransMax;
nfapi_uint16_tlv_t powerRampingStep;
nfapi_uint16_tlv_t ra_ResponseWindow;
} nfapi_nr_rach_config_t;
typedef struct {
nfapi_uint16_tlv_t groupHoppingEnabledTransformPrecoding; ///// L1 parameter 'Group-hopping-enabled-Transform-precoding'
nfapi_uint16_tlv_t msg3_DeltaPreamble; ///// L1 parameter 'Delta-preamble-msg3'
nfapi_uint16_tlv_t p0_NominalWithGrant; ///// L1 parameter 'p0-nominal-pusch-withgrant'
nfapi_uint16_tlv_t TimeDomainResourceAllocation_k2; ///// L1 parameter 'K2'
nfapi_uint16_tlv_t TimeDomainResourceAllocation_mappingType; ///// L1 parameter 'Mapping-type'
nfapi_uint16_tlv_t dmrs_TypeA_Position;
nfapi_uint16_tlv_t num_PUSCHTimeDomainResourceAllocations;
nfapi_uint16_tlv_t PUSCHTimeDomainResourceAllocation_k2[NFAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS]; ///// L1 parameter 'K2'
nfapi_uint16_tlv_t PUSCHTimeDomainResourceAllocation_mappingType[NFAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS]; ///// L1 parameter 'Mapping-type'
nfapi_uint16_tlv_t PUSCHTimeDomainResourceAllocation_startSymbolAndLength[NFAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS];
} nfapi_nr_pusch_config_t;
typedef struct {
uint8_t pucch_resource_common;
nfapi_uint16_tlv_t pucch_GroupHopping; ///// L1 parameter 'PUCCH-GroupHopping'
nfapi_uint16_tlv_t p0_nominal; ///// L1 parameter 'p0-nominal-pucch'
} nfapi_nr_pucch_config_t;
typedef struct {
nfapi_tl_t tl;
nfapi_nr_SearchSpace_t sib1searchSpace;
nfapi_nr_SearchSpace_t sibssearchSpace;
nfapi_nr_SearchSpace_t ra_SearchSpace;
nfapi_uint16_tlv_t controlResourceSetZero;
nfapi_uint16_tlv_t searchSpaceZero;
// nfapi_nr_SearchSpace_t sib1searchSpace;
// nfapi_nr_SearchSpace_t sibssearchSpace;
// nfapi_nr_SearchSpace_t ra_SearchSpace;
}nfapi_nr_pdcch_config_t;
typedef struct {
//NR TDD-UL-DL-ConfigCommon ///// L1 parameter 'UL-DL-configuration-common'
nfapi_uint16_tlv_t subcarrierspacing; ///// L1 parameter 'reference-SCS'
nfapi_uint16_tlv_t referenceSubcarrierSpacing; ///// L1 parameter 'reference-SCS'
nfapi_uint16_tlv_t dl_ul_periodicity; ///// L1 parameter 'DL-UL-transmission-periodicity'
nfapi_uint16_tlv_t nrofDownlinkSlots; ///// L1 parameter 'number-of-DL-slots'
nfapi_uint16_tlv_t nrofDownlinkSymbols; ///// L1 parameter 'number-of-DL-symbols-common'
nfapi_uint16_tlv_t nrofUplinkSlots; ///// L1 parameter 'number-of-UL-slots'
nfapi_uint16_tlv_t nrofUplinkSymbols; ///// L1 parameter 'number-of-UL-symbols-common'
nfapi_uint16_tlv_t Pattern2Present;
nfapi_uint16_tlv_t Pattern2_dl_ul_periodicity; ///// L1 parameter 'DL-UL-transmission-periodicity'
nfapi_uint16_tlv_t Pattern2_nrofDownlinkSlots; ///// L1 parameter 'number-of-DL-slots'
nfapi_uint16_tlv_t Pattern2_nrofDownlinkSymbols; ///// L1 parameter 'number-of-DL-symbols-common'
nfapi_uint16_tlv_t Pattern2_nrofUplinkSlots; ///// L1 parameter 'number-of-UL-slots'
nfapi_uint16_tlv_t Pattern2_nrofUplinkSymbols; ///// L1 parameter 'number-of-UL-symbols-common'
} nfapi_nr_tdd_ul_dl_config_t;
typedef struct {
@@ -287,6 +255,7 @@ typedef struct {
nfapi_nr_subframe_config_t subframe_config;
nfapi_nr_rf_config_t rf_config;
nfapi_nr_sch_config_t sch_config;
nfapi_nr_initialBWP_config_t initialBWP_config;
nfapi_nr_pdsch_config_t pdsch_config;
nfapi_nr_rach_config_t rach_config;
nfapi_nr_pusch_config_t pusch_config;
@@ -426,13 +395,9 @@ typedef enum {
NFAPI_NR_MCS_TABLE_QAM256
} nfapi_nr_pdsch_mcs_table_e;
typedef enum {
NFAPI_NR_DMRS_TYPE1=0,
NFAPI_NR_DMRS_TYPE2
} nfapi_nr_dmrs_type_e;
// P7 Sub Structures
/*
typedef struct {
nfapi_tl_t tl;
@@ -495,9 +460,12 @@ uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16
uint16_t padding;
} nfapi_nr_dl_config_dci_dl_pdu_rel15_t;
*/
//#define NFAPI_NR_DL_CONFIG_REQUEST_DCI_DL_PDU_REL15_TAG 0x????
/*
typedef struct{
nfapi_tl_t tl;
uint8_t coreset_id;
@@ -532,11 +500,13 @@ typedef struct{
uint16_t number_of_candidates[NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS];
} nfapi_nr_search_space_t;
typedef struct {
nfapi_tl_t tl;
uint16_t rnti;
uint8_t rnti_type;
uint8_t dci_format;
uint16_t cce_index;
/// Number of CRB in BWP that this DCI configures
uint16_t n_RB_BWP;
uint8_t config_type;
@@ -561,118 +531,7 @@ typedef struct {
nfapi_bf_vector_t bf_vector;
} nfapi_nr_dl_config_pdcch_parameters_rel15_t;
typedef struct {
nfapi_tl_t tl;
uint16_t length;
int16_t pdu_index;
uint16_t transmission_power;
} nfapi_nr_dl_config_bch_pdu_rel15_t;
#define NFAPI_NR_DL_CONFIG_REQUEST_BCH_PDU_REL15_TAG 0x5025
typedef struct {
nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15;
} nfapi_nr_dl_config_bch_pdu;
typedef struct {
nfapi_tl_t tl;
uint16_t length;
uint8_t pdu_index;
uint16_t rnti;
uint16_t nb_mod_symbols;
uint8_t time_allocation_type;
uint8_t freq_allocation_type;
uint16_t start_prb;
uint16_t n_prb;
uint8_t start_symbol;
uint8_t nb_symbols;
uint8_t mcs_idx;
uint8_t mcs_table;
uint8_t ndi;
uint8_t nb_codewords;
uint8_t nb_layers;
uint16_t coding_rate;
uint8_t modulation;
uint8_t modulation_order;
uint32_t transport_block_size;
uint8_t nb_re_dmrs;
uint8_t time_alloc_list_flag;
uint8_t time_alloc_list;
uint8_t rbg_list;
uint8_t virtual_resource_block_assignment_flag;
uint32_t resource_block_coding;
uint8_t redundancy_version;
uint8_t transport_blocks;
uint8_t transmission_scheme;
uint8_t number_of_subbands;
uint8_t codebook_index[NFAPI_MAX_NUM_SUBBANDS];
uint8_t ue_category_capacity;
uint8_t pa;
uint8_t delta_power_offset_index;
uint8_t ngap;
uint8_t transmission_mode;
uint8_t num_bf_prb_per_subband;
uint8_t num_bf_vector;
nfapi_bf_vector_t bf_vector[NFAPI_MAX_BF_VECTORS];
}nfapi_nr_dl_config_dlsch_pdu_rel15_t;
#define NFAPI_NR_DL_CONFIG_REQUEST_DLSCH_PDU_REL15_TAG
typedef struct {
nfapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_pdu_rel15;
} nfapi_nr_dl_config_dlsch_pdu;
typedef struct {
nfapi_tl_t tl;
nfapi_nr_search_space_t pagingSearchSpace;
nfapi_nr_coreset_t pagingControlResourceSets;
}nfapi_nr_dl_config_pch_pdu_rel15_t;
typedef struct {
} nfapi_nr_dl_config_nbch_pdu_rel15_t;
typedef struct {
} nfapi_nr_dl_config_npdcch_pdu_rel15_t;
typedef struct {
} nfapi_nr_dl_config_ndlsch_pdu_rel15_t;
typedef struct {
nfapi_nr_dl_config_dci_dl_pdu_rel15_t dci_dl_pdu_rel15;
nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params_rel15;
} nfapi_nr_dl_config_dci_dl_pdu;
typedef struct {
uint8_t pdu_type;
uint8_t pdu_size;
union {
nfapi_nr_dl_config_dci_dl_pdu dci_dl_pdu;
nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15;
nfapi_nr_dl_config_dlsch_pdu dlsch_pdu;
nfapi_nr_dl_config_pch_pdu_rel15_t pch_pdu_rel15;
nfapi_nr_dl_config_nbch_pdu_rel15_t nbch_pdu_rel15;
nfapi_nr_dl_config_npdcch_pdu_rel15_t npdcch_pdu_rel15;
nfapi_nr_dl_config_ndlsch_pdu_rel15_t ndlsch_pdu_rel15;
};
} nfapi_nr_dl_config_request_pdu_t;
typedef struct {
nfapi_tl_t tl;
uint8_t number_dci;
uint8_t number_pdu;
uint8_t number_pdsch_rnti;
nfapi_nr_dl_config_request_pdu_t *dl_config_pdu_list;
} nfapi_nr_dl_config_request_body_t;
typedef struct {
nfapi_p7_message_header_t header;
uint16_t sfn_sf;
nfapi_nr_dl_config_request_body_t dl_config_request_body;
nfapi_vendor_extension_tlv_t vendor_extension;
} nfapi_nr_dl_config_request_t;
*/
typedef enum {nr_pusch_freq_hopping_disabled = 0 ,
@@ -711,9 +570,37 @@ typedef struct {
uint8_t beta_offset_ind;
} nfapi_nr_ul_config_ulsch_pdu_rel15_t;
typedef struct {
uint16_t rnti;
nfapi_nr_ul_config_ulsch_pdu_rel15_t ulsch_pdu_rel15;
} nfapi_nr_ul_config_ulsch_pdu;
typedef struct {
uint8_t pdu_type;
uint8_t pdu_size;
union {
// nfapi_nr_ul_config_uci_pdu uci_pdu;
nfapi_nr_ul_config_ulsch_pdu ulsch_pdu;
// nfapi_nr_ul_config_srs_pdu srs_pdu;
};
} nfapi_nr_ul_config_request_pdu_t;
typedef struct {
nfapi_tl_t tl;
uint8_t number_pdu;
nfapi_nr_ul_config_request_pdu_t *ul_config_pdu_list;
} nfapi_nr_ul_config_request_body_t;
typedef struct {
nfapi_p7_message_header_t header;
uint16_t sfn_sf;
nfapi_nr_ul_config_request_body_t ul_config_request_body;
nfapi_vendor_extension_tlv_t vendor_extension;
} nfapi_nr_ul_config_request_t;
#endif
nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h
+441 -198
View File
@@ -11,7 +11,6 @@
#include "stddef.h"
#include "nfapi_interface.h"
#include <nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h>
#define NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS 5
#define NFAPI_NR_MAX_NB_TCI_STATES_PDCCH 64
@@ -23,7 +22,6 @@
#define NFAPI_MAX_NUM_GROUPS 8
#define NFAPI_MAX_NUM_CB 8
/*
// Extension to the generic structures for single tlv values
typedef struct {
nfapi_tl_t tl;
@@ -34,7 +32,34 @@ typedef struct {
nfapi_tl_t tl;
uint32_t value;
} nfapi_uint32_tlv_t;
*/
typedef struct {
nfapi_tl_t tl;
int64_t value;
} nfapi_int64_tlv_t;
typedef struct {
nfapi_tl_t tl;
uint64_t value;
} nfapi_uint64_tlv_t;
typedef enum {
NFAPI_NR_DMRS_TYPE1=0,
NFAPI_NR_DMRS_TYPE2
} nfapi_nr_dmrs_type_e;
typedef struct {
/// Value: 0 -> 1, 0: Payload is carried directly in the value field, 1: Pointer to payload is in the value field
uint16_t tag;
/// Length of the actual payload in bytes, without the padding bytes Value: 0 → 65535
uint16_t length;
union {
uint32_t *ptr;
uint32_t direct[16384];
} value;
} nfapi_nr_tx_data_request_tlv_t;
// 2019.8
// SCF222_5G-FAPI_PHY_SPI_Specificayion.pdf Section 3.2
@@ -68,12 +93,6 @@ typedef enum {
//3.3.1 PARAM
typedef struct {
nfapi_tl_t tl;
uint16_t value;
} nfapi_nr_param_tlv_t;
//same with nfapi_param_request_t
typedef struct {
nfapi_p4_p5_message_header_t header;
@@ -86,12 +105,12 @@ typedef enum {
} nfapi_nr_param_errors_e;
typedef struct {
/*typedef struct {
nfapi_nr_param_errors_e error_code;
//Number of TLVs contained in the message body.
uint8_t number_of_tlvs;
nfapi_nr_param_tlv_t TLV;
} nfapi_nr_param_response_t;
} nfapi_nr_param_response_t;*/
//PARAM and CONFIG TLVs are used in the PARAM and CONFIG message exchanges, respectively
@@ -101,7 +120,7 @@ typedef struct {
//table 3-9
#define NFAPI_NR_PARAM_TLV_RELEASE_CAPABILITY_TAG 0x0001
#define NFAPI_NR_PARAM_TLV_RELEASE_CAPABILITY_TAG 0x0001
#define NFAPI_NR_PARAM_TLV_PHY_STATE_TAG 0x0002
#define NFAPI_NR_PARAM_TLV_SKIP_BLANK_DL_CONFIG_TAG 0x0003
#define NFAPI_NR_PARAM_TLV_SKIP_BLANK_UL_CONFIG_TAG 0x0004
@@ -158,123 +177,113 @@ typedef struct {
typedef struct
{
uint16_t release_capability; //TAG 0x0001
uint16_t phy_state;
uint8_t skip_blank_dl_config;
uint8_t skip_blank_ul_config;
uint16_t num_config_tlvs_to_report;
nfapi_nr_param_tlv_t* config_tlvs_to_report_list;
nfapi_uint16_tlv_t release_capability; //TAG 0x0001
nfapi_uint16_tlv_t phy_state;
nfapi_uint8_tlv_t skip_blank_dl_config;
nfapi_uint8_tlv_t skip_blank_ul_config;
nfapi_uint16_tlv_t num_config_tlvs_to_report;
nfapi_uint8_tlv_t* config_tlvs_to_report_list;
} nfapi_nr_cell_param_t;
//table 3-10 Carrier parameters
typedef struct
{
uint8_t cyclic_prefix;//TAG 0x0006
uint8_t supported_subcarrier_spacings_dl;
uint16_t supported_bandwidth_dl;
uint8_t supported_subcarrier_spacings_ul;
uint16_t supported_bandwidth_ul;
nfapi_uint8_tlv_t cyclic_prefix;//TAG 0x0006
nfapi_uint16_tlv_t supported_subcarrier_spacings_dl;
nfapi_uint16_tlv_t supported_bandwidth_dl;
nfapi_uint8_tlv_t supported_subcarrier_spacings_ul;
nfapi_uint16_tlv_t supported_bandwidth_ul;
} nfapi_nr_carrier_param_t;
//table 3-11 PDCCH parameters
typedef struct
{
uint8_t cce_mapping_type;
uint8_t coreset_outside_first_3_of_ofdm_syms_of_slot;
uint8_t coreset_precoder_granularity_coreset;
uint8_t pdcch_mu_mimo;
uint8_t pdcch_precoder_cycling;
uint8_t max_pdcch_per_slot;//TAG 0x0010
nfapi_uint8_tlv_t cce_mapping_type;
nfapi_uint8_tlv_t coreset_outside_first_3_of_ofdm_syms_of_slot;
nfapi_uint8_tlv_t coreset_precoder_granularity_coreset;
nfapi_uint8_tlv_t pdcch_mu_mimo;
nfapi_uint8_tlv_t pdcch_precoder_cycling;
nfapi_uint8_tlv_t max_pdcch_per_slot;//TAG 0x0010
} nfapi_nr_pdcch_param_t;
//table 3-12 PUCCH parameters
typedef struct
{
uint8_t pucch_formats;
uint8_t max_pucchs_per_slot;
nfapi_uint8_tlv_t pucch_formats;
nfapi_uint8_tlv_t max_pucchs_per_slot;
} nfapi_nr_pucch_param_t;
//table 3-13 PDSCH parameters
typedef struct
{
uint8_t pdsch_mapping_type;
uint8_t pdsch_allocation_types;
uint8_t pdsch_vrb_to_prb_mapping;
uint8_t pdsch_cbg;
uint8_t pdsch_dmrs_config_types;
uint8_t pdsch_dmrs_max_length;
uint8_t pdsch_dmrs_additional_pos;
uint8_t max_pdsch_tbs_per_slot;
uint8_t max_number_mimo_layers_pdsch;
uint8_t supported_max_modulation_order_dl;
uint8_t max_mu_mimo_users_dl;
uint8_t pdsch_data_in_dmrs_symbols;
uint8_t premption_support;//TAG 0x001F
uint8_t pdsch_non_slot_support;
nfapi_uint8_tlv_t pdsch_mapping_type;
nfapi_uint8_tlv_t pdsch_allocation_types;
nfapi_uint8_tlv_t pdsch_vrb_to_prb_mapping;
nfapi_uint8_tlv_t pdsch_cbg;
nfapi_uint8_tlv_t pdsch_dmrs_config_types;
nfapi_uint8_tlv_t pdsch_dmrs_max_length;
nfapi_uint8_tlv_t pdsch_dmrs_additional_pos;
nfapi_uint8_tlv_t max_pdsch_tbs_per_slot;
nfapi_uint8_tlv_t max_number_mimo_layers_pdsch;
nfapi_uint8_tlv_t supported_max_modulation_order_dl;
nfapi_uint8_tlv_t max_mu_mimo_users_dl;
nfapi_uint8_tlv_t pdsch_data_in_dmrs_symbols;
nfapi_uint8_tlv_t premption_support;//TAG 0x001F
nfapi_uint8_tlv_t pdsch_non_slot_support;
} nfapi_nr_pdsch_param_t;
//table 3-14
typedef struct
{
uint8_t uci_mux_ulsch_in_pusch;
uint8_t uci_only_pusch;
uint8_t pusch_frequency_hopping;
uint8_t pusch_dmrs_config_types;
uint8_t pusch_dmrs_max_len;
uint8_t pusch_dmrs_additional_pos;
uint8_t pusch_cbg;
uint8_t pusch_mapping_type;
uint8_t pusch_allocation_types;
uint8_t pusch_vrb_to_prb_mapping;
//uint8 ? ↓ see table 3-14
uint8_t pusch_max_ptrs_ports;
uint8_t max_pduschs_tbs_per_slot;
uint8_t max_number_mimo_layers_non_cb_pusch;
uint8_t supported_modulation_order_ul;
uint8_t max_mu_mimo_users_ul;
uint8_t dfts_ofdm_support;
uint8_t pusch_aggregation_factor;//TAG 0x0031
nfapi_uint8_tlv_t uci_mux_ulsch_in_pusch;
nfapi_uint8_tlv_t uci_only_pusch;
nfapi_uint8_tlv_t pusch_frequency_hopping;
nfapi_uint8_tlv_t pusch_dmrs_config_types;
nfapi_uint8_tlv_t pusch_dmrs_max_len;
nfapi_uint8_tlv_t pusch_dmrs_additional_pos;
nfapi_uint8_tlv_t pusch_cbg;
nfapi_uint8_tlv_t pusch_mapping_type;
nfapi_uint8_tlv_t pusch_allocation_types;
nfapi_uint8_tlv_t pusch_vrb_to_prb_mapping;
nfapi_uint8_tlv_t pusch_max_ptrs_ports;
nfapi_uint8_tlv_t max_pduschs_tbs_per_slot;
nfapi_uint8_tlv_t max_number_mimo_layers_non_cb_pusch;
nfapi_uint8_tlv_t supported_modulation_order_ul;
nfapi_uint8_tlv_t max_mu_mimo_users_ul;
nfapi_uint8_tlv_t dfts_ofdm_support;
nfapi_uint8_tlv_t pusch_aggregation_factor;//TAG 0x0031
} nfapi_nr_pusch_param_t;
//table 3-15
typedef struct
{
uint8_t prach_long_formats;
uint8_t prach_short_formats;
uint8_t prach_restricted_sets;
uint8_t max_prach_fd_occasions_in_a_slot;
nfapi_uint8_tlv_t prach_long_formats;
nfapi_uint8_tlv_t prach_short_formats;
nfapi_uint8_tlv_t prach_restricted_sets;
nfapi_uint8_tlv_t max_prach_fd_occasions_in_a_slot;
} nfapi_nr_prach_param_t;
//table 3-16
typedef struct
{
uint8_t rssi_measurement_support;
nfapi_uint8_tlv_t rssi_measurement_support;
} nfapi_nr_measurement_param_t;
//-------------------------------------------//
//3.3.2 CONFIG
typedef struct {
nfapi_tl_t tl;
uint16_t value;
} nfapi_nr_config_tlv_t;
typedef struct {
uint8_t number_of_tlvs;
nfapi_nr_config_tlv_t tlv;
} nfapi_nr_config_request_scf_t;
typedef enum {
NFAPI_NR_CONFIG_MSG_OK = 0,
NFAPI_NR_CONFIG_MSG_INVALID_CONFIG //The configuration provided has missing mandatory TLVs, or TLVs that are invalid or unsupported in this state.
NFAPI_NR_CONFIG_MSG_INVALID_CONFIG //The configuration provided has missing mandatory TLVs, or TLVs that are invalid or unsupported in this state.
} nfapi_nr_config_errors_e;
typedef struct {
/*typedef struct {
nfapi_nr_config_errors_e error_code;
uint8_t number_of_invalid_tlvs_that_can_only_be_configured_in_idle;
uint8_t unmber_of_missing_tlvs;
@@ -284,7 +293,7 @@ typedef struct {
nfapi_nr_config_tlv_t* tlv_invalid_running_list;
nfapi_nr_config_tlv_t* tlv_missing_list;
} nfapi_nr_config_response_t;
} nfapi_nr_config_response_t;*/
//nfapi_nr_config_tlv_format_t carrier config ~ precoding config:
@@ -337,34 +346,34 @@ typedef struct {
//table 3-21
typedef struct
{
uint16_t dl_bandwidth;//Carrier bandwidth for DL in MHz [38.104, sec 5.3.2] Values: 5, 10, 15, 20, 25, 30, 40,50, 60, 70, 80,90,100,200,400
uint32_t dl_frequency; //Absolute frequency of DL point A in KHz [38.104, sec5.2 and 38.211 sec 4.4.4.2] Value: 450000 -> 52600000
uint16_t dl_k0[5];//𝑘_{0}^{𝜇} for each of the numerologies [38.211, sec 5.3.1] Value: 0 ->23699
uint16_t dl_grid_size[5];//Grid size 𝑁_{𝑔𝑟𝑖𝑑}^{𝑠𝑖𝑧𝑒,𝜇} for each of the numerologies [38.211, sec 4.4.2] Value: 0->275 0 = this numerology not used
uint16_t num_tx_ant;//Number of Tx antennas
uint16_t uplink_bandwidth;//Carrier bandwidth for UL in MHz. [38.104, sec 5.3.2] Values: 5, 10, 15, 20, 25, 30, 40,50, 60, 70, 80,90,100,200,400
uint32_t uplink_frequency;//Absolute frequency of UL point A in KHz [38.104, sec5.2 and 38.211 sec 4.4.4.2] Value: 450000 -> 52600000
uint16_t ul_k0[5];//𝑘0 𝜇 for each of the numerologies [38.211, sec 5.3.1] Value: : 0 ->23699
uint16_t ul_grid_size[5];//Grid size 𝑁𝑔𝑟𝑖𝑑 𝑠𝑖𝑧𝑒,𝜇 for each of the numerologies [38.211, sec 4.4.2]. Value: 0->275 0 = this numerology not used
uint16_t num_rx_ant;//
uint8_t frequency_shift_7p5khz;//Indicates presence of 7.5KHz frequency shift. Value: 0 = false 1 = true
nfapi_uint16_tlv_t dl_bandwidth;//Carrier bandwidth for DL in MHz [38.104, sec 5.3.2] Values: 5, 10, 15, 20, 25, 30, 40,50, 60, 70, 80,90,100,200,400
nfapi_uint32_tlv_t dl_frequency; //Absolute frequency of DL point A in KHz [38.104, sec5.2 and 38.211 sec 4.4.4.2] Value: 450000 -> 52600000
nfapi_uint16_tlv_t dl_k0[5];//𝑘_{0}^{𝜇} for each of the numerologies [38.211, sec 5.3.1] Value: 0 ->23699
nfapi_uint16_tlv_t dl_grid_size[5];//Grid size 𝑁_{𝑔𝑟𝑖𝑑}^{𝑠𝑖𝑧𝑒,𝜇} for each of the numerologies [38.211, sec 4.4.2] Value: 0->275 0 = this numerology not used
nfapi_uint16_tlv_t num_tx_ant;//Number of Tx antennas
nfapi_uint16_tlv_t uplink_bandwidth;//Carrier bandwidth for UL in MHz. [38.104, sec 5.3.2] Values: 5, 10, 15, 20, 25, 30, 40,50, 60, 70, 80,90,100,200,400
nfapi_uint32_tlv_t uplink_frequency;//Absolute frequency of UL point A in KHz [38.104, sec5.2 and 38.211 sec 4.4.4.2] Value: 450000 -> 52600000
nfapi_uint16_tlv_t ul_k0[5];//𝑘0 𝜇 for each of the numerologies [38.211, sec 5.3.1] Value: : 0 ->23699
nfapi_uint16_tlv_t ul_grid_size[5];//Grid size 𝑁𝑔𝑟𝑖𝑑 𝑠𝑖𝑧𝑒,𝜇 for each of the numerologies [38.211, sec 4.4.2]. Value: 0->275 0 = this numerology not used
nfapi_uint16_tlv_t num_rx_ant;//
nfapi_uint8_tlv_t frequency_shift_7p5khz;//Indicates presence of 7.5KHz frequency shift. Value: 0 = false 1 = true
} nfapi_nr_carrier_config_t;
//table 3-22
typedef struct
{
uint8_t phy_cell_id;//Physical Cell ID, 𝑁_{𝐼𝐷}^{𝑐𝑒𝑙𝑙} [38.211, sec 7.4.2.1] Value: 0 ->1007
uint8_t frame_duplex_type;//Frame duplex type Value: 0 = FDD 1 = TDD
nfapi_uint8_tlv_t phy_cell_id;//Physical Cell ID, 𝑁_{𝐼𝐷}^{𝑐𝑒𝑙𝑙} [38.211, sec 7.4.2.1] Value: 0 ->1007
nfapi_uint8_tlv_t frame_duplex_type;//Frame duplex type Value: 0 = FDD 1 = TDD
} nfapi_nr_cell_config_t;
//table 3-23
typedef struct
{
uint32_t ss_pbch_power;//SSB Block Power Value: TBD (-60..50 dBm)
uint8_t bch_payload;//Defines option selected for generation of BCH payload, see Table 3-13 (v0.0.011 Value: 0: MAC generates the full PBCH payload 1: PHY generates the timing PBCH bits 2: PHY generates the full PBCH payload
uint8_t scs_common;//subcarrierSpacing for common, used for initial access and broadcast message. [38.211 sec 4.2] Value:0->3
nfapi_uint32_tlv_t ss_pbch_power;//SSB Block Power Value: TBD (-60..50 dBm)
nfapi_uint8_tlv_t bch_payload;//Defines option selected for generation of BCH payload, see Table 3-13 (v0.0.011 Value: 0: MAC generates the full PBCH payload 1: PHY generates the timing PBCH bits 2: PHY generates the full PBCH payload
nfapi_uint8_tlv_t scs_common;//subcarrierSpacing for common, used for initial access and broadcast message. [38.211 sec 4.2] Value:0->3
} nfapi_nr_ssb_config_t;
@@ -376,51 +385,51 @@ typedef struct
typedef struct
{
uint8_t num_prach_fd_occasions;
uint16_t prach_root_sequence_index;//Starting logical root sequence index, 𝑖, equivalent to higher layer parameter prach-RootSequenceIndex [38.211, sec 6.3.3.1] Value: 0 -> 837
uint8_t num_root_sequences;//Number of root sequences for a particular FD occasion that are required to generate the necessary number of preambles
uint16_t k1;//Frequency offset (from UL bandwidth part) for each FD. [38.211, sec 6.3.3.2] Value: from 0 to 272
uint8_t prach_zero_corr_conf;//PRACH Zero CorrelationZone Config which is used to dervive 𝑁𝑐𝑠 [38.211, sec 6.3.3.1] Value: from 0 to 15
uint8_t num_unused_root_sequences;//Number of unused sequences available for noise estimation per FD occasion. At least one unused root sequence is required per FD occasion.
uint8_t* unused_root_sequences_list;//Unused root sequence or sequences per FD occasion. Required for noise estimation.
nfapi_uint16_tlv_t prach_root_sequence_index;//Starting logical root sequence index, 𝑖, equivalent to higher layer parameter prach-RootSequenceIndex [38.211, sec 6.3.3.1] Value: 0 -> 837
nfapi_uint8_tlv_t num_root_sequences;//Number of root sequences for a particular FD occasion that are required to generate the necessary number of preambles
nfapi_uint16_tlv_t k1;//Frequency offset (from UL bandwidth part) for each FD. [38.211, sec 6.3.3.2] Value: from 0 to 272
nfapi_uint8_tlv_t prach_zero_corr_conf;//PRACH Zero CorrelationZone Config which is used to dervive 𝑁𝑐𝑠 [38.211, sec 6.3.3.1] Value: from 0 to 15
nfapi_uint8_tlv_t num_unused_root_sequences;//Number of unused sequences available for noise estimation per FD occasion. At least one unused root sequence is required per FD occasion.
nfapi_uint8_tlv_t* unused_root_sequences_list;//Unused root sequence or sequences per FD occasion. Required for noise estimation.
} nfapi_nr_num_prach_fd_occasions_t;
typedef struct
{
uint8_t prach_sequence_length;//RACH sequence length. Long or Short sequence length. Only short sequence length is supported for FR2. [38.211, sec 6.3.3.1] Value: 0 = Long sequence 1 = Short sequence
uint8_t prach_sub_c_spacing;//Subcarrier spacing of PRACH. [38.211 sec 4.2] Value:0->4
uint8_t restricted_set_config;//PRACH restricted set config Value: 0: unrestricted 1: restricted set type A 2: restricted set type B
uint8_t num_prach_fd_occasions;//Number of RACH frequency domain occasions. Corresponds to the parameter 𝑀 in [38.211, sec 6.3.3.2] which equals the higher layer parameter msg1FDM Value: 1,2,4,8
nfapi_uint8_tlv_t prach_sequence_length;//RACH sequence length. Only short sequence length is supported for FR2. [38.211, sec 6.3.3.1] Value: 0 = Long sequence 1 = Short sequence
nfapi_uint8_tlv_t prach_sub_c_spacing;//Subcarrier spacing of PRACH. [38.211 sec 4.2] Value:0->4
nfapi_uint8_tlv_t restricted_set_config;//PRACH restricted set config Value: 0: unrestricted 1: restricted set type A 2: restricted set type B
nfapi_uint8_tlv_t num_prach_fd_occasions;//Corresponds to the parameter 𝑀 in [38.211, sec 6.3.3.2] which equals the higher layer parameter msg1FDM Value: 1,2,4,8
nfapi_nr_num_prach_fd_occasions_t* num_prach_fd_occasions_list;
uint8_t ssb_per_rach;//SSB-per-RACH-occasion Value: 0: 1/8 1:1/4, 2:1/2 3:1 4:2 5:4, 6:8 7:16
uint8_t prach_multiple_carriers_in_a_band;//0 = disabled 1 = enabled
nfapi_uint8_tlv_t ssb_per_rach;//SSB-per-RACH-occasion Value: 0: 1/8 1:1/4, 2:1/2 3:1 4:2 5:4, 6:8 7:16
nfapi_uint8_tlv_t prach_multiple_carriers_in_a_band;//0 = disabled 1 = enabled
} nfapi_nr_prach_config_t;
//table 3-25
typedef struct
{
uint32_t ssb_mask;//Bitmap for actually transmitted SSB. MSB->LSB of first 32 bit number corresponds to SSB 0 to SSB 31 MSB->LSB of second 32 bit number corresponds to SSB 32 to SSB 63 Value for each bit: 0: not transmitted 1: transmitted
nfapi_uint32_tlv_t ssb_mask;//Bitmap for actually transmitted SSB. MSB->LSB of first 32 bit number corresponds to SSB 0 to SSB 31 MSB->LSB of second 32 bit number corresponds to SSB 32 to SSB 63 Value for each bit: 0: not transmitted 1: transmitted
} nfapi_nr_ssb_mask_size_2_t;
typedef struct
{
uint8_t beam_id[64];//BeamID for each SSB in SsbMask. For example, if SSB mask bit 26 is set to 1, then BeamId[26] will be used to indicate beam ID of SSB 26. Value: from 0 to 63
nfapi_uint8_tlv_t beam_id[64];//BeamID for each SSB in SsbMask. For example, if SSB mask bit 26 is set to 1, then BeamId[26] will be used to indicate beam ID of SSB 26. Value: from 0 to 63
} nfapi_nr_ssb_mask_size_64_t;
typedef struct
{
uint16_t ssb_offset_point_a;//Offset of lowest subcarrier of lowest resource block used for SS/PBCH block. Given in PRB [38.211, section 4.4.4.2] Value: 0->2199
uint8_t beta_pss;//PSS EPRE to SSS EPRE in a SS/PBCH block [38.213, sec 4.1] Values: 0 = 0dB
uint8_t ssb_period;//SSB periodicity in msec Value: 0: ms5 1: ms10 2: ms20 3: ms40 4: ms80 5: ms160
uint8_t ssb_subcarrier_offset;//ssbSubcarrierOffset or 𝑘𝑆𝑆𝐵 (38.211, section 7.4.3.1) Value: 0->31
uint32_t MIB;//MIB payload, where the 24 MSB are used and represent the MIB in [38.331 MIB IE] and represent 0 1 2 3 1 , , , ,..., A− a a a a a [38.212, sec 7.1.1]
nfapi_nr_ssb_mask_size_2_t* ssb_mask_size_2_list;//2
nfapi_nr_ssb_mask_size_64_t* ssb_mask_size_64_list;//64
uint8_t ss_pbch_multiple_carriers_in_a_band;//0 = disabled 1 = enabled
uint8_t multiple_cells_ss_pbch_in_a_carrier;//Indicates that multiple cells will be supported in a single carrier 0 = disabled 1 = enabled
nfapi_uint16_tlv_t ssb_offset_point_a;//Offset of lowest subcarrier of lowest resource block used for SS/PBCH block. Given in PRB [38.211, section 4.4.4.2] Value: 0->2199
nfapi_uint8_tlv_t beta_pss;//PSS EPRE to SSS EPRE in a SS/PBCH block [38.213, sec 4.1] Values: 0 = 0dB
nfapi_uint8_tlv_t ssb_period;//SSB periodicity in msec Value: 0: ms5 1: ms10 2: ms20 3: ms40 4: ms80 5: ms160
nfapi_uint8_tlv_t ssb_subcarrier_offset;//ssbSubcarrierOffset or 𝑘𝑆𝑆𝐵 (38.211, section 7.4.3.1) Value: 0->31
nfapi_uint32_tlv_t MIB;//MIB payload, where the 24 MSB are used and represent the MIB in [38.331 MIB IE] and represent 0 1 2 3 1 , , , ,..., A− a a a a a [38.212, sec 7.1.1]
nfapi_nr_ssb_mask_size_2_t ssb_mask_list[2];
nfapi_nr_ssb_mask_size_64_t* ssb_beam_id_list;//64
nfapi_uint8_tlv_t ss_pbch_multiple_carriers_in_a_band;//0 = disabled 1 = enabled
nfapi_uint8_tlv_t multiple_cells_ss_pbch_in_a_carrier;//Indicates that multiple cells will be supported in a single carrier 0 = disabled 1 = enabled
} nfapi_nr_ssb_table_t;
@@ -429,7 +438,7 @@ typedef struct
//?
typedef struct
{
uint8_t slot_config;//For each symbol in each slot a uint8_t value is provided indicating: 0: DL slot 1: UL slot 2: Guard slot
nfapi_uint8_tlv_t slot_config;//For each symbol in each slot a uint8_t value is provided indicating: 0: DL slot 1: UL slot 2: Guard slot
} nfapi_nr_max_num_of_symbol_per_slot_t;
@@ -441,7 +450,7 @@ typedef struct
typedef struct
{
uint8_t tdd_period;//DL UL Transmission Periodicity. Value:0: ms0p5 1: ms0p625 2: ms1 3: ms1p25 4: ms2 5: ms2p5 6: ms5 7: ms10
nfapi_uint8_tlv_t tdd_period;//DL UL Transmission Periodicity. Value:0: ms0p5 1: ms0p625 2: ms1 3: ms1p25 4: ms2 5: ms2p5 6: ms5 7: ms10 8: ms3 9: ms4
nfapi_nr_max_tdd_periodicity_t* max_tdd_periodicity_list;
} nfapi_nr_tdd_table_t;
@@ -449,10 +458,23 @@ typedef struct
//table 3-27
typedef struct
{
uint8_t rssi_measurement;//RSSI measurement unit. See Table 3-16 for RSSI definition. Value: 0: Do not report RSSI 1: dBm 2: dBFS
nfapi_uint8_tlv_t rssi_measurement;//RSSI measurement unit. See Table 3-16 for RSSI definition. Value: 0: Do not report RSSI 1: dBm 2: dBFS
} nfapi_nr_measurement_config_t;
typedef struct {
uint8_t num_tlv;
nfapi_nr_carrier_config_t carrier_config;
nfapi_nr_cell_config_t cell_config;
nfapi_nr_ssb_config_t ssb_config;
nfapi_nr_prach_config_t prach_config;
nfapi_nr_ssb_table_t ssb_table;
nfapi_nr_tdd_table_t tdd_table;
nfapi_nr_measurement_config_t measurement_config;
} nfapi_nr_config_request_scf_t;
//------------------------------//
//3.3.3 START
@@ -574,17 +596,29 @@ typedef struct
}nfapi_nr_tx_precoding_and_beamforming_number_of_prgs_t;
/*
//table 3-43
typedef struct
{
uint16_t num_prgs;/*Number of PRGs spanning this allocation.
Value : 1->275 */
uint16_t prg_size;/*Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275 */
uint16_t num_prgs;//Number of PRGs spanning this allocation. Value : 1->275
uint16_t prg_size;//Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275
//watchout: dig_bf_interfaces here, in table 3-53 it's dig_bf_interface
uint8_t dig_bf_interfaces;//Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255
nfapi_nr_tx_precoding_and_beamforming_number_of_prgs_t* prgs_list;//
}nfapi_nr_tx_precoding_and_beamforming_t;
*/
typedef struct {
/// Number of PRGs spanning this allocation. Value : 1->275
uint16_t numPRGs;
/// Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275
uint16_t prgSize;
/// Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255
uint8_t digBFInterfaces;
uint16_t PMIdx[275];
uint16_t *beamIdx[275];
} nfapi_nr_tx_precoding_and_beamforming_t;
//table 3-37
@@ -607,33 +641,154 @@ SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 */
} nfapi_nr_dl_dci_pdu_t;
//table 3-36
typedef struct
{
uint16_t bwp_size;//Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP Value: 1->275
uint16_t bwp_start;//bandwidth part start RB index from reference CRB [TS38.213 sec 12] Value: 0->274
uint8_t subcarrier_spacing;//subcarrierSpacing [TS38.211 sec 4.2] Value:0->4
uint8_t cyclic_prefix;//Cyclic prefix type [TS38.211 sec 4.2] 0: Normal; 1: Extended
//Coreset [TS38.211 sec 7.3.2.2]
uint8_t start_symbol_index;//Starting OFDM symbol for the CORESET Value: 0->13
uint8_t duration_symbols;/* Contiguous time duration of the CORESET in number of symbols. Corresponds to L1 parameter 𝑁𝑠𝑦𝑚𝑏 𝐶𝑂𝑅𝐸𝑆𝐸𝑇 [TS38.211 sec 7.3.2.2] Value: 1,2,3*/
uint8_t freq_domain_resource[6];/* Frequency domain resources. This is a bitmap defining non-overlapping groups of 6 PRBs in ascending order. [TS38.213 10.1]. Also, corresponds to L1 parameter N^{CORESET}_{RB} [TS38.211 sec 7.3.2.2]
Bitmap of uint8 array. 45 bits.*/
uint8_t cce_reg_mapping_type;/*CORESET-CCE-to-REG-mapping-type [TS38.211 sec 7.3.2.2] 0: non-interleaved 1: interleaved */
uint8_t reg_bundle_size;/*The number of REGs in a bundle. Must be 6 for
cceRegMappingType = nonInterleaved. For cceRegMappingType = interleaved, must belong to {2,6} if duration = 1,2 and must belong to {3,6} if
duration = 3. Corresponds to parameter L. [TS38.211 sec 7.3.2.2] Value: 2,3,6 */
uint8_t interleaver_size;//The interleaver size. For interleaved mapping belongs to {2,3,6} and for non-interleaved mapping is NA. Corresponds to parameter R. [TS38.211 sec 7.3.2.2] Value: 2,3,6
uint8_t core_set_type;//[TS38.211 sec 7.3.2.2 and sec 7.4.1.3.2] 0: CORESET is configured by the PBCH or SIB1 (subcarrier 0 of CRB0 for DMRS mapping) 1: otherwise (subcarrier 0 of CORESET)
uint16_t shift_index;//[TS38.211 sec 7.3.2.2] Not applicable for non-interleaved mapping. For interleaved mapping and a PDCCH transmitted in a CORESET configured by the PBCH or SIB1 this should be set to phy cell ID. Value: 10 bits Otherwise, for interleaved mapping this is set to 0-> max num of PRBs. Value 0-> 275
uint8_t precoder_granularity;//Granularity of precoding [TS38.211 sec 7.3.2.2] 0: sameAsRegBundle 1: allContiguousRBs
uint16_t num_dl_dci;//Number of DCIs in this CORESET. Value: 0->MaxDciPerSlot
nfapi_nr_dl_dci_pdu_t* dl_dci_list;
typedef struct {
/// Number of PRGs spanning this allocation. Value : 1->275
uint16_t numPRGs;
/// Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275
uint16_t prgSize;
/// Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255
uint8_t digBFInterfaces;
uint16_t PMIdx[275];
uint16_t *beamIdx[275];
} nr_beamforming_t;
#define MAX_DCI_CORESET 8
#define DCI_PAYLOAD_BYTE_LEN 8
typedef struct {
///Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP,Value: 1->275
uint16_t BWPSize;
///bandwidth part start RB index from reference CRB, [TS38.213 sec 12], Value: 0->274
uint16_t BWPStart;
///subcarrierSpacing [TS38.211 sec 4.2], Value:0->4
uint8_t SubcarrierSpacing;
///Cyclic prefix type [TS38.211 sec 4.2], 0: Normal; 1: Extended
uint8_t CyclicPrefix;
///Starting OFDM symbol for the CORESET, Value: 0->13
uint8_t StartSymbolIndex;
///Contiguous time duration of the CORESET in number of symbols. Corresponds to L1 parameter 𝑁𝑠𝑦𝑚𝑏_𝐶𝑂𝑅𝐸𝑆𝐸𝑇 [TS38.211 sec 7.3.2.2] Value: 1,2,3
uint8_t DurationSymbols;
///Frequency domain resources. This is a bitmap defining non-overlapping groups of 6 PRBs in ascending order. [TS38.213 10.1]. Also, corresponds to L1 parameter CORE SET RB N [TS38.211 sec 7.3.2.2] Bitmap of uint8 array. 45 bits.
uint8_t FreqDomainResource[6];
///CORESET-CCE-to-REG-mapping-type [TS38.211 sec 7.3.2.2] 0: non-interleaved 1: interleaved
uint8_t CceRegMappingType;
///The number of REGs in a bundle. Must be 6 for cceRegMappingType = nonInterleaved. For cceRegMappingType = interleaved, must belong to {2,6} if duration = 1,2 and must belong to {3,6} if duration = 3. Corresponds to parameter L. [TS38.211 sec 7.3.2.2] Value: 2,3,6
uint8_t RegBundleSize;
///The interleaver size. For interleaved mapping belongs to {2,3,6} and for non-interleaved mapping is NA. Corresponds to parameter R. [TS38.211 sec 7.3.2.2] Value: 2,3,6 CoreSetType
uint8_t InterleaverSize;
///[TS38.211 sec 7.3.2.2 and sec 7.4.1.3.2] 0: CORESET is configured by the PBCH or SIB1 (subcarrier 0 of CRB0 for DMRS mapping) 1: otherwise (subcarrier 0 of CORESET)
uint8_t CoreSetType;
///[TS38.211 sec 7.3.2.2] Not applicable for non-interleaved mapping. For interleaved mapping and a PDCCH transmitted in a CORESET configured by the PBCH or SIB1 this should be set to phy cell ID. Value: 10 bits Otherwise, for interleaved mapping this is set to 0-> max num of PRBs. Value 0-> 275
uint16_t ShiftIndex;
///Granularity of precoding [TS38.211 sec 7.3.2.2] Field Type Description 0: sameAsRegBundle 1: allContiguousRBs
uint8_t precoderGranularity;
///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot
uint16_t numDlDci;
///The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535.
uint16_t RNTI[MAX_DCI_CORESET];
///For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535
uint16_t ScramblingId[MAX_DCI_CORESET];
///For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535
uint16_t ScramblingRNTI[MAX_DCI_CORESET];
///CCE start Index used to send the DCI Value: 0->135
uint8_t CceIndex[MAX_DCI_CORESET];
///Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16
uint8_t AggregationLevel[MAX_DCI_CORESET];
///Precoding and Beamforming structure See Table 3-43
nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET];
///PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps
uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET];
///PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB
uint8_t powerControlOffsetSS[MAX_DCI_CORESET];
///The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BTYE_LEN*8
uint16_t PayloadSizeBits[MAX_DCI_CORESET];
///DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB
uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN];
} nfapi_nr_dl_tti_pdcch_pdu_rel15_t;
typedef struct {
uint16_t pduBitmap;
uint16_t rnti;
uint16_t pduIndex;
// BWP [TS38.213 sec 12]
/// Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP, Value: 1->275
uint16_t BWPSize;
/// bandwidth part start RB index from reference CRB [TS38.213 sec 12],Value: 0->274
uint16_t BWPStart;
/// subcarrierSpacing [TS38.211 sec 4.2], Value:0->4
uint8_t SubcarrierSpacing;
/// Cyclic prefix type [TS38.211 sec 4.2], 0: Normal; 1: Extended
uint8_t CyclicPrefix;
// Codeword information
/// Number of code words for this RNTI (UE), Value: 1 -> 2
uint8_t NrOfCodewords;
/// Target coding rate [TS38.212 sec 5.4.2.1 and 38.214 sec 5.1.3.1]. This is the number of information bits per 1024 coded bits expressed in 0.1 bit units
uint16_t targetCodeRate[2];
/// QAM modulation [TS38.212 sec 5.4.2.1 and 38.214 sec 5.1.3.1], Value: 2,4,6,8
uint8_t qamModOrder[2];
/// MCS index [TS38.214, sec 5.1.3.1], should match value sent in DCI Value : 0->31
uint8_t mcsIndex[2];
/// MCS-Table-PDSCH [TS38.214, sec 5.1.3.1] 0: notqam256, 1: qam256, 2: qam64LowSE
uint8_t mcsTable[2];
/// Redundancy version index [TS38.212, Table 5.4.2.1-2 and 38.214, Table 5.1.2.1-2], should match value sent in DCI Value : 0->3
uint8_t rvIndex[2];
/// Transmit block size (in bytes) [TS38.214 sec 5.1.3.2], Value: 0->65535
uint32_t TBSize[2];
/// dataScramblingIdentityPdsch [TS38.211, sec 7.3.1.1], It equals the higher-layer parameter Datascrambling-Identity if configured and the RNTI equals the C-RNTI, otherwise L2 needs to set it to physical cell id. Value: 0->65535
uint16_t dataScramblingId;
/// Number of layers [TS38.211, sec 7.3.1.3]. Value : 1->8
uint8_t nrOfLayers;
/// PDSCH transmission schemes [TS38.214, sec5.1.1] 0: Up to 8 transmission layers
uint8_t transmissionScheme;
/// Reference point for PDSCH DMRS "k" - used for tone mapping [TS38.211, sec 7.4.1.1.2] Resource block bundles [TS38.211, sec 7.3.1.6] Value: 0 -> 1 If 0, the 0 reference point for PDSCH DMRS is at Point A [TS38.211 sec 4.4.4.2]. Resource block bundles generated per sub-bullets 2 and 3 in [TS38.211, sec 7.3.1.6]. For sub-bullet 2, the start of bandwidth part must be set to the start of actual bandwidth part +NstartCORESET and the bandwidth of the bandwidth part must be set to the bandwidth of the initial bandwidth part. If 1, the DMRS reference point is at the lowest VRB/PRB of the allocation. Resource block bundles generated per sub-bullets 1 [TS38.211, sec 7.3.1.6]
uint8_t refPoint;
// DMRS [TS38.211 sec 7.4.1.1]
/// DMRS symbol positions [TS38.211, sec 7.4.1.1.2 and Tables 7.4.1.1.2-3 and 7.4.1.1.2-4] Bitmap occupying the 14 LSBs with: bit 0: first symbol and for each bit 0: no DMRS 1: DMRS
uint16_t dlDmrsSymbPos;
/// DL DMRS config type [TS38.211, sec 7.4.1.1.2] 0: type 1, 1: type 2
uint8_t dmrsConfigType;
/// DL-DMRS-Scrambling-ID [TS38.211, sec 7.4.1.1.2 ] If provided by the higher-layer and the PDSCH is scheduled by PDCCH with CRC scrambled by CRNTI or CS-RNTI, otherwise, L2 should set this to physical cell id. Value: 0->65535
uint16_t dlDmrsScramblingId;
/// DMRS sequence initialization [TS38.211, sec 7.4.1.1.2]. Should match what is sent in DCI 1_1, otherwise set to 0. Value : 0->1
uint8_t SCID;
/// Number of DM-RS CDM groups without data [TS38.212 sec 7.3.1.2.2] [TS38.214 Table 4.1-1] it determines the ratio of PDSCH EPRE to DM-RS EPRE. Value: 1->3
uint8_t numDmrsCdmGrpsNoData;
/// DMRS ports. [TS38.212 7.3.1.2.2] provides description between DCI 1-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used
uint16_t dmrsPorts;
// Pdsch Allocation in frequency domain [TS38.214, sec 5.1.2.2]
/// Resource Allocation Type [TS38.214, sec 5.1.2.2] 0: Type 0, 1: Type 1
uint8_t resourceAlloc;
/// For resource alloc type 0. TS 38.212 V15.0.x, 7.3.1.2.2 bitmap of RBs, 273 rounded up to multiple of 32. This bitmap is in units of VRBs. LSB of byte 0 of the bitmap represents the first RB of the bwp
uint8_t rbBitmap[36];
/// For resource allocation type 1. [TS38.214, sec 5.1.2.2.2] The starting resource block within the BWP for this PDSCH. Value: 0->274
uint16_t rbStart;
/// For resource allocation type 1. [TS38.214, sec 5.1.2.2.2] The number of resource block within for this PDSCH. Value: 1->275
uint16_t rbSize;
/// VRB-to-PRB-mapping [TS38.211, sec 7.3.1.6] 0: non-interleaved 1: interleaved with RB size 2 2: Interleaved with RB size 4
uint8_t VRBtoPRBMapping;
// Resource Allocation in time domain [TS38.214, sec 5.1.2.1]
/// Start symbol index of PDSCH mapping from the start of the slot, S. [TS38.214, Table 5.1.2.1-1] Value: 0->13
uint8_t StartSymbolIndex;
/// PDSCH duration in symbols, L [TS38.214, Table 5.1.2.1-1] Value: 1->14
uint8_t NrOfSymbols;
// PTRS [TS38.214, sec 5.1.6.3]
/// PT-RS antenna ports [TS38.214, sec 5.1.6.3] [TS38.211, table 7.4.1.2.2-1] Bitmap occupying the 6 LSBs with: bit 0: antenna port 1000 bit 5: antenna port 1005 and for each bit 0: PTRS port not used 1: PTRS port used
uint8_t PTRSPortIndex ;
/// PT-RS time density [TS38.214, table 5.1.6.3-1] 0: 1 1: 2 2: 4
uint8_t PTRSTimeDensity;
/// PT-RS frequency density [TS38.214, table 5.1.6.3-2] 0: 2 1: 4
uint8_t PTRSFreqDensity;
/// PT-RS resource element offset [TS38.211, table 7.4.1.2.2-1] Value: 0->3
uint8_t PTRSReOffset;
/// PT-RS-to-PDSCH EPRE ratio [TS38.214, table 4.1-2] Value :0->3
uint8_t nEpreRatioOfPDSCHToPTRS;
// Beamforming
nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming;
}nfapi_nr_dl_tti_pdsch_pdu_rel15_t;
} nfapi_nr_pdcch_pdu_t;
//for pdsch_pdu:
/*
typedef struct
{
uint16_t target_code_rate;//
@@ -693,31 +848,32 @@ typedef struct
uint32_t dl_tb_crc;//TB CRC: to be used in the last CB, applicable only if last CB is present
} nfapi_nr_dlsch_pdu_t;
*/
//for csi-rs_pdu:
//table 3-39
typedef struct
{
uint16_t bwp_size;//
uint16_t bwp_start;//
uint8_t subcarrier_spacing;//
uint8_t cyclic_prefix;//
uint16_t start_rb;
uint16_t nr_of_rbs;
uint8_t csi_type;//Value: 0:TRS 1:CSI-RS NZP 2:CSI-RS ZP
uint8_t row;//Row entry into the CSI Resource location table. [TS38.211, sec 7.4.1.5.3 and table 7.4.1.5.3-1] Value: 1-18
uint16_t freq_domain;//Value: Up to the 12 LSBs, actual size is determined by the Row parameter
uint8_t symb_l0;//The time domain location l0 and firstOFDMSymbolInTimeDomain Value: 0->13
uint8_t symb_l1;//
uint8_t cdm_type;
uint8_t freq_density;//The density field, p and comb offset (for dot5).0: dot5 (even RB), 1: dot5 (odd RB), 2: one, 3: three
uint16_t scramb_id;//ScramblingID of the CSI-RS [TS38.214, sec 5.2.2.3.1] Value: 0->1023
//tx power info
uint8_t power_control_offset;//Ratio of PDSCH EPRE to NZP CSI-RSEPRE Value :0->23 representing -8 to 15 dB in 1dB steps
uint8_t power_control_offset_ss;//Ratio of SSB/PBCH block EPRE to NZP CSI-RS EPRES 0: -3dB, 1: 0dB, 2: 3dB, 3: 6dB
uint16_t bwp_size;//
uint16_t bwp_start;//
uint8_t subcarrier_spacing;//
uint8_t cyclic_prefix;//
uint16_t start_rb;
uint16_t nr_of_rbs;
uint8_t csi_type;//Value: 0:TRS 1:CSI-RS NZP 2:CSI-RS ZP
uint8_t row;//Row entry into the CSI Resource location table. [TS38.211, sec 7.4.1.5.3 and table 7.4.1.5.3-1] Value: 1-18
uint16_t freq_domain;//Value: Up to the 12 LSBs, actual size is determined by the Row parameter
uint8_t symb_l0;//The time domain location l0 and firstOFDMSymbolInTimeDomain Value: 0->13
uint8_t symb_l1;//
uint8_t cdm_type;
uint8_t freq_density;//The density field, p and comb offset (for dot5).0: dot5 (even RB), 1: dot5 (odd RB), 2: one, 3: three
uint16_t scramb_id;//ScramblingID of the CSI-RS [TS38.214, sec 5.2.2.3.1] Value: 0->1023
//tx power info
uint8_t power_control_offset;//Ratio of PDSCH EPRE to NZP CSI-RSEPRE Value :0->23 representing -8 to 15 dB in 1dB steps
uint8_t power_control_offset_ss;//Ratio of SSB/PBCH block EPRE to NZP CSI-RS EPRES 0: -3dB, 1: 0dB, 2: 3dB, 3: 6dB
} nfapi_nr_csi_rs_pdu_t;
} nfapi_nr_dl_tti_csi_rs_pdu_rel15_t;
//for ssb_pdu:
@@ -744,27 +900,85 @@ typedef struct
} nfapi_nr_bch_payload_t;
typedef struct
{
uint16_t phys_cell_id;//0~1007
uint8_t beta_pss;//PSS EPRE to SSS EPRE in a SS/PBCH block 0 = 0dB 1 = 3dB
uint8_t ssb_block_index;//SS/PBCH block index within a SSB burst set. Required for PBCH DMRS scrambling. Value: 0->63 (Lmax)
uint8_t ssb_subcarrier_offset;//
uint16_t ssb_offset_point_a;//Offset of lowest subcarrier of lowest resource block used for SS/PBCH block. Value: 0->2199
uint8_t bch_payload_flag;//A value indicating how the BCH payload is generated. This should match the PARAM/CONFIG TLVs. Value: 0: MAC generates the full PBCH payload, see Table 3-41, where bchPayload has 31 bits 1: PHY generates the timing PBCH bits, see Table 3-41, where the bchPayload has 24 bits 2: PHY generates the full PBCH payload
nfapi_nr_bch_payload_t bch_payload;
typedef struct {
/// Physical Cell ID Value 0~>1007
uint16_t PhysCellId;
///PSS EPRE to SSS EPRE in a SS/PBCH block 0 = 0dB 1 = 3dB
uint8_t BetaPss;
///SS/PBCH block index within a SSB burst set. Required for PBCH DMRS scrambling. Value: 0->63 (Lmax)
uint8_t SsbBlockIndex;
/// ssbSubcarrierOffset or 𝑘𝑆𝑆𝐵 (TS38.211, section 7.4.3.1) Value: 0->31
uint8_t SsbSubcarrierOffset;
///Offset of lowest subcarrier of lowest resource block used for SS/PBCH block. Value: 0->2199
uint16_t ssbOffsetPointA;
/// A value indicating how the BCH payload is generated. This should match the PARAM/CONFIG TLVs. Value: 0: MAC generates the full PBCH payload, see Table 3-41, where bchPayload has 31 bits 1: PHY generates the timing PBCH bits, see Table 3-41, where the bchPayload has 24 bits 2: PHY generates the full PBCH payload
uint8_t bchPayloadFlag;
uint32_t bchPayload;
nfapi_nr_tx_precoding_and_beamforming_t precoding_and_beamforming;
} nfapi_nr_dl_tti_ssb_pdu_rel15_t;
} nfapi_nr_ssb_pdu_t;
typedef struct {
nfapi_nr_dl_tti_ssb_pdu_rel15_t ssb_pdu_rel15;
} nfapi_nr_dl_tti_ssb_pdu;
typedef struct {
nfapi_nr_dl_tti_csi_rs_pdu_rel15_t csi_rs_pdu_rel15;
} nfapi_nr_dl_tti_csi_rs_pdu;
typedef struct {
nfapi_nr_dl_tti_pdsch_pdu_rel15_t pdsch_pdu_rel15;
} nfapi_nr_dl_tti_pdsch_pdu;
typedef struct {
nfapi_nr_dl_tti_pdcch_pdu_rel15_t pdcch_pdu_rel15;
} nfapi_nr_dl_tti_pdcch_pdu;
typedef struct {
uint16_t PDUType;
uint16_t PDUSize;
union {
nfapi_nr_dl_tti_pdcch_pdu pdcch_pdu;
nfapi_nr_dl_tti_pdsch_pdu pdsch_pdu;
nfapi_nr_dl_tti_csi_rs_pdu csi_rs_pdu;
nfapi_nr_dl_tti_ssb_pdu ssb_pdu;
};
} nfapi_nr_dl_tti_request_pdu_t;
#define NFAPI_NR_MAX_DL_TTI_PDUS 32
typedef struct {
/// Number of PDUs that are included in this message. All PDUs in the message are numbered in order. Value 0 -> 255
uint8_t nPDUs;
/// Number of UEs in the Group included in this message. Value 0 -> 255
uint8_t nGroup;
/// List containing PDUs
nfapi_nr_dl_tti_request_pdu_t dl_tti_pdu_list[NFAPI_NR_MAX_DL_TTI_PDUS];
/// Number of UE in this group. For SU-MIMO, one group includes one UE only. For MU-MIMO, one group includes up to 12 UEs. Value 1 -> 12
uint8_t nUe[256];
/// This value is an index for number of PDU identified by nPDU in this message Value: 0 -> 255
uint8_t PduIdx[256][12];
} nfapi_nr_dl_tti_request_body_t;
typedef struct {
nfapi_p7_message_header_t header;
/// System Frame Number (0-1023)
uint16_t SFN;
/// Slot number (0-319)
uint16_t Slot;
nfapi_nr_dl_tti_request_body_t dl_tti_request_body;
nfapi_vendor_extension_tlv_t vendor_extension;
} nfapi_nr_dl_tti_request_t;
/*
typedef struct
{
nfapi_nr_pdcch_pdu_t* pdcch_pdu;
nfapi_nr_dlsch_pdu_t* dlsch_pdu;//pdsch_pdu;
nfapi_nr_csi_rs_pdu_t* csi_rs_pdu;
nfapi_nr_ssb_pdu_t* ssb_pdu;
nfapi_nr_dl_tti_pdcch_pdu* pdcch_pdu;
nfapi_nr_dl_tti_pdsch_pdu* pdsch_pdu;
nfapi_nr_dl_tti_csi_rs_pdu_t* csi_rs_pdu;
nfapi_nr_dl_tti_ssb_pdu_t* ssb_pdu;
} nfapi_nr_dl_pdu_configuration_t;
*/
/*
typedef struct
{
uint16_t pdu_type;//0: PDCCH PDU 1: PDSCH PDU 2: CSI-RS PDU 3: SSB PDU,
@@ -772,6 +986,7 @@ typedef struct
nfapi_nr_dl_pdu_configuration_t* dl_pdu_configuration;
} nfapi_nr_dl_tti_request_number_of_pdus_t;
typedef struct
{
@@ -796,9 +1011,10 @@ typedef struct {
nfapi_nr_dl_tti_request_number_of_groups_t* groups_list;
} nfapi_nr_dl_tti_request_t;
*/
// Section 3.4.3 ul_tti_request
//for prach_pdu:
typedef struct
{
@@ -906,10 +1122,10 @@ typedef struct
uint16_t data_scrambling_id;
uint8_t nrOfLayers;
//DMRS
uint8_t ul_dmrs_symb_pos;
uint16_t ul_dmrs_symb_pos;
uint8_t dmrs_config_type;
uint16_t ul_dmrs_scrambling_id;
uint8_t scid;//
uint8_t scid;
uint8_t num_dmrs_cdm_grps_no_data;
uint16_t dmrs_ports;//DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used
//Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2]
@@ -1016,6 +1232,13 @@ typedef struct
//
typedef enum {
NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE = 0,
NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE = 1,
NFAPI_NR_DL_TTI_CSI_RS_PDU_TYPE = 2,
NFAPI_NR_DL_TTI_SSB_PDU_TYPE = 3,
} nfapi_nr_dl_tti_pdu_type_e;
typedef enum {
NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE=0,
NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE,
@@ -1051,8 +1274,8 @@ typedef struct
} nfapi_nr_ul_tti_request_number_of_groups_t;
typedef struct {
uint16_t sfn; //0->1023
uint16_t slot;//0->319
uint16_t SFN; //0->1023
uint16_t Slot;//0->319
uint8_t n_pdus;//Number of PDUs that are included in this message. All PDUs in the message are numbered in order. Value 0 -> 255
uint8_t rach_present;//Indicates if a RACH PDU will be included in this message. 0: no RACH in this slot 1: RACH in this slot
uint8_t n_ulsch;//Number of ULSCH PDUs that are included in this message.
@@ -1060,13 +1283,13 @@ typedef struct {
uint8_t n_group;//Number of UE Groups included in this message. Value 0 -> 8
nfapi_nr_ul_tti_request_number_of_pdus_t pdus_list[NFAPI_MAX_NUM_UL_PDU];
nfapi_nr_ul_tti_request_number_of_groups_t groups_list[NFAPI_MAX_NUM_GROUPS];
} nfapi_nr_ul_tti_request_t;
//3.4.4 ul_dci_request
//table 3-54
/*
typedef struct
{
uint16_t pdu_type;//0: PDCCH PDU
@@ -1083,6 +1306,25 @@ typedef struct
nfapi_nr_ul_dci_request_number_of_pdus_t* pdu_list;
} nfapi_nr_ul_dci_request_t;
*/
// normally one PDU per coreset per BWP
#define NFAPI_NR_MAX_UL_DCI_PDUS 4
typedef struct {
/// only possible value 0: PDCCH PDU
uint16_t PDUType;
///Size of the PDU control information (in bytes). This length value includes the 4 bytes required for the PDU type and PDU size parameters. Value 0 -> 65535
uint16_t PDUSize;
nfapi_nr_dl_tti_pdcch_pdu pdcch_pdu;
} nfapi_nr_ul_dci_request_pdus_t;
typedef struct {
uint16_t SFN;
uint16_t Slot;
uint8_t numPdus;
nfapi_nr_ul_dci_request_pdus_t ul_dci_pdu_list[NFAPI_NR_MAX_UL_DCI_PDUS];
} nfapi_nr_ul_dci_request_t;
//3.4.5 slot_errors
typedef enum {
@@ -1099,6 +1341,7 @@ typedef enum {
} nfapi_nr_slot_errors_dl_tti_e;
typedef enum {
NFAPI_NR_SLOT_UL_DCI_MSG_INVALID_STATE,
NFAPI_NR_SLOT_UL_DCI_MSG_INVALID_SFN,
@@ -1109,23 +1352,23 @@ typedef enum {
//3.4.6 tx_data_request
//table 3-58
#define NFAPI_NR_MAX_TX_REQUEST_TLV 2
typedef struct
{
uint16_t pdu_length;
uint16_t pdu_index;
uint32_t num_tlv;
//! fixme
nfapi_int32_tlv_t* tlvs; //nfapi_int32_tlv_t tlvs[num_tlv]
uint16_t PDU_length;
uint16_t PDU_index;
uint32_t num_TLV;
nfapi_nr_tx_data_request_tlv_t TLVs[NFAPI_NR_MAX_TX_REQUEST_TLV];
} nfapi_nr_pdu_t;
#define NFAPI_NR_MAX_TX_REQUEST_PDUS 16
typedef struct
{
uint16_t sfn;
uint16_t slot;
uint16_t number_of_pdus;
nfapi_nr_pdu_t* pdu_list;
uint16_t SFN;
uint16_t Slot;
uint16_t Number_of_PDUs;
nfapi_nr_pdu_t pdu_list[NFAPI_NR_MAX_TX_REQUEST_PDUS];
} nfapi_nr_tx_data_request_t;