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very big merge with merged develop, basic test done

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This commit is contained in:
laurent
2020-01-30 17:10:36 +01:00
parent c8d28f5254 4eaadf8d82
commit 8d9d80ee37
784 changed files with 1098575 additions and 26905 deletions
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nfapi/oai_integration/nfapi_vnf.c
+21 -2
View File
@@ -31,7 +31,7 @@
#include <netinet/in.h>
#include <arpa/inet.h>
#include "nfapi_interface.h"
#include "nfapi_nr_interface.h"
#include "nfapi_vnf_interface.h"
#include "nfapi.h"
#include "vendor_ext.h"
@@ -1168,7 +1168,26 @@ int oai_nfapi_dl_config_req(nfapi_dl_config_request_t *dl_config_req) {
return retval;
}
int oai_nfapi_tx_req(nfapi_tx_request_t *tx_req) {
int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req)
{
nfapi_vnf_p7_config_t *p7_config = vnf.p7_vnfs[0].config;
dl_config_req->header.phy_id = 1; // DJP HACK TODO FIXME - need to pass this around!!!!
int retval = nfapi_vnf_p7_nr_dl_config_req(p7_config, dl_config_req);
dl_config_req->dl_config_request_body.number_dci = 0;
dl_config_req->dl_config_request_body.number_pdu = 0;
dl_config_req->dl_config_request_body.number_pdsch_rnti = 0;
if (retval!=0) {
LOG_E(PHY, "%s() Problem sending retval:%d\n", __FUNCTION__, retval);
}
return retval;
}
int oai_nfapi_tx_req(nfapi_tx_request_t *tx_req)
{
nfapi_vnf_p7_config_t *p7_config = vnf.p7_vnfs[0].config;
tx_req->header.phy_id = 1; // DJP HACK TODO FIXME - need to pass this around!!!!
tx_req->header.message_id = NFAPI_TX_REQUEST;
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h
+59
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@@ -0,0 +1,59 @@
#ifndef _FAPI_NR_UE_CONSTANTS_H_
#define _FAPI_NR_UE_CONSTANTS_H_
// constants defined by specification 38.331
#define FAPI_NR_MAX_NUM_DL_ALLOCATIONS 16
#define FAPI_NR_MAX_NUM_UL_ALLOCATIONS 16
#define FAPI_NR_MAX_NUM_SERVING_CELLS 32
#define FAPI_NR_MAX_NUM_ZP_CSI_RS_RESOURCE_PER_SET 16
#define FAPI_NR_MAX_NUM_CANDIDATE_BEAMS 16
#define FAPI_NR_MAX_RA_OCCASION_PER_CSIRS 64
/// RX_IND
#define FAPI_NR_RX_PDU_TYPE_MIB 0x01
#define FAPI_NR_RX_PDU_TYPE_SIB 0x02
#define FAPI_NR_RX_PDU_TYPE_DLSCH 0x03
#define FAPI_NR_DCI_IND 0x04
#define FAPI_NR_SIBS_MASK_SIB1 0x1
/// DCI_IND
#define FAPI_NR_DCI_TYPE_0_0 0x01
#define FAPI_NR_DCI_TYPE_0_1 0x02
#define FAPI_NR_DCI_TYPE_1_0 0x03
#define FAPI_NR_DCI_TYPE_1_1 0x04
#define FAPI_NR_DCI_TYPE_2_0 0x05
#define FAPI_NR_DCI_TYPE_2_1 0x06
#define FAPI_NR_DCI_TYPE_2_2 0x07
#define FAPI_NR_DCI_TYPE_2_3 0x08
/// TX_REQ
/// DL_CONFIG_REQ
#define FAPI_NR_DL_CONFIG_LIST_NUM 10
#define FAPI_NR_DL_CONFIG_TYPE_DCI 0x01
#define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02
#define CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01
#define CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02
#define PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE 0x01
#define PRECODER_GRANULARITY_ALL_CONTIGUOUS_RBS 0x02
/// UL_CONFIG_REQ
#define FAPI_NR_UL_CONFIG_LIST_NUM 10
#define FAPI_NR_UL_CONFIG_TYPE_PRACH 0x01
#define FAPI_NR_UL_CONFIG_TYPE_PUCCH 0x02
#define FAPI_NR_UL_CONFIG_TYPE_PUSCH 0x03
#define FAPI_NR_UL_CONFIG_TYPE_SRS 0x04
#endif
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
+923
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@@ -0,0 +1,923 @@
/*
* Copyright 2017 Cisco Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _FAPI_NR_UE_INTERFACE_H_
#define _FAPI_NR_UE_INTERFACE_H_
#include "stddef.h"
#include "platform_types.h"
#include "fapi_nr_ue_constants.h"
#include "PHY/impl_defs_nr.h"
/*
typedef unsigned int uint32_t;
typedef unsigned short uint16_t;
typedef unsigned char uint8_t;
typedef signed int int32_t;
typedef signed short int16_t;
typedef signed char int8_t;
*/
typedef struct {
uint8_t identifier_dci_formats ; // 0 IDENTIFIER_DCI_FORMATS:
uint8_t carrier_ind ; // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1:
uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND:
uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND:
uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND:
uint8_t short_messages ; // 9 SHORT_MESSAGES:
uint16_t freq_dom_resource_assignment_UL; // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
// (NOTE 1) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding
// is larger than the payload size of the DCI format 1_0 monitored in common search space
// the bitwidth of the frequency domain resource allocation field in the DCI format 0_0
// is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0
uint16_t freq_dom_resource_assignment_DL; // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
uint8_t time_dom_resource_assignment ; // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
// where I the number of entries in the higher layer parameter pusch-AllocationList
uint8_t vrb_to_prb_mapping ; // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
uint8_t prb_bundling_size_ind ; // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
uint8_t rate_matching_ind ; // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
uint8_t zp_csi_rs_trigger ; // 16 ZP_CSI_RS_TRIGGER:
uint8_t freq_hopping_flag ; // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
uint8_t tb1_mcs ; // 18 TB1_MCS:
uint8_t tb1_ndi ; // 19 TB1_NDI:
uint8_t tb1_rv ; // 20 TB1_RV:
uint8_t tb2_mcs ; // 21 TB2_MCS:
uint8_t tb2_ndi ; // 22 TB2_NDI:
uint8_t tb2_rv ; // 23 TB2_RV:
uint8_t mcs ; // 24 MCS:
uint8_t ndi ; // 25 NDI:
uint8_t rv ; // 26 RV:
uint8_t harq_process_number ; // 27 HARQ_PROCESS_NUMBER:
uint8_t dai ; // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
// 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
// 0 otherwise
uint8_t first_dai ; // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK
uint8_t second_dai ; // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
uint8_t tb_scaling ; // 31 TB_SCALING:
uint8_t tpc_pusch ; // 32 TPC_PUSCH:
uint8_t tpc_pucch ; // 33 TPC_PUCCH:
uint8_t pucch_resource_ind ; // 34 PUCCH_RESOURCE_IND:
uint8_t pdsch_to_harq_feedback_time_ind ; // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
uint8_t srs_resource_ind ; // 36 SRS_RESOURCE_IND:
uint8_t precod_nbr_layers ; // 37 PRECOD_NBR_LAYERS:
uint8_t antenna_ports ; // 38 ANTENNA_PORTS:
uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
uint8_t srs_request ; // 40 SRS_REQUEST:
uint8_t tpc_cmd ; // 41 TPC_CMD:
uint8_t csi_request ; // 42 CSI_REQUEST:
uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
uint8_t ptrs_dmrs ; // 45 PTRS_DMRS:
uint8_t beta_offset_ind ; // 46 BETA_OFFSET_IND:
uint8_t dmrs_seq_ini ; // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding
// is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
uint8_t ul_sch_ind ; // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
uint16_t padding_nr_dci ; // 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding
// is less than the payload size of the DCI format 1_0 monitored in common search space
// zeros shall be appended to the DCI format 0_0
// until the payload size equals that of the DCI format 1_0
uint8_t sul_ind_0_0 ; // 50 SUL_IND_0_0:
uint8_t ra_preamble_index ; // 51 RA_PREAMBLE_INDEX:
uint8_t sul_ind_1_0 ; // 52 SUL_IND_1_0:
uint8_t ss_pbch_index ; // 53 SS_PBCH_INDEX
uint8_t prach_mask_index ; // 54 PRACH_MASK_INDEX
uint8_t reserved_nr_dci ; // 55 RESERVED_NR_DCI
} fapi_nr_dci_pdu_rel15_t;
typedef struct {
uint8_t uci_format;
uint8_t uci_channel;
uint8_t harq_ack_bits;
uint32_t harq_ack;
uint8_t csi_bits;
uint32_t csi;
uint8_t sr_bits;
uint32_t sr;
} fapi_nr_uci_pdu_rel15_t;
typedef struct {
/// frequency_domain_resource;
//uint32_t rb_start;
//uint32_t rb_end;
uint64_t frequency_domain_resource;
uint16_t rb_offset;
uint8_t duration;
uint8_t cce_reg_mapping_type; // interleaved or noninterleaved
uint8_t cce_reg_interleaved_reg_bundle_size; // valid if CCE to REG mapping type is interleaved type
uint8_t cce_reg_interleaved_interleaver_size; // valid if CCE to REG mapping type is interleaved type
uint8_t cce_reg_interleaved_shift_index; // valid if CCE to REG mapping type is interleaved type
uint8_t precoder_granularity;
uint16_t pdcch_dmrs_scrambling_id;
uint8_t tci_state_pdcch;
uint8_t tci_present_in_dci;
} fapi_nr_coreset_t;
//
// Top level FAPI messages
//
//
// P7
//
typedef struct {
uint16_t rnti;
uint8_t dci_format;
// n_CCE index of first CCE for PDCCH reception
int n_CCE;
// N_CCE is L, or number of CCEs for DCI
int N_CCE;
fapi_nr_dci_pdu_rel15_t dci;
} fapi_nr_dci_indication_pdu_t;
///
typedef struct {
uint32_t sfn_slot;
uint16_t number_of_dcis;
fapi_nr_dci_indication_pdu_t dci_list[10];
} fapi_nr_dci_indication_t;
typedef struct {
uint32_t pdu_length;
uint8_t* pdu;
} fapi_nr_pdsch_pdu_t;
typedef struct {
uint8_t* pdu; // 3bytes
uint8_t additional_bits;
uint8_t ssb_index;
uint8_t ssb_length;
uint16_t cell_id;
} fapi_nr_mib_pdu_t;
typedef struct {
uint32_t pdu_length;
uint8_t* pdu;
uint32_t sibs_mask;
} fapi_nr_sib_pdu_t;
typedef struct {
uint8_t pdu_type;
union {
fapi_nr_pdsch_pdu_t pdsch_pdu;
fapi_nr_mib_pdu_t mib_pdu;
fapi_nr_sib_pdu_t sib_pdu;
};
} fapi_nr_rx_indication_body_t;
///
#define NFAPI_RX_IND_MAX_PDU 100
typedef struct {
uint32_t sfn_slot;
uint16_t number_pdus;
fapi_nr_rx_indication_body_t rx_indication_body[NFAPI_RX_IND_MAX_PDU];
} fapi_nr_rx_indication_t;
typedef struct {
uint8_t ul_cqi;
uint16_t timing_advance;
uint16_t rnti;
} fapi_nr_tx_config_t;
typedef struct {
uint16_t pdu_length;
uint16_t pdu_index;
uint8_t* pdu;
} fapi_nr_tx_request_body_t;
///
typedef struct {
uint32_t sfn_slot;
fapi_nr_tx_config_t tx_config;
uint16_t number_of_pdus;
fapi_nr_tx_request_body_t *tx_request_body;
} fapi_nr_tx_request_t;
typedef struct {
uint8_t preamble_index;
uint8_t prach_configuration_index;
uint16_t preamble_length;
uint8_t power_ramping_step;
uint16_t preamble_received_target_power;
uint8_t msg1_fdm;
uint8_t msg1_frequency_start;
uint8_t zero_correlation_zone_config;
uint8_t subcarrier_spacing;
uint8_t restrictedset_config;
uint16_t root_sequence_index;
uint16_t rsrp_threshold_ssb;
uint16_t rsrp_threshold_sul;
uint16_t prach_freq_offset;
} fapi_nr_ul_config_prach_pdu;
typedef struct {
pucch_format_nr_t format; /* format 0 1 2 3 4 */
uint8_t initialCyclicShift; /* x x */
uint8_t nrofSymbols; /* x x x x x */
uint8_t startingSymbolIndex; /* x x x x x */
uint8_t timeDomainOCC; /* x */
uint8_t nrofPRBs; /* x x */
uint16_t startingPRB; /* maxNrofPhysicalResourceBlocks = 275 */
uint8_t occ_length; /* x */
uint8_t occ_Index; /* x */
feature_status_t intraSlotFrequencyHopping;
uint16_t secondHopPRB;
/*
-- Enabling inter-slot frequency hopping when PUCCH Format 1, 3 or 4 is repeated over multiple slots.
-- The field is not applicable for format 2.
*/
feature_status_t interslotFrequencyHopping;
/*
-- Enabling 2 DMRS symbols per hop of a PUCCH Format 3 or 4 if both hops are more than X symbols when FH is enabled (X=4).
-- Enabling 4 DMRS sybmols for a PUCCH Format 3 or 4 with more than 2X+1 symbols when FH is disabled (X=4).
-- Corresponds to L1 parameter 'PUCCH-F3-F4-additional-DMRS' (see 38.213, section 9.2.1)
-- The field is not applicable for format 1 and 2.
*/
enable_feature_t additionalDMRS;
/*
-- Max coding rate to determine how to feedback UCI on PUCCH for format 2, 3 or 4
-- Corresponds to L1 parameter 'PUCCH-F2-maximum-coderate', 'PUCCH-F3-maximum-coderate' and 'PUCCH-F4-maximum-coderate'
-- (see 38.213, section 9.2.5)
-- The field is not applicable for format 1.
*/
PUCCH_MaxCodeRate_t maxCodeRate;
/*
-- Number of slots with the same PUCCH F1, F3 or F4. When the field is absent the UE applies the value n1.
-- Corresponds to L1 parameter 'PUCCH-F1-number-of-slots', 'PUCCH-F3-number-of-slots' and 'PUCCH-F4-number-of-slots'
-- (see 38.213, section 9.2.6)
-- The field is not applicable for format 2.
*/
uint8_t nrofSlots;
/*
-- Enabling pi/2 BPSK for UCI symbols instead of QPSK for PUCCH.
-- Corresponds to L1 parameter 'PUCCH-PF3-PF4-pi/2PBSK' (see 38.213, section 9.2.5)
-- The field is not applicable for format 1 and 2.
*/
feature_status_t pi2PBSK;
/*
-- Enabling simultaneous transmission of CSI and HARQ-ACK feedback with or without SR with PUCCH Format 2, 3 or 4
-- Corresponds to L1 parameter 'PUCCH-F2-Simultaneous-HARQ-ACK-CSI', 'PUCCH-F3-Simultaneous-HARQ-ACK-CSI' and
-- 'PUCCH-F4-Simultaneous-HARQ-ACK-CSI' (see 38.213, section 9.2.5)
-- When the field is absent the UE applies the value OFF
-- The field is not applicable for format 1.
*/
enable_feature_t simultaneousHARQ_ACK_CSI;
/*
-- Configuration of group- and sequence hopping for all the PUCCH formats 0, 1, 3 and 4. "neither" implies neither group
-- or sequence hopping is enabled. "enable" enables group hopping and disables sequence hopping. "disable"” disables group
-- hopping and enables sequence hopping. Corresponds to L1 parameter 'PUCCH-GroupHopping' (see 38.211, section 6.4.1.3)
pucch-GroupHopping ENUMERATED { neither, enable, disable },
*/
pucch_GroupHopping_t pucch_GroupHopping;
/*
-- Cell-Specific scrambling ID for group hoppping and sequence hopping if enabled.
-- Corresponds to L1 parameter 'HoppingID' (see 38.211, section 6.3.2.2)
hoppingId BIT STRING (SIZE (10)) OPTIONAL, -- Need R
*/
uint16_t hoppingId;
/*
-- Power control parameter P0 for PUCCH transmissions. Value in dBm. Only even values (step size 2) allowed.
-- Corresponds to L1 parameter 'p0-nominal-pucch' (see 38.213, section 7.2)
p0-nominal INTEGER (-202..24) OPTIONAL, -- Need R
*/
int8_t p0_nominal;
int8_t deltaF_PUCCH_f[NUMBER_PUCCH_FORMAT_NR];
uint8_t p0_PUCCH_Id; /* INTEGER (1..8) */
int8_t p0_PUCCH_Value;
// pathlossReferenceRSs SEQUENCE (SIZE (1..maxNrofPUCCH-PathlossReferenceRSs)) OF PUCCH-PathlossReferenceRS OPTIONAL, -- Need M
int8_t twoPUCCH_PC_AdjustmentStates;
} fapi_nr_ul_config_pucch_pdu;
typedef enum {pusch_freq_hopping_disabled = 0 , pusch_freq_hopping_enabled = 1}pusch_freq_hopping_t;
typedef struct{
uint8_t aperiodicSRS_ResourceTrigger;
} fapi_nr_ul_srs_config_t;
typedef struct {
uint8_t bandwidth_part_ind;
uint16_t number_rbs;
uint16_t start_rb;
uint8_t frame_offset;
uint16_t number_symbols;
uint16_t start_symbol;
pusch_freq_hopping_t pusch_freq_hopping;
uint8_t mcs;
uint8_t ndi;
uint8_t rv;
uint8_t harq_process_nbr;
int8_t accumulated_delta_PUSCH;
int8_t absolute_delta_PUSCH;
uint8_t n_layers;
uint8_t tpmi;
uint8_t n_dmrs_cdm_groups;
uint8_t dmrs_ports[4];
uint8_t n_front_load_symb;
fapi_nr_ul_srs_config_t srs_config;
uint8_t csi_reportTriggerSize;
uint8_t maxCodeBlockGroupsPerTransportBlock;
uint8_t ptrs_dmrs_association_port;
uint8_t beta_offset_ind;
} fapi_nr_ul_config_pusch_pdu_rel15_t;
typedef struct {
uint16_t rnti;
fapi_nr_ul_config_pusch_pdu_rel15_t ulsch_pdu_rel15;
} fapi_nr_ul_config_pusch_pdu;
typedef struct {
} fapi_nr_ul_config_srs_pdu;
typedef struct {
uint8_t pdu_type;
union {
fapi_nr_ul_config_prach_pdu prach_config_pdu;
fapi_nr_ul_config_pucch_pdu pucch_config_pdu;
fapi_nr_ul_config_pusch_pdu ulsch_config_pdu;
fapi_nr_ul_config_srs_pdu srs_config_pdu;
};
} fapi_nr_ul_config_request_pdu_t;
typedef struct {
uint32_t sfn_slot;
uint8_t number_pdus;
fapi_nr_ul_config_request_pdu_t ul_config_list[FAPI_NR_UL_CONFIG_LIST_NUM];
} fapi_nr_ul_config_request_t;
typedef struct {
uint16_t rnti;
fapi_nr_coreset_t coreset;
uint16_t N_RB_BWP;
uint32_t duration;
uint8_t number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
uint16_t monitoring_symbols_within_slot;
// DCI foramt-specific
uint8_t format_2_0_number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
uint8_t format_2_3_monitorying_periodicity;
uint8_t format_2_3_number_of_candidates;
} fapi_nr_dl_config_dci_dl_pdu_rel15_t;
typedef struct {
fapi_nr_dl_config_dci_dl_pdu_rel15_t dci_config_rel15;
} fapi_nr_dl_config_dci_pdu;
typedef struct{
uint8_t aperiodicSRS_ResourceTrigger;
} fapi_nr_dl_srs_config_t;
typedef enum{vrb_to_prb_mapping_non_interleaved = 0, vrb_to_prb_mapping_interleaved = 1} vrb_to_prb_mapping_t;
//typedef fapi_nr_dci_pdu_rel15_t fapi_nr_dl_config_dlsch_pdu_rel15_t;
typedef struct {
uint8_t bandwidth_part_ind;
uint16_t number_rbs;
uint16_t start_rb;
uint8_t frame_offset;
uint16_t number_symbols;
uint16_t start_symbol;
uint8_t prb_bundling_size_ind;
uint8_t rate_matching_ind;
uint8_t zp_csi_rs_trigger;
uint8_t mcs;
uint8_t ndi;
uint8_t rv;
uint8_t tb2_mcs;
uint8_t tb2_ndi;
uint8_t tb2_rv;
uint8_t harq_process_nbr;
vrb_to_prb_mapping_t vrb_to_prb_mapping;
uint8_t dai;
double scaling_factor_S;
int8_t accumulated_delta_PUCCH;
uint8_t pucch_resource_id;
uint8_t pdsch_to_harq_feedback_time_ind;
uint8_t n_dmrs_cdm_groups;
uint8_t dmrs_ports[10];
uint8_t n_front_load_symb;
uint8_t tci_state;
fapi_nr_dl_srs_config_t srs_config;
uint8_t cbgti;
uint8_t codeBlockGroupFlushIndicator;
// to be check the fields needed to L1 with NR_DL_UE_HARQ_t and NR_UE_DLSCH_t
} fapi_nr_dl_config_dlsch_pdu_rel15_t;
typedef struct {
uint16_t rnti;
fapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_config_rel15;
} fapi_nr_dl_config_dlsch_pdu;
typedef struct {
uint8_t pdu_type;
union {
fapi_nr_dl_config_dci_pdu dci_config_pdu;
fapi_nr_dl_config_dlsch_pdu dlsch_config_pdu;
};
} fapi_nr_dl_config_request_pdu_t;
typedef struct {
uint32_t sfn_slot;
uint8_t number_pdus;
fapi_nr_dl_config_request_pdu_t dl_config_list[FAPI_NR_DL_CONFIG_LIST_NUM];
} fapi_nr_dl_config_request_t;
//
// P5
//
typedef struct {
fapi_nr_coreset_t coreset;
uint8_t monitoring_slot_peridicity;
uint8_t monitoring_slot_offset;
uint16_t duration;
uint16_t monitoring_symbols_within_slot;
uint8_t number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
uint8_t dci_2_0_number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
uint8_t dci_2_3_monitorying_periodicity;
uint8_t dci_2_3_number_of_candidates;
} fapi_nr_search_space_t;
typedef struct {
fapi_nr_search_space_t search_space_sib1;
fapi_nr_search_space_t search_space_others_sib;
fapi_nr_search_space_t search_space_paging;
//fapi_nr_coreset_t coreset_ra; // common coreset
fapi_nr_search_space_t search_space_ra;
} fapi_nr_pdcch_config_common_t;
typedef struct {
uint8_t k0;
uint8_t mapping_type;
uint8_t symbol_starting;
uint8_t symbol_length;
} fapi_nr_pdsch_time_domain_resource_allocation_t;
typedef struct {
fapi_nr_pdsch_time_domain_resource_allocation_t allocation_list[FAPI_NR_MAX_NUM_DL_ALLOCATIONS];
} fapi_nr_pdsch_config_common_t;
typedef struct {
uint8_t prach_configuration_index;
uint8_t msg1_fdm;
uint8_t msg1_frequency_start;
uint8_t zero_correlation_zone_config;
uint8_t preamble_received_target_power;
uint8_t preamble_transmission_max;
uint8_t power_ramping_step;
uint8_t ra_window_size;
uint8_t total_number_of_preamble;
uint8_t ssb_occasion_per_rach;
uint8_t cb_preamble_per_ssb;
uint8_t group_a_msg3_size;
uint8_t group_a_number_of_preamble;
uint8_t group_b_power_offset;
uint8_t contention_resolution_timer;
uint8_t rsrp_threshold_ssb;
uint8_t rsrp_threshold_ssb_sul;
uint8_t prach_length; // l839, l139
uint8_t prach_root_sequence_index; // 0 - 837 for l839, 0 - 137 for l139
uint8_t msg1_subcarrier_spacing;
uint8_t restrictedset_config;
uint8_t msg3_transform_precoding;
} fapi_nr_rach_config_common_t;
typedef struct {
uint8_t k2;
uint8_t mapping_type;
uint8_t symbol_starting;
uint8_t symbol_length;
} fapi_nr_pusch_time_domain_resource_allocation_t;
typedef struct {
uint8_t group_hopping_enabled_transform_precoding;
fapi_nr_pusch_time_domain_resource_allocation_t allocation_list[FAPI_NR_MAX_NUM_UL_ALLOCATIONS];
uint8_t msg3_delta_preamble;
uint8_t p0_nominal_with_grant;
} fapi_nr_pusch_config_common_t;
typedef struct {
uint8_t pucch_resource_common;
uint8_t pucch_group_hopping;
uint8_t hopping_id;
uint8_t p0_nominal;
} fapi_nr_pucch_config_common_t;
typedef struct {
uint8_t subcarrier_spacing_common;
uint8_t ssb_subcarrier_offset;
uint8_t dmrs_type_a_position;
uint8_t pdcch_config_sib1;
uint8_t cell_barred;
uint8_t intra_frequency_reselection;
uint16_t system_frame_number;
uint8_t ssb_index;
uint8_t half_frame_bit;
} fapi_nr_pbch_config_t;
typedef struct {
fapi_nr_pdcch_config_common_t pdcch_config_common;
fapi_nr_pdsch_config_common_t pdsch_config_common;
} fapi_nr_dl_bwp_common_config_t;
typedef struct {
uint16_t int_rnti;
uint8_t time_frequency_set;
uint8_t dci_payload_size;
uint8_t serving_cell_id[FAPI_NR_MAX_NUM_SERVING_CELLS]; // interrupt configuration per serving cell
uint8_t position_in_dci[FAPI_NR_MAX_NUM_SERVING_CELLS]; // interrupt configuration per serving cell
} fapi_nr_downlink_preemption_t;
typedef struct {
uint8_t tpc_index;
uint8_t tpc_index_sul;
uint8_t target_cell;
} fapi_nr_pusch_tpc_command_config_t;
typedef struct {
uint8_t tpc_index_pcell;
uint8_t tpc_index_pucch_scell;
} fapi_nr_pucch_tpc_command_config_t;
typedef struct {
uint8_t starting_bit_of_format_2_3;
uint8_t feild_type_format_2_3;
} fapi_nr_srs_tpc_command_config_t;
typedef struct {
fapi_nr_downlink_preemption_t downlink_preemption;
fapi_nr_pusch_tpc_command_config_t tpc_pusch;
fapi_nr_pucch_tpc_command_config_t tpc_pucch;
fapi_nr_srs_tpc_command_config_t tpc_srs;
} fapi_nr_pdcch_config_dedicated_t;
typedef struct {
uint8_t dmrs_type;
uint8_t dmrs_addition_position;
uint8_t max_length;
uint16_t scrambling_id0;
uint16_t scrambling_id1;
uint8_t ptrs_frequency_density[2]; // phase tracking rs
uint8_t ptrs_time_density[3]; // phase tracking rs
uint8_t ptrs_epre_ratio; // phase tracking rs
uint8_t ptrs_resource_element_offset; // phase tracking rs
} fapi_nr_dmrs_downlink_config_t;
typedef struct {
uint8_t bwp_or_cell_level;
uint8_t pattern_type;
uint32_t resource_blocks[9]; // bitmaps type 275 bits
uint8_t slot_type; // bitmaps type one/two slot(s)
uint32_t symbols_in_resouece_block; // bitmaps type 14/28 bits
uint8_t periodic; // bitmaps type
uint32_t pattern[2]; // bitmaps type 2/4/5/8/10/20/40 bits
fapi_nr_coreset_t coreset; // coreset
uint8_t subcarrier_spacing;
uint8_t mode;
} fapi_nr_rate_matching_pattern_group_t;
typedef struct {
// resource mapping
uint8_t row; // row1/row2/row4/other
uint16_t frequency_domain_allocation; // 4/12/3/6 bits
uint8_t number_of_ports;
uint8_t first_ofdm_symbol_in_time_domain;
uint8_t first_ofdm_symbol_in_time_domain2;
uint8_t cdm_type;
uint8_t density; // .5/1/3
uint8_t density_dot5_type; // even/odd PRBs
uint8_t frequency_band_starting_rb; // freqBand
uint8_t frequency_band_number_of_rb; // freqBand
// periodicityAndOffset
uint8_t periodicity; // slot4/5/8/10/16/20/32/40/64/80/160/320/640
uint32_t offset; // 0..639 bits
} fapi_nr_zp_csi_rs_resource_t;
typedef struct {
uint16_t data_scrambling_id_pdsch;
fapi_nr_dmrs_downlink_config_t dmrs_dl_for_pdsch_mapping_type_a;
fapi_nr_dmrs_downlink_config_t dmrs_dl_for_pdsch_mapping_type_b;
uint8_t vrb_to_prb_interleaver;
uint8_t resource_allocation;
fapi_nr_pdsch_time_domain_resource_allocation_t allocation_list[FAPI_NR_MAX_NUM_DL_ALLOCATIONS];
uint8_t pdsch_aggregation_factor;
fapi_nr_rate_matching_pattern_group_t rate_matching_pattern_group1;
fapi_nr_rate_matching_pattern_group_t rate_matching_pattern_group2;
uint8_t rbg_size;
uint8_t mcs_table;
uint8_t max_num_of_code_word_scheduled_by_dci;
uint8_t bundle_size; // prb_bundling static
uint8_t bundle_size_set1; // prb_bundling dynamic
uint8_t bundle_size_set2; // prb_bundling dynamic
fapi_nr_zp_csi_rs_resource_t periodically_zp_csi_rs_resource_set[FAPI_NR_MAX_NUM_ZP_CSI_RS_RESOURCE_PER_SET];
} fapi_nr_pdsch_config_dedicated_t;
typedef struct {
uint16_t starting_prb;
uint8_t intra_slot_frequency_hopping;
uint16_t second_hop_prb;
uint8_t format; // pucch format 0..4
uint8_t initial_cyclic_shift;
uint8_t number_of_symbols;
uint8_t starting_symbol_index;
uint8_t time_domain_occ;
uint8_t number_of_prbs;
uint8_t occ_length;
uint8_t occ_index;
} fapi_nr_pucch_resource_t;
typedef struct {
uint8_t periodicity;
uint8_t number_of_harq_process;
fapi_nr_pucch_resource_t n1_pucch_an;
} fapi_nr_sps_config_t;
typedef struct {
uint8_t beam_failure_instance_max_count;
uint8_t beam_failure_detection_timer;
} fapi_nr_radio_link_monitoring_config_t;
typedef struct {
fapi_nr_pdcch_config_dedicated_t pdcch_config_dedicated;
fapi_nr_pdsch_config_dedicated_t pdsch_config_dedicated;
fapi_nr_sps_config_t sps_config;
fapi_nr_radio_link_monitoring_config_t radio_link_monitoring_config;
} fapi_nr_dl_bwp_dedicated_config_t;
typedef struct {
fapi_nr_rach_config_common_t rach_config_common;
fapi_nr_pusch_config_common_t pusch_config_common;
fapi_nr_pucch_config_common_t pucch_config_common;
} fapi_nr_ul_bwp_common_config_t;
typedef struct {
uint8_t inter_slot_frequency_hopping;
uint8_t additional_dmrs;
uint8_t max_code_rate;
uint8_t number_of_slots;
uint8_t pi2bpsk;
uint8_t simultaneous_harq_ack_csi;
} fapi_nr_pucch_format_config_t;
typedef struct {
fapi_nr_pucch_format_config_t format1;
fapi_nr_pucch_format_config_t format2;
fapi_nr_pucch_format_config_t format3;
fapi_nr_pucch_format_config_t format4;
fapi_nr_pucch_resource_t multi_csi_pucch_resources[2];
uint8_t dl_data_to_ul_ack[8];
// pucch power control
uint8_t deltaF_pucch_f0;
uint8_t deltaF_pucch_f1;
uint8_t deltaF_pucch_f2;
uint8_t deltaF_pucch_f3;
uint8_t deltaF_pucch_f4;
uint8_t two_pucch_pc_adjusment_states;
} fapi_nr_pucch_config_dedicated_t;
typedef struct {
uint8_t dmrs_type;
uint8_t dmrs_addition_position;
uint8_t ptrs_uplink_config; // to indicate if PTRS Uplink is configured of not
uint8_t ptrs_type; //cp-OFDM, dft-S-OFDM
uint16_t ptrs_frequency_density[2];
uint8_t ptrs_time_density[3];
uint8_t ptrs_max_number_of_ports;
uint8_t ptrs_resource_element_offset;
uint8_t ptrs_power;
uint16_t ptrs_sample_density[5];
uint8_t ptrs_time_density_transform_precoding;
uint8_t max_length;
uint16_t scrambling_id0;
uint16_t scrambling_id1;
uint8_t npusch_identity;
uint8_t disable_sequence_group_hopping;
uint8_t sequence_hopping_enable;
} fapi_nr_dmrs_uplink_config_t;
typedef struct {
uint8_t tpc_accmulation;
uint8_t msg3_alpha;
uint8_t p0_nominal_with_grant;
uint8_t two_pusch_pc_adjustments_states;
uint8_t delta_mcs;
} fapi_nr_pusch_power_control_t;
typedef enum {tx_config_codebook = 1, tx_config_nonCodebook = 2} tx_config_t;
typedef enum {transform_precoder_disabled = 0, transform_precoder_enabled = 1} transform_precoder_t;
typedef enum {
codebook_subset_fullyAndPartialAndNonCoherent = 1,
codebook_subset_partialAndNonCoherent = 2,
codebook_subset_nonCoherent = 3} codebook_subset_t;
typedef struct {
uint16_t data_scrambling_identity;
tx_config_t tx_config;
fapi_nr_dmrs_uplink_config_t dmrs_ul_for_pusch_mapping_type_a;
fapi_nr_dmrs_uplink_config_t dmrs_ul_for_pusch_mapping_type_b;
fapi_nr_pusch_power_control_t pusch_power_control;
uint8_t frequency_hopping;
uint16_t frequency_hopping_offset_lists[4];
uint8_t resource_allocation;
fapi_nr_pusch_time_domain_resource_allocation_t allocation_list[FAPI_NR_MAX_NUM_UL_ALLOCATIONS];
uint8_t pusch_aggregation_factor;
uint8_t mcs_table;
uint8_t mcs_table_transform_precoder;
transform_precoder_t transform_precoder;
codebook_subset_t codebook_subset;
uint8_t max_rank;
uint8_t rbg_size;
//uci-OnPUSCH
uint8_t uci_on_pusch_type; //dynamic, semi-static
uint8_t beta_offset_ack_index1[4];
uint8_t beta_offset_ack_index2[4];
uint8_t beta_offset_ack_index3[4];
uint8_t beta_offset_csi_part1_index1[4];
uint8_t beta_offset_csi_part1_index2[4];
uint8_t beta_offset_csi_part2_index1[4];
uint8_t beta_offset_csi_part2_index2[4];
uint8_t tp_pi2BPSK;
} fapi_nr_pusch_config_dedicated_t;
typedef struct {
uint8_t frequency_hopping;
fapi_nr_dmrs_uplink_config_t cg_dmrs_configuration;
uint8_t mcs_table;
uint8_t mcs_table_transform_precoder;
//uci-OnPUSCH
uint8_t uci_on_pusch_type; //dynamic, semi-static
uint8_t beta_offset_ack_index1[4];
uint8_t beta_offset_ack_index2[4];
uint8_t beta_offset_ack_index3[4];
uint8_t beta_offset_csi_part1_index1[4];
uint8_t beta_offset_csi_part1_index2[4];
uint8_t beta_offset_csi_part2_index1[4];
uint8_t beta_offset_csi_part2_index2[4];
uint8_t resource_allocation;
// rgb-Size structure missing in spec.
uint8_t power_control_loop_to_use;
// p0-PUSCH-Alpha
uint8_t p0;
uint8_t alpha;
uint8_t transform_precoder;
uint8_t number_of_harq_process;
uint8_t rep_k;
uint8_t rep_k_rv;
uint8_t periodicity;
uint8_t configured_grant_timer;
// rrc-ConfiguredUplinkGrant
uint16_t time_domain_offset;
uint8_t time_domain_allocation;
uint32_t frequency_domain_allocation;
uint8_t antenna_ports;
uint8_t dmrs_seq_initialization;
uint8_t precoding_and_number_of_layers;
uint8_t srs_resource_indicator;
uint8_t mcs_and_tbs;
uint8_t frequency_hopping_offset;
uint8_t path_loss_reference_index;
} fapi_nr_configured_grant_config_t;
typedef struct {
uint8_t qcl_type1_serving_cell_index;
uint8_t qcl_type1_bwp_id;
uint8_t qcl_type1_rs_type; // csi-rs or ssb
uint8_t qcl_type1_nzp_csi_rs_resource_id;
uint8_t qcl_type1_ssb_index;
uint8_t qcl_type1_type;
uint8_t qcl_type2_serving_cell_index;
uint8_t qcl_type2_bwp_id;
uint8_t qcl_type2_rs_type; // csi-rs or ssb
uint8_t qcl_type2_nzp_csi_rs_resource_id;
uint8_t qcl_type2_ssb_index;
uint8_t qcl_type2_type;
} fapi_nr_tci_state_t;
typedef struct {
uint8_t root_sequence_index;
// rach genertic
uint8_t prach_configuration_index;
uint8_t msg1_fdm;
uint8_t msg1_frequency_start;
uint8_t zero_correlation_zone_config;
uint8_t preamble_received_target_power;
uint8_t preamble_transmission_max;
uint8_t power_ramping_step;
uint8_t ra_window_size;
uint8_t rsrp_threshold_ssb;
// PRACH-ResourceDedicatedBFR
uint8_t bfr_ssb_index[FAPI_NR_MAX_NUM_CANDIDATE_BEAMS];
uint8_t bfr_ssb_ra_preamble_index[FAPI_NR_MAX_NUM_CANDIDATE_BEAMS];
// NZP-CSI-RS-Resource
uint8_t bfr_csi_rs_nzp_resource_mapping[FAPI_NR_MAX_NUM_CANDIDATE_BEAMS];
uint8_t bfr_csi_rs_power_control_offset[FAPI_NR_MAX_NUM_CANDIDATE_BEAMS];
uint8_t bfr_csi_rs_power_control_offset_ss[FAPI_NR_MAX_NUM_CANDIDATE_BEAMS];
uint16_t bfr_csi_rs_scrambling_id[FAPI_NR_MAX_NUM_CANDIDATE_BEAMS];
uint8_t bfr_csi_rs_resource_periodicity[FAPI_NR_MAX_NUM_CANDIDATE_BEAMS];
uint16_t bfr_csi_rs_resource_offset[FAPI_NR_MAX_NUM_CANDIDATE_BEAMS];
fapi_nr_tci_state_t qcl_infomation_periodic_csi_rs[FAPI_NR_MAX_NUM_CANDIDATE_BEAMS];
uint8_t bfr_csirs_ra_occasions[FAPI_NR_MAX_NUM_CANDIDATE_BEAMS];
uint8_t bfr_csirs_ra_preamble_index[FAPI_NR_MAX_NUM_CANDIDATE_BEAMS][FAPI_NR_MAX_RA_OCCASION_PER_CSIRS];
uint8_t ssb_per_rach_occasion;
uint8_t ra_ssb_occasion_mask_index;
fapi_nr_search_space_t recovery_search_space;
// RA-Prioritization
uint8_t power_ramping_step_high_priority;
uint8_t scaling_factor_bi;
uint8_t beam_failure_recovery_timer;
} fapi_nr_beam_failure_recovery_config_t;
typedef struct {
fapi_nr_pucch_config_dedicated_t pucch_config_dedicated;
fapi_nr_pusch_config_dedicated_t pusch_config_dedicated;
fapi_nr_configured_grant_config_t configured_grant_config;
// SRS-Config
uint8_t srs_tpc_accumulation;
fapi_nr_beam_failure_recovery_config_t beam_failure_recovery_config;
} fapi_nr_ul_bwp_dedicated_config_t;
#define FAPI_NR_CONFIG_REQUEST_MASK_PBCH 0x01
#define FAPI_NR_CONFIG_REQUEST_MASK_DL_BWP_COMMON 0x02
#define FAPI_NR_CONFIG_REQUEST_MASK_UL_BWP_COMMON 0x04
#define FAPI_NR_CONFIG_REQUEST_MASK_DL_BWP_DEDICATED 0x08
#define FAPI_NR_CONFIG_REQUEST_MASK_UL_BWP_DEDICATED 0x10
typedef struct {
uint32_t config_mask;
fapi_nr_pbch_config_t pbch_config; // MIB
fapi_nr_dl_bwp_common_config_t dl_bwp_common;
fapi_nr_dl_bwp_dedicated_config_t dl_bwp_dedicated;
fapi_nr_ul_bwp_common_config_t ul_bwp_common;
fapi_nr_ul_bwp_dedicated_config_t ul_bwp_dedicated;
} fapi_nr_config_request_t;
#endif
nfapi/open-nFAPI/nfapi/public_inc/nfapi_interface.h
+38 -6
View File
@@ -1,12 +1,12 @@
/*
* Copyright 2017 Cisco Systems, Inc.
*
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*
* http://www.apache.org/licenses/LICENSE-2.0
*
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -19,6 +19,7 @@
#define _NFAPI_INTERFACE_H_
#include "stddef.h"
#include <stdint.h>
// Constants - update based on implementation
#define NFAPI_MAX_PHY_RF_INSTANCES 2
@@ -30,7 +31,7 @@
// These may be changed if desired. They are used in the encoder to make sure
// that the user has not specified a 'count' larger than the max array, and also
// used by the decoder when decode an array. If the 'count' received is larger
// than the array it is to be stored in the decode fails.
// than the array it is to be stored in the decode fails.
#define NFAPI_MAX_NUM_ANTENNAS 8
#define NFAPI_MAX_NUM_SUBBANDS 13
#define NFAPI_MAX_BF_VECTORS 8
@@ -74,6 +75,9 @@
#define NFAPI_VERSION_3_0_11 0x000
#define NFAPI_VERSION_3_0_12 0x001
#define NFAPI_HALF_FRAME_INDEX_FIRST_HALF 0
#define NFAPI_HALF_FRAME_INDEX_SECOND_HALF 1
// The IANA agreed port definition of the P5 SCTP VNF enpoint
// http://www.iana.org/assignments/service-names-port-numbers/service-names-port-numbers.xhtml?search=7701
#define NFAPI_P5_SCTP_PORT 7701
@@ -340,7 +344,8 @@ typedef enum {
NFAPI_3GPP_REL_SUPPORTED_9 = 1,
NFAPI_3GPP_REL_SUPPORTED_10 = 2,
NFAPI_3GPP_REL_SUPPORTED_11 = 4,
NFAPI_3GPP_REL_SUPPORTED_12 = 8
NFAPI_3GPP_REL_SUPPORTED_12 = 8,
NFAPI_3GPP_REL_SUPPORTED_15 = 64
} nfapi_3gpp_release_supported_e;
@@ -359,7 +364,8 @@ typedef enum {
NFAPI_RAT_TYPE_LTE = 0,
NFAPI_RAT_TYPE_UTRAN = 1,
NFAPI_RAT_TYPE_GERAN = 2,
NFAPI_RAT_TYPE_NB_IOT = 3
NFAPI_RAT_TYPE_NB_IOT = 3,
NFAPI_RAT_TYPE_NR = 4
} nfapi_rat_type_e;
typedef enum {
@@ -536,6 +542,16 @@ typedef struct {
} nfapi_pnf_phy_rel13_nb_iot_t;
#define NFAPI_PNF_PHY_REL13_NB_IOT_TAG 0x100E
typedef struct {
uint16_t phy_config_index;
} nfapi_pnf_phy_rel15_info_t;
typedef struct {
nfapi_tl_t tl;
uint16_t number_of_phys;
nfapi_pnf_phy_rel15_info_t phy[NFAPI_MAX_PNF_PHY];
} nfapi_pnf_phy_rel15_t;
#define NFAPI_PNF_PHY_REL15_TAG 0x100H
typedef struct {
@@ -621,6 +637,7 @@ typedef struct {
#define NFAPI_L23_CONFIG_SFNSF_TAG 0x00F1
typedef struct {
nfapi_uint16_tlv_t numerology_index_mu;
nfapi_uint16_tlv_t duplex_mode;
nfapi_uint16_tlv_t pcfich_power_offset;
nfapi_uint16_tlv_t pb;
@@ -633,6 +650,7 @@ typedef struct {
#define NFAPI_SUBFRAME_CONFIG_PB_TAG 0x0003
#define NFAPI_SUBFRAME_CONFIG_DL_CYCLIC_PREFIX_TYPE_TAG 0x0004
#define NFAPI_SUBFRAME_CONFIG_UL_CYCLIC_PREFIX_TYPE_TAG 0x0005
#define NFAPI_SUBFRAME_CONFIG_NUMEROLOGY_INDEX_MU_TAG 0x0006
typedef struct {
nfapi_uint16_tlv_t dl_channel_bandwidth;
@@ -658,15 +676,28 @@ typedef struct {
#define NFAPI_PHICH_CONFIG_PHICH_DURATION_TAG 0x0015
#define NFAPI_PHICH_CONFIG_PHICH_POWER_OFFSET_TAG 0x0016
typedef struct {
nfapi_uint16_tlv_t primary_synchronization_signal_epre_eprers;
nfapi_uint16_tlv_t secondary_synchronization_signal_epre_eprers;
nfapi_uint16_tlv_t physical_cell_id;
nfapi_uint16_tlv_t half_frame_index;
nfapi_uint16_tlv_t ssb_subcarrier_offset;
nfapi_uint16_tlv_t ssb_position_in_burst;
nfapi_uint16_tlv_t ssb_periodicity;
nfapi_uint16_tlv_t ss_pbch_block_power;
nfapi_uint16_tlv_t n_ssb_crb;
} nfapi_sch_config_t;
#define NFAPI_SCH_CONFIG_PRIMARY_SYNCHRONIZATION_SIGNAL_EPRE_EPRERS_TAG 0x001E
#define NFAPI_SCH_CONFIG_SECONDARY_SYNCHRONIZATION_SIGNAL_EPRE_EPRERS_TAG 0x001F
#define NFAPI_SCH_CONFIG_PHYSICAL_CELL_ID_TAG 0x0020
#define NFAPI_SCH_CONFIG_HALF_FRAME_INDEX_TAG 0x0021
#define NFAPI_SCH_CONFIG_SSB_SUBCARRIER_OFFSET_TAG 0x0022
#define NFAPI_SCH_CONFIG_SSB_POSITION_IN_BURST 0x0023
#define NFAPI_SCH_CONFIG_SSB_PERIODICITY 0x0024
#define NFAPI_SCH_CONFIG_SS_PBCH_BLOCK_POWER 0x0025
#define NFAPI_SCH_CONFIG_N_SSB_CRB 0x0025
typedef struct {
nfapi_uint16_tlv_t configuration_index;
@@ -1069,6 +1100,7 @@ typedef struct {
nfapi_pnf_phy_rel12_t pnf_phy_rel12;
nfapi_pnf_phy_rel13_t pnf_phy_rel13;
nfapi_pnf_phy_rel13_nb_iot_t pnf_phy_rel13_nb_iot;
nfapi_pnf_phy_rel15_t pnf_phy_rel15;
nfapi_vendor_extension_tlv_t vendor_extension;
} nfapi_pnf_param_response_t;
nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h
+719
View File
@@ -0,0 +1,719 @@
/*
nfapi_nr_interface.h
-------------------
AUTHOR : Raymond Knopp, Guy de Souza, WEI-TAI CHEN
COMPANY : EURECOM, NTUST
EMAIL : Lionel.Gauthier@eurecom.fr, desouza@eurecom.fr, kroempa@gmail.com
*/
#ifndef _NFAPI_NR_INTERFACE_H_
#define _NFAPI_NR_INTERFACE_H_
#include "nfapi_interface.h"
#define NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS 5
#define NFAPI_NR_MAX_NB_TCI_STATES_PDCCH 64
#define NFAPI_NR_MAX_NB_CORESETS 12
#define NFAPI_NR_MAX_NB_SEARCH_SPACES 40
// Extension to the generic structures for single tlv values
typedef struct {
nfapi_tl_t tl;
int32_t value;
} nfapi_int32_tlv_t;
typedef struct {
nfapi_tl_t tl;
uint32_t value;
} nfapi_uint32_tlv_t;
/*typedef struct {
nfapi_tl_t tl;
int64_t value;
} nfapi_int64_tlv_t;*/
typedef struct {
nfapi_tl_t tl;
uint64_t value;
} nfapi_uint64_tlv_t;
// nFAPI enums
typedef enum {
NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE = 0,
NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_PCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_NBCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_NPDCCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_NDLSCH_PDU_TYPE
} nfapi_nr_dl_config_pdu_type_e;
//These TLVs are used exclusively by nFAPI
typedef struct
{
// These TLVs are used to setup the transport connection between VNF and PNF
// nfapi_ipv4_address_t p7_vnf_address_ipv4;
// nfapi_ipv6_address_t p7_vnf_address_ipv6;
// nfapi_uint16_tlv_t p7_vnf_port;
// nfapi_ipv4_address_t p7_pnf_address_ipv4;
// nfapi_ipv6_address_t p7_pnf_address_ipv6;
// nfapi_uint16_tlv_t p7_pnf_port;
// // These TLVs are used to setup the transport connection between VNF and PNF
// nfapi_uint8_tlv_t dl_ue_per_sf;
// nfapi_uint8_tlv_t ul_ue_per_sf;
// These TLVs are used by PNF to report its RF capabilities to the VNF software
nfapi_rf_bands_t rf_bands;
// These TLVs are used by the VNF to configure the synchronization with the PNF.
// nfapi_uint8_tlv_t timing_window;
// nfapi_uint8_tlv_t timing_info_mode;
// nfapi_uint8_tlv_t timing_info_period;
// These TLVs are used by the VNF to configure the RF in the PNF
// nfapi_uint16_tlv_t max_transmit_power;
nfapi_uint32_tlv_t nrarfcn;
// nfapi_nmm_frequency_bands_t nmm_gsm_frequency_bands;
// nfapi_nmm_frequency_bands_t nmm_umts_frequency_bands;
// nfapi_nmm_frequency_bands_t nmm_lte_frequency_bands;
// nfapi_uint8_tlv_t nmm_uplink_rssi_supported;
} nfapi_nr_nfapi_t;
#define NFAPI_NR_NFAPI_P7_VNF_ADDRESS_IPV4_TAG 0x5100
#define NFAPI_NR_NFAPI_P7_VNF_ADDRESS_IPV6_TAG 0x5101
#define NFAPI_NR_NFAPI_P7_VNF_PORT_TAG 0x5102
#define NFAPI_NR_NFAPI_P7_PNF_ADDRESS_IPV4_TAG 0x5103
#define NFAPI_NR_NFAPI_P7_PNF_ADDRESS_IPV6_TAG 0x5104
#define NFAPI_NR_NFAPI_P7_PNF_PORT_TAG 0x5105
#define NFAPI_NR_NFAPI_DOWNLINK_UES_PER_SUBFRAME_TAG 0x510A
#define NFAPI_NR_NFAPI_UPLINK_UES_PER_SUBFRAME_TAG 0x510B
#define NFAPI_NR_NFAPI_RF_BANDS_TAG 0x5114
#define NFAPI_NR_NFAPI_TIMING_WINDOW_TAG 0x511E
#define NFAPI_NR_NFAPI_TIMING_INFO_MODE_TAG 0x511F
#define NFAPI_NR_NFAPI_TIMING_INFO_PERIOD_TAG 0x5120
#define NFAPI_NR_NFAPI_MAXIMUM_TRANSMIT_POWER_TAG 0x5128
#define NFAPI_NR_NFAPI_NRARFCN_TAG 0x5129
#define NFAPI_NR_NFAPI_NMM_GSM_FREQUENCY_BANDS_TAG 0x5130
#define NFAPI_NR_NFAPI_NMM_UMTS_FREQUENCY_BANDS_TAG 0x5131
#define NFAPI_NR_NFAPI_NMM_LTE_FREQUENCY_BANDS_TAG 0x5132
#define NFAPI_NR_NFAPI_NMM_UPLINK_RSSI_SUPPORTED_TAG 0x5133
// P5 Message Structures
typedef struct{
nfapi_tl_t tl;
uint16_t corset_ID; ///// L1 parameter 'CORESET-ID'
uint16_t freq_dom; ///// L1 parameter 'CORESET-freq-dom'
uint16_t duration; ///// L1 parameter 'CORESET-time-duration'
uint16_t reg_type; ///// L1 parameter 'CORESET-CCE-REG-mapping-type'
uint16_t reg_bundlesize; ///// L1 parameter 'CORESET-REG-bundle-size'
uint16_t interleaversize; ///// L1 parameter 'CORESET-interleaver-size'
uint16_t shiftindex; ///// L1 parameter 'CORESET-shift-index'
uint16_t precodergranularity; ///// L1 parameter 'CORESET-precoder-granuality'
uint16_t tci_stateId; ///// L1 parameter 'TCI-StatesPDCCH'
uint16_t tci_present; ///// L1 parameter 'TCI-PresentInDCI'
uint16_t dmrs_scramblingID; ///// L1 parameter 'PDCCH-DMRS-Scrambling-ID'
} nfapi_nr_ControlResourcesSet_t;
typedef struct{
nfapi_tl_t tl;
nfapi_nr_ControlResourcesSet_t coreset;
uint16_t monitoringSlotPeriodicityAndOffset; ///// L1 parameters 'Montoring-periodicity-PDCCH-slot'
uint16_t monitoringSymbolsWithinSlot; ///// L1 parameter 'Montoring-symbols-PDCCH-within-slot'
uint16_t nrofCand_aggLevel1; ///// L1 parameter 'Aggregation-level-1'
uint16_t nrofCand_aggLevel2; ///// L1 parameter 'Aggregation-level-2'
uint16_t nrofCand_aggLevel4; ///// L1 parameter 'Aggregation-level-4'
uint16_t nrofCand_aggLevel8; ///// L1 parameter 'Aggregation-level-8'
uint16_t nrofCand_aggLevel16; ///// L1 parameter 'Aggregation-level-16'
uint16_t sfi_agg_fmt2_0; ///// L1 parameters 'SFI-Num-PDCCH-cand' and 'SFI-Aggregation-Level'
uint16_t monitoringperiodicity_fmt2_3; ///// L1 parameter 'SRS-monitoring-periodicity'
uint16_t nrof_candidates_fmt_2_3; ///// L1 parameter 'SRS-Num-PDCCH-cand'
} nfapi_nr_SearchSpace_t;
typedef struct {
nfapi_uint16_tlv_t numerology_index_mu;
nfapi_uint16_tlv_t duplex_mode;
nfapi_uint16_tlv_t dl_cyclic_prefix_type;
nfapi_uint16_tlv_t ul_cyclic_prefix_type;
} nfapi_nr_subframe_config_t;
#define NFAPI_NR_SUBFRAME_CONFIG_DUPLEX_MODE_TAG 0x5001
#define NFAPI_NR_SUBFRAME_CONFIG_PCFICH_POWER_OFFSET_TAG 0x5002
#define NFAPI_NR_SUBFRAME_CONFIG_PB_TAG 0x5003
#define NFAPI_NR_SUBFRAME_CONFIG_DL_CYCLIC_PREFIX_TYPE_TAG 0x5004
#define NFAPI_NR_SUBFRAME_CONFIG_UL_CYCLIC_PREFIX_TYPE_TAG 0x5005
#define NFAPI_NR_SUBFRAME_CONFIG_NUMEROLOGY_INDEX_MU_TAG 0x5006
typedef struct {
nfapi_uint16_tlv_t dl_carrier_bandwidth;
nfapi_uint16_tlv_t ul_carrier_bandwidth;
nfapi_uint16_tlv_t dl_bwp_subcarrierspacing;
nfapi_uint16_tlv_t ul_bwp_subcarrierspacing;
nfapi_uint16_tlv_t dl_locationandbandwidth;
nfapi_uint16_tlv_t ul_locationandbandwidth;
nfapi_uint16_tlv_t dl_absolutefrequencypointA;
nfapi_uint16_tlv_t ul_absolutefrequencypointA;
nfapi_uint16_tlv_t dl_offsettocarrier;
nfapi_uint16_tlv_t ul_offsettocarrier;
nfapi_uint16_tlv_t dl_subcarrierspacing;
nfapi_uint16_tlv_t ul_subcarrierspacing;
nfapi_uint16_tlv_t dl_specificcarrier_k0;
nfapi_uint16_tlv_t ul_specificcarrier_k0;
nfapi_uint16_tlv_t NIA_subcarrierspacing;
} nfapi_nr_rf_config_t;
#define NFAPI_NR_RF_CONFIG_DL_CARRIER_BANDWIDTH_TAG 0x500A
#define NFAPI_NR_RF_CONFIG_UL_CARRIER_BANDWIDTH_TAG 0x500B
#define NFAPI_NR_RF_CONFIG_DL_SUBCARRIERSPACING_TAG 0x500C
#define NFAPI_NR_RF_CONFIG_UL_SUBCARRIERSPACING_TAG 0x500D
typedef struct {
nfapi_uint16_tlv_t physical_cell_id;
nfapi_uint16_tlv_t half_frame_index;
nfapi_uint16_tlv_t ssb_subcarrier_offset;
nfapi_uint16_tlv_t ssb_sib1_position_in_burst; // in sib1
nfapi_uint64_tlv_t ssb_scg_position_in_burst; // in servingcellconfigcommon
nfapi_uint16_tlv_t ssb_periodicity;
nfapi_uint16_tlv_t ss_pbch_block_power;
nfapi_uint16_tlv_t n_ssb_crb;
nfapi_uint16_tlv_t rmsi_pdcch_config;
} nfapi_nr_sch_config_t;
#define NFAPI_NR_SCH_CONFIG_PHYSICAL_CELL_ID_TAG 0x501E
#define NFAPI_NR_SCH_CONFIG_HALF_FRAME_INDEX_TAG 0x501F
#define NFAPI_NR_SCH_CONFIG_SSB_SUBCARRIER_OFFSET_TAG 0x5020
#define NFAPI_NR_SCH_CONFIG_SSB_POSITION_IN_BURST 0x5021
#define NFAPI_NR_SCH_CONFIG_SSB_PERIODICITY 0x5022
#define NFAPI_NR_SCH_CONFIG_SS_PBCH_BLOCK_POWER 0x5023
#define NFAPI_NR_SCH_CONFIG_N_SSB_CRB 0x5024
typedef struct {
nfapi_uint16_tlv_t data_scrambling_id;
nfapi_uint16_tlv_t dmrs_typeA_position;
nfapi_uint16_tlv_t dmrs_additional_position;
nfapi_uint16_tlv_t dmrs_type;
nfapi_uint16_tlv_t dmrs_max_length;
nfapi_uint16_tlv_t mapping_type;
nfapi_uint16_tlv_t resource_allocation;
nfapi_uint16_tlv_t time_allocation_list;
nfapi_uint16_tlv_t mcs_table;
nfapi_uint16_tlv_t aggregation_factor;
nfapi_uint16_tlv_t prb_bundling_type;
nfapi_uint16_tlv_t rbg_size;
nfapi_uint16_tlv_t vrb_to_prb_interleaver;
nfapi_uint16_tlv_t code_block_groug_transmission;
nfapi_uint16_tlv_t x_overhead;
nfapi_uint16_tlv_t max_dci_codewords;
} nfapi_nr_pdsch_config_t;
#define NFAPI_NR_PDSCH_CONFIG_TAG
typedef struct {
nfapi_uint16_tlv_t prach_RootSequenceIndex; ///// L1 parameter 'PRACHRootSequenceIndex'
nfapi_uint16_tlv_t prach_msg1_SubcarrierSpacing; ///// L1 parameter 'prach-Msg1SubcarrierSpacing'
nfapi_uint16_tlv_t restrictedSetConfig;
nfapi_uint16_tlv_t msg3_transformPrecoding; ///// L1 parameter 'msg3-tp'
/////////////////--------------------NR RACH-ConfigGeneric--------------------/////////////////
nfapi_uint16_tlv_t prach_ConfigurationIndex; ///// L1 parameter 'PRACHConfigurationIndex'
nfapi_uint16_tlv_t prach_msg1_FDM; ///// L1 parameter 'prach-FDM'
nfapi_uint16_tlv_t prach_msg1_FrequencyStart; ///// L1 parameter 'prach-frequency-start'
nfapi_uint16_tlv_t zeroCorrelationZoneConfig;
nfapi_uint16_tlv_t preambleReceivedTargetPower;
} nfapi_nr_rach_config_t;
typedef struct {
nfapi_uint16_tlv_t groupHoppingEnabledTransformPrecoding; ///// L1 parameter 'Group-hopping-enabled-Transform-precoding'
nfapi_uint16_tlv_t msg3_DeltaPreamble; ///// L1 parameter 'Delta-preamble-msg3'
nfapi_uint16_tlv_t p0_NominalWithGrant; ///// L1 parameter 'p0-nominal-pusch-withgrant'
nfapi_uint16_tlv_t TimeDomainResourceAllocation_k2; ///// L1 parameter 'K2'
nfapi_uint16_tlv_t TimeDomainResourceAllocation_mappingType; ///// L1 parameter 'Mapping-type'
} nfapi_nr_pusch_config_t;
typedef struct {
nfapi_uint16_tlv_t pucch_GroupHopping; ///// L1 parameter 'PUCCH-GroupHopping'
nfapi_uint16_tlv_t p0_nominal; ///// L1 parameter 'p0-nominal-pucch'
} nfapi_nr_pucch_config_t;
typedef struct {
nfapi_tl_t tl;
nfapi_nr_SearchSpace_t sib1searchSpace;
nfapi_nr_SearchSpace_t sibssearchSpace;
nfapi_nr_SearchSpace_t ra_SearchSpace;
}nfapi_nr_pdcch_config_t;
typedef struct {
//NR TDD-UL-DL-ConfigCommon ///// L1 parameter 'UL-DL-configuration-common'
nfapi_uint16_tlv_t subcarrierspacing; ///// L1 parameter 'reference-SCS'
nfapi_uint16_tlv_t dl_ul_periodicity; ///// L1 parameter 'DL-UL-transmission-periodicity'
nfapi_uint16_tlv_t nrofDownlinkSlots; ///// L1 parameter 'number-of-DL-slots'
nfapi_uint16_tlv_t nrofDownlinkSymbols; ///// L1 parameter 'number-of-DL-symbols-common'
nfapi_uint16_tlv_t nrofUplinkSlots; ///// L1 parameter 'number-of-UL-slots'
nfapi_uint16_tlv_t nrofUplinkSymbols; ///// L1 parameter 'number-of-UL-symbols-common'
} nfapi_nr_tdd_ul_dl_config_t;
typedef struct {
//RateMatchPattern is used to configure one rate matching pattern for PDSCH ///// L1 parameter 'Resource-set-cekk'
nfapi_uint16_tlv_t Match_Id;
nfapi_uint16_tlv_t patternType;
nfapi_uint16_tlv_t symbolsInResourceBlock; ///// L1 parameter 'rate-match-PDSCH-bitmap2
nfapi_uint16_tlv_t periodicityAndPattern; ///// L1 parameter 'rate-match-PDSCH-bitmap3'
nfapi_uint16_tlv_t controlResourceSet;
nfapi_uint16_tlv_t subcarrierSpacing; ///// L1 parameter 'resource-pattern-scs'
nfapi_uint16_tlv_t mode;
} nfapi_nr_ratematchpattern_t;
typedef struct {
//NR RateMatchPatternLTE-CRS
nfapi_uint16_tlv_t carrierfreqDL; ///// L1 parameter 'center-subcarrier-location'
nfapi_uint16_tlv_t dl_bandwidth; ///// L1 parameter 'BW'
nfapi_uint16_tlv_t nrofcrs_Ports; ///// L1 parameter 'rate-match-resources-numb-LTE-CRS-antenna-port'
nfapi_uint16_tlv_t v_Shift; ///// L1 parameter 'rate-match-resources-LTE-CRS-v-shift'
nfapi_uint16_tlv_t frame_Period;
nfapi_uint16_tlv_t frame_Offset;
} nfapi_nr_ratematchpattern_lte_crs_t;
typedef struct {
nfapi_p4_p5_message_header_t header;
uint8_t num_tlv;
nfapi_nr_subframe_config_t subframe_config;
nfapi_nr_rf_config_t rf_config;
nfapi_nr_sch_config_t sch_config;
nfapi_nr_pdsch_config_t pdsch_config;
nfapi_nr_rach_config_t rach_config;
nfapi_nr_pusch_config_t pusch_config;
nfapi_nr_pucch_config_t pucch_config;
nfapi_nr_pdcch_config_t pdcch_config;
nfapi_nr_tdd_ul_dl_config_t tdd_ul_dl_config;
nfapi_nr_ratematchpattern_t ratematchpattern;
nfapi_nr_ratematchpattern_lte_crs_t ratematchpattern_lte_crs;
nfapi_nr_nfapi_t nfapi_config;
nfapi_vendor_extension_tlv_t vendor_extension;
} nfapi_nr_config_request_t;
typedef enum {
NFAPI_NR_DL_DCI_FORMAT_1_0 = 0,
NFAPI_NR_DL_DCI_FORMAT_1_1,
NFAPI_NR_DL_DCI_FORMAT_2_0,
NFAPI_NR_DL_DCI_FORMAT_2_1,
NFAPI_NR_DL_DCI_FORMAT_2_2,
NFAPI_NR_DL_DCI_FORMAT_2_3,
NFAPI_NR_UL_DCI_FORMAT_0_0,
NFAPI_NR_UL_DCI_FORMAT_0_1
} nfapi_nr_dci_format_e;
typedef enum {
NFAPI_NR_RNTI_new = 0,
NFAPI_NR_RNTI_C,
NFAPI_NR_RNTI_RA,
NFAPI_NR_RNTI_P,
NFAPI_NR_RNTI_CS,
NFAPI_NR_RNTI_TC,
NFAPI_NR_RNTI_SP_CSI,
NFAPI_NR_RNTI_SI,
NFAPI_NR_RNTI_SFI,
NFAPI_NR_RNTI_INT,
NFAPI_NR_RNTI_TPC_PUSCH,
NFAPI_NR_RNTI_TPC_PUCCH,
NFAPI_NR_RNTI_TPC_SRS
} nfapi_nr_rnti_type_e;
typedef enum {
NFAPI_NR_USS_FORMAT_0_0_AND_1_0,
NFAPI_NR_USS_FORMAT_0_1_AND_1_1,
} nfapi_nr_uss_dci_formats_e;
typedef enum {
NFAPI_NR_SEARCH_SPACE_TYPE_COMMON=0,
NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC
} nfapi_nr_search_space_type_e;
typedef enum {
NFAPI_NR_COMMON_SEARCH_SPACE_TYPE_0=0,
NFAPI_NR_COMMON_SEARCH_SPACE_TYPE_0A,
NFAPI_NR_COMMON_SEARCH_SPACE_TYPE_1,
NFAPI_NR_COMMON_SEARCH_SPACE_TYPE_2
} nfapi_nr_common_search_space_type_e;
typedef enum {
NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1=0,
NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2,
NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE3
} nfapi_nr_ssb_and_cset_mux_pattern_type_e;
typedef enum {
NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED=0,
NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED
} nfapi_nr_cce_reg_mapping_type_e;
typedef enum {
NFAPI_NR_CSET_CONFIG_MIB_SIB1=0,
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG, // implicit assumption of coreset Id other than 0
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG_CSET_0
} nfapi_nr_coreset_config_type_e;
typedef enum {
NFAPI_NR_CSET_SAME_AS_REG_BUNDLE=0,
NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS
} nfapi_nr_coreset_precoder_granularity_type_e;
typedef enum {
NFAPI_NR_QCL_TYPE_A=0,
NFAPI_NR_QCL_TYPE_B,
NFAPI_NR_QCL_TYPE_C,
NFAPI_NR_QCL_TYPE_D
} nfapi_nr_qcl_type_e;
typedef enum {
NFAPI_NR_SS_PERIODICITY_SL1=1,
NFAPI_NR_SS_PERIODICITY_SL2=2,
NFAPI_NR_SS_PERIODICITY_SL4=4,
NFAPI_NR_SS_PERIODICITY_SL5=5,
NFAPI_NR_SS_PERIODICITY_SL8=8,
NFAPI_NR_SS_PERIODICITY_SL10=10,
NFAPI_NR_SS_PERIODICITY_SL16=16,
NFAPI_NR_SS_PERIODICITY_SL20=20,
NFAPI_NR_SS_PERIODICITY_SL40=40,
NFAPI_NR_SS_PERIODICITY_SL80=80,
NFAPI_NR_SS_PERIODICITY_SL160=160,
NFAPI_NR_SS_PERIODICITY_SL320=320,
NFAPI_NR_SS_PERIODICITY_SL640=640,
NFAPI_NR_SS_PERIODICITY_SL1280=1280,
NFAPI_NR_SS_PERIODICITY_SL2560=2560
} nfapi_nr_search_space_monitoring_periodicity_e;
typedef enum {
NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_DEFAULT_A=0,
NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_DEFAULT_B,
NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_DEFAULT_C,
NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_ALLOC_LIST
} nfapi_nr_pdsch_time_domain_alloc_type_e;
typedef enum {
NFAPI_NR_PDSCH_MAPPING_TYPE_A=0,
NFAPI_NR_PDSCH_MAPPING_TYPE_B
} nfapi_nr_pdsch_mapping_type_e;
typedef enum {
NFAPI_NR_PDSCH_RBG_CONFIG_TYPE1=0,
NFAPI_NR_PDSCH_RBG_CONFIG_TYPE2
} nfapi_nr_pdsch_rbg_config_type_e;
typedef enum {
NFAPI_NR_PRG_GRANULARITY_2=2,
NFAPI_NR_PRG_GRANULARITY_4=4,
NFAPI_NR_PRG_GRANULARITY_WIDEBAND
} nfapi_nr_prg_granularity_e;
typedef enum {
NFAPI_NR_PRB_BUNDLING_TYPE_STATIC=0,
NFAPI_NR_PRB_BUNDLING_TYPE_DYNAMIC
} nfapi_nr_prb_bundling_type_e;
typedef enum {
NFAPI_NR_MCS_TABLE_QAM64_LOW_SE=0,
NFAPI_NR_MCS_TABLE_QAM256
} nfapi_nr_pdsch_mcs_table_e;
typedef enum {
NFAPI_NR_DMRS_TYPE1=0,
NFAPI_NR_DMRS_TYPE2
} nfapi_nr_dmrs_type_e;
// P7 Sub Structures
typedef struct {
nfapi_tl_t tl;
uint8_t format_indicator; //1 bit
uint16_t frequency_domain_assignment; //up to 16 bits
uint8_t time_domain_assignment; // 4 bits
uint8_t frequency_hopping_flag; //1 bit
uint8_t ra_preamble_index; //6 bits
uint8_t ss_pbch_index; //6 bits
uint8_t prach_mask_index; //4 bits
uint8_t vrb_to_prb_mapping; //0 or 1 bit
uint8_t mcs; //5 bits
uint8_t ndi; //1 bit
uint8_t rv; //2 bits
uint8_t harq_pid; //4 bits
uint8_t dai; //0, 2 or 4 bits
uint8_t dai1; //1 or 2 bits
uint8_t dai2; //0 or 2 bits
uint8_t tpc; //2 bits
uint8_t pucch_resource_indicator; //3 bits
uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits
uint8_t short_messages_indicator; //2 bits
uint8_t short_messages; //8 bits
uint8_t tb_scaling; //2 bits
uint8_t carrier_indicator; //0 or 3 bits
uint8_t bwp_indicator; //0, 1 or 2 bits
uint8_t prb_bundling_size_indicator; //0 or 1 bits
uint8_t rate_matching_indicator; //0, 1 or 2 bits
uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits
uint8_t transmission_configuration_indication; //0 or 3 bits
uint8_t srs_request; //2 bits
uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits
uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit
uint8_t dmrs_sequence_initialization; //0 or 1 bit
uint8_t srs_resource_indicator;
uint8_t precoding_information;
uint8_t csi_request;
uint8_t ptrs_dmrs_association;
uint8_t beta_offset_indicator; //0 or 2 bits
uint8_t slot_format_indicator_count;
uint8_t *slot_format_indicators;
uint8_t pre_emption_indication_count;
uint16_t *pre_emption_indications; //14 bit
uint8_t block_number_count;
uint8_t *block_numbers;
uint8_t ul_sul_indicator; //0 or 1 bit
uint8_t antenna_ports;
uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
uint16_t padding;
} nfapi_nr_dl_config_dci_dl_pdu_rel15_t;
//#define NFAPI_NR_DL_CONFIG_REQUEST_DCI_DL_PDU_REL15_TAG 0x????
typedef struct{
nfapi_tl_t tl;
uint8_t coreset_id;
uint64_t frequency_domain_resources;
uint8_t duration;
uint8_t cce_reg_mapping_type;
uint8_t reg_bundle_size;
uint8_t interleaver_size;
uint8_t shift_index;
uint8_t precoder_granularity;
uint8_t tci_state_id;
uint8_t tci_present_in_dci;
uint32_t dmrs_scrambling_id;
} nfapi_nr_coreset_t;
typedef struct{
nfapi_tl_t tl;
uint8_t search_space_id;
uint8_t coreset_id;
uint8_t search_space_type;
uint8_t duration;
uint8_t css_formats_0_0_and_1_0;
uint8_t css_format_2_0;
uint8_t css_format_2_1;
uint8_t css_format_2_2;
uint8_t css_format_2_3;
uint8_t uss_dci_formats;
uint16_t srs_monitoring_periodicity;
uint16_t slot_monitoring_periodicity;
uint16_t slot_monitoring_offset;
uint32_t monitoring_symbols_in_slot;
uint16_t number_of_candidates[NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS];
} nfapi_nr_search_space_t;
typedef struct {
nfapi_tl_t tl;
uint16_t rnti;
uint8_t rnti_type;
uint8_t dci_format;
/// Number of CRB in BWP that this DCI configures
uint16_t n_RB_BWP;
uint8_t config_type;
uint8_t search_space_type;
uint8_t common_search_space_type;
uint8_t aggregation_level;
uint8_t n_rb;
uint8_t n_symb;
int8_t rb_offset;
uint8_t cr_mapping_type;
uint8_t reg_bundle_size;
uint8_t interleaver_size;
uint8_t shift_index;
uint8_t mux_pattern;
uint8_t precoder_granularity;
uint8_t first_slot;
uint8_t first_symbol;
uint8_t nb_ss_sets_per_slot;
uint8_t nb_slots;
uint8_t sfn_mod2;
uint16_t scrambling_id;
nfapi_bf_vector_t bf_vector;
} nfapi_nr_dl_config_pdcch_parameters_rel15_t;
typedef struct {
nfapi_tl_t tl;
uint16_t length;
int16_t pdu_index;
uint16_t transmission_power;
} nfapi_nr_dl_config_bch_pdu_rel15_t;
#define NFAPI_NR_DL_CONFIG_REQUEST_BCH_PDU_REL15_TAG 0x5025
typedef struct {
nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15;
} nfapi_nr_dl_config_bch_pdu;
typedef struct {
nfapi_tl_t tl;
uint16_t length;
uint8_t pdu_index;
uint16_t rnti;
uint16_t nb_mod_symbols;
uint8_t time_allocation_type;
uint8_t freq_allocation_type;
uint16_t start_prb;
uint16_t n_prb;
uint8_t start_symbol;
uint8_t nb_symbols;
uint8_t mcs_idx;
uint8_t mcs_table;
uint8_t ndi;
uint8_t nb_codewords;
uint8_t nb_layers;
uint16_t coding_rate;
uint8_t modulation;
uint8_t modulation_order;
uint32_t transport_block_size;
uint8_t nb_re_dmrs;
uint8_t time_alloc_list_flag;
uint8_t time_alloc_list;
uint8_t rbg_list;
uint8_t virtual_resource_block_assignment_flag;
uint32_t resource_block_coding;
uint8_t redundancy_version;
uint8_t transport_blocks;
uint8_t transmission_scheme;
uint8_t number_of_subbands;
uint8_t codebook_index[NFAPI_MAX_NUM_SUBBANDS];
uint8_t ue_category_capacity;
uint8_t pa;
uint8_t delta_power_offset_index;
uint8_t ngap;
uint8_t transmission_mode;
uint8_t num_bf_prb_per_subband;
uint8_t num_bf_vector;
nfapi_bf_vector_t bf_vector[NFAPI_MAX_BF_VECTORS];
}nfapi_nr_dl_config_dlsch_pdu_rel15_t;
#define NFAPI_NR_DL_CONFIG_REQUEST_DLSCH_PDU_REL15_TAG
typedef struct {
nfapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_pdu_rel15;
} nfapi_nr_dl_config_dlsch_pdu;
typedef struct {
nfapi_tl_t tl;
nfapi_nr_search_space_t pagingSearchSpace;
nfapi_nr_coreset_t pagingControlResourceSets;
}nfapi_nr_dl_config_pch_pdu_rel15_t;
typedef struct {
} nfapi_nr_dl_config_nbch_pdu_rel15_t;
typedef struct {
} nfapi_nr_dl_config_npdcch_pdu_rel15_t;
typedef struct {
} nfapi_nr_dl_config_ndlsch_pdu_rel15_t;
typedef struct {
nfapi_nr_dl_config_dci_dl_pdu_rel15_t dci_dl_pdu_rel15;
nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params_rel15;
} nfapi_nr_dl_config_dci_dl_pdu;
typedef struct {
uint8_t pdu_type;
uint8_t pdu_size;
union {
nfapi_nr_dl_config_dci_dl_pdu dci_dl_pdu;
nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15;
nfapi_nr_dl_config_dlsch_pdu dlsch_pdu;
nfapi_nr_dl_config_pch_pdu_rel15_t pch_pdu_rel15;
nfapi_nr_dl_config_nbch_pdu_rel15_t nbch_pdu_rel15;
nfapi_nr_dl_config_npdcch_pdu_rel15_t npdcch_pdu_rel15;
nfapi_nr_dl_config_ndlsch_pdu_rel15_t ndlsch_pdu_rel15;
};
} nfapi_nr_dl_config_request_pdu_t;
typedef struct {
nfapi_tl_t tl;
uint8_t number_dci;
uint8_t number_pdu;
uint8_t number_pdsch_rnti;
nfapi_nr_dl_config_request_pdu_t *dl_config_pdu_list;
} nfapi_nr_dl_config_request_body_t;
typedef struct {
nfapi_p7_message_header_t header;
uint16_t sfn_sf;
nfapi_nr_dl_config_request_body_t dl_config_request_body;
nfapi_vendor_extension_tlv_t vendor_extension;
} nfapi_nr_dl_config_request_t;
typedef enum {nr_pusch_freq_hopping_disabled = 0 ,
nr_pusch_freq_hopping_enabled = 1
} nr_pusch_freq_hopping_t;
typedef struct{
uint8_t aperiodicSRS_ResourceTrigger;
} nfapi_nr_ul_srs_config_t;
typedef struct {
uint8_t bandwidth_part_ind;
uint16_t number_rbs;
uint16_t start_rb;
uint8_t frame_offset;
uint16_t number_symbols;
uint16_t start_symbol;
uint8_t length_dmrs;
nr_pusch_freq_hopping_t pusch_freq_hopping;
uint8_t mcs;
uint8_t Qm;
uint16_t R;
uint8_t ndi;
uint8_t rv;
int8_t accumulated_delta_PUSCH;
int8_t absolute_delta_PUSCH;
uint8_t n_layers;
uint8_t tpmi;
uint8_t n_dmrs_cdm_groups;
uint8_t dmrs_ports[4];
uint8_t n_front_load_symb;
nfapi_nr_ul_srs_config_t srs_config;
uint8_t csi_reportTriggerSize;
uint8_t maxCodeBlockGroupsPerTransportBlock;
uint8_t ptrs_dmrs_association_port;
uint8_t beta_offset_ind;
} nfapi_nr_ul_config_ulsch_pdu_rel15_t;
typedef struct {
uint16_t rnti;
nfapi_nr_ul_config_ulsch_pdu_rel15_t ulsch_pdu_rel15;
} nfapi_nr_ul_config_ulsch_pdu;
#endif
nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h
+1402
View File
File diff suppressed because it is too large Load Diff
nfapi/open-nFAPI/vnf/public_inc/nfapi_vnf_interface.h
+2
View File
@@ -18,6 +18,7 @@
#define _NFAPI_VNF_INTERFACE_H_
#include "nfapi_interface.h"
#include "nfapi_nr_interface.h"
#include "debug.h"
#include "netinet/in.h"
@@ -937,6 +938,7 @@ int nfapi_vnf_p7_del_pnf(nfapi_vnf_p7_config_t* config, int phy_id);
* may be released after this function call has returned or at a later pointer
*/
int nfapi_vnf_p7_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_dl_config_request_t* req);
int nfapi_vnf_p7_nr_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_nr_dl_config_request_t* req);
/*! Send the UL_CONFIG.request
* \param config A pointer to the vnf p7 configuration
nfapi/open-nFAPI/vnf/src/vnf_p7.c
+4 -2
View File
@@ -376,9 +376,11 @@ int send_mac_subframe_indications(vnf_p7_t* vnf_p7)
if(curr->in_sync == 1)
{
// ask for subframes in the future
uint16_t sfn_sf_adv = increment_sfn_sf_by(curr->sfn_sf, 2);
//uint16_t sfn_sf_adv = increment_sfn_sf_by(curr->sfn_sf, 2);
vnf_p7->_public.subframe_indication(&(vnf_p7->_public), curr->phy_id, sfn_sf_adv);
//vnf_p7->_public.subframe_indication(&(vnf_p7->_public), curr->phy_id, sfn_sf_adv);
// suggestion fix by Haruki NAOI
vnf_p7->_public.subframe_indication(&(vnf_p7->_public), curr->phy_id, curr->sfn_sf);
}
curr = curr->next;
nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c
+11
View File
@@ -482,6 +482,17 @@ int nfapi_vnf_p7_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_dl_config_re
return vnf_p7_pack_and_send_p7_msg(vnf_p7, &req->header);
}
int nfapi_vnf_p7_nr_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_nr_dl_config_request_t* req)
{
//NFAPI_TRACE(NFAPI_TRACE_INFO, "%s(config:%p req:%p)\n", __FUNCTION__, config, req);
if(config == 0 || req == 0)
return -1;
vnf_p7_t* vnf_p7 = (vnf_p7_t*)config;
return vnf_p7_pack_and_send_p7_msg(vnf_p7, &req->header);
}
int nfapi_vnf_p7_ul_config_req(nfapi_vnf_p7_config_t* config, nfapi_ul_config_request_t* req)
{
if(config == 0 || req == 0)