bugfix: fix timing advance
- re-use ta_timer - when ta_timer is running: - no TA sent to UE - no TA from UE (for UE to have time to apply previous TA command) - decrease ta_timer every TTI - be careful to use correct value of ta_update (31 means no TA) Maybe not correct, to be checked.
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@@ -749,8 +749,8 @@ void generate_Msg4(module_id_t module_idP,int CC_idP,frame_t frameP,sub_frame_t
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(unsigned short*)&rrc_sdu_length, //
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&lcid, // sdu_lcid
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255, // no drx
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0, // no timing advance
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RA_template->cont_res_id, // contention res id
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31, // no timing advance
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RA_template->cont_res_id, // contention res id
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msg4_padding, // no padding
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msg4_post_padding);
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@@ -913,8 +913,8 @@ void generate_Msg4(module_id_t module_idP,int CC_idP,frame_t frameP,sub_frame_t
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(unsigned short*)&rrc_sdu_length, //
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&lcid, // sdu_lcid
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255, // no drx
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0, // no timing advance
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RA_template->cont_res_id, // contention res id
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31, // no timing advance
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RA_template->cont_res_id, // contention res id
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msg4_padding, // no padding
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msg4_post_padding);
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@@ -169,7 +169,7 @@ generate_dlsch_header(
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last_size=1;
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}
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if (timing_advance_cmd != 0) {
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if (timing_advance_cmd != 31) {
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if (first_element>0) {
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mac_header_ptr->E = 1;
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mac_header_ptr++;
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@@ -457,6 +457,7 @@ schedule_ue_spec(
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nfapi_dl_config_request_body_t *dl_req;
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nfapi_dl_config_request_pdu_t *dl_config_pdu;
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int tdd_sfa;
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int ta_update;
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#if 0
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if (UE_list->head==-1) {
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@@ -816,7 +817,18 @@ schedule_ue_spec(
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// check first for RLC data on DCCH
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// add the length for all the control elements (timing adv, drx, etc) : header + payload
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ta_len = (ue_sched_ctl->ta_update!=0) ? 2 : 0;
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if (ue_sched_ctl->ta_timer == 0) {
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ta_update = ue_sched_ctl->ta_update;
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/* if we send TA then set timer to not send it for a while */
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if (ta_update != 31)
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ue_sched_ctl->ta_timer = 20;
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/* reset ta_update */
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ue_sched_ctl->ta_update = 31;
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} else {
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ta_update = 31;
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}
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ta_len = (ta_update != 31) ? 2 : 0;
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header_len_dcch = 2; // 2 bytes DCCH SDU subheader
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@@ -1094,17 +1106,17 @@ schedule_ue_spec(
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sdu_lengths, //
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sdu_lcids,
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255, // no drx
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ue_sched_ctl->ta_update, // timing advance
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ta_update, // timing advance
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NULL, // contention res id
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padding,
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post_padding);
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//#ifdef DEBUG_eNB_SCHEDULER
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if (ue_sched_ctl->ta_update) {
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if (ta_update != 31) {
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LOG_D(MAC,
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"[eNB %d][DLSCH] Frame %d Generate header for UE_id %d on CC_id %d: sdu_length_total %d, num_sdus %d, sdu_lengths[0] %d, sdu_lcids[0] %d => payload offset %d,timing advance value : %d, padding %d,post_padding %d,(mcs %d, TBS %d, nb_rb %d),header_dcch %d, header_dtch %d\n",
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module_idP,frameP, UE_id, CC_id, sdu_length_total,num_sdus,sdu_lengths[0],sdu_lcids[0],offset,
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ue_sched_ctl->ta_update,padding,post_padding,mcs,TBS,nb_rb,header_len_dcch,header_len_dtch);
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ta_update,padding,post_padding,mcs,TBS,nb_rb,header_len_dcch,header_len_dtch);
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}
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//#endif
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#ifdef DEBUG_eNB_SCHEDULER
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@@ -1116,6 +1128,7 @@ schedule_ue_spec(
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LOG_T(MAC,"\n");
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#endif
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// cycle through SDUs and place in dlsch_buffer
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memcpy(&UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0][offset],dlsch_buffer,sdu_length_total);
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// memcpy(RC.mac[0].DLSCH_pdu[0][0].payload[0][offset],dcch_buffer,sdu_lengths[0]);
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@@ -1724,6 +1724,8 @@ int add_new_ue(module_id_t mod_idP, int cc_idP, rnti_t rntiP,int harq_pidP
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memset((void*)&UE_list->UE_sched_ctrl[UE_id],0,sizeof(UE_sched_ctrl));
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memset((void*)&UE_list->eNB_UE_stats[cc_idP][UE_id],0,sizeof(eNB_UE_STATS));
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UE_list->UE_sched_ctrl[UE_id].ta_update = 31;
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for (j=0; j<8; j++) {
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UE_list->UE_template[cc_idP][UE_id].oldNDI[j] = (j==0)?1:0; // 1 because first transmission is with format1A (Msg4) for harq_pid 0
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UE_list->UE_template[cc_idP][UE_id].oldNDI_UL[j] = (j==harq_pidP)?0:1; // 1st transmission is with Msg3;
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@@ -115,7 +115,9 @@ void rx_sdu(const module_id_t enb_mod_idP,
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UE_list->UE_sched_ctrl[UE_id].ul_inactivity_timer = 0;
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UE_list->UE_sched_ctrl[UE_id].ul_failure_timer = 0;
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UE_list->UE_sched_ctrl[UE_id].ul_scheduled &= (~(1<<harq_pid));
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UE_list->UE_sched_ctrl[UE_id].ta_update = timing_advance;
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/* don't take into account TA if timer is running */
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if (UE_list->UE_sched_ctrl[UE_id].ta_timer == 0)
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UE_list->UE_sched_ctrl[UE_id].ta_update = timing_advance;
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UE_list->UE_sched_ctrl[UE_id].ul_cqi = ul_cqi;
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UE_list->UE_sched_ctrl[UE_id].ul_consecutive_errors = 0;
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first_rb = UE_list->UE_template[CC_idP][UE_id].first_rb_ul[harq_pid];
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@@ -894,6 +894,8 @@ void dlsch_scheduler_pre_processor_reset (int module_idP,
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LOG_D(MAC,"Running preprocessor for UE %d (%x)\n",UE_id,rnti);
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// initialize harq_pid and round
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if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--;
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/*
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eNB_UE_stats *eNB_UE_stats;
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