bugfix: fix timing advance
- re-use ta_timer - when ta_timer is running: - no TA sent to UE - no TA from UE (for UE to have time to apply previous TA command) - decrease ta_timer every TTI - be careful to use correct value of ta_update (31 means no TA) Maybe not correct, to be checked.
This commit is contained in:
@@ -1525,12 +1525,8 @@ void init_te_thread(PHY_VARS_eNB *eNB,pthread_attr_t *attr_te) {
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}
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}
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void fill_rx_indication(PHY_VARS_eNB *eNB,int UE_id,int frame,int subframe)
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{
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void fill_rx_indication(PHY_VARS_eNB *eNB,int UE_id,int frame,int subframe) {
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nfapi_rx_indication_pdu_t *pdu;
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nfapi_rx_indication_pdu_t *pdu;
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int timing_advance_update;
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int timing_advance_update;
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@@ -1551,50 +1547,36 @@ void fill_rx_indication(PHY_VARS_eNB *eNB,int UE_id,int frame,int subframe) {
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sync_pos = lte_est_timing_advance_pusch(eNB,UE_id);
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sync_pos = lte_est_timing_advance_pusch(eNB,UE_id);
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timing_advance_update = sync_pos - eNB->frame_parms.nb_prefix_samples/4; //to check
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timing_advance_update = sync_pos - eNB->frame_parms.nb_prefix_samples/4; //to check
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// if (timing_advance_update > 10) { dump_ulsch(eNB,frame,subframe,UE_id); exit(-1);}
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// if (timing_advance_update > 10) { dump_ulsch(eNB,frame,subframe,UE_id); exit(-1);}
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// if (timing_advance_update < -10) { dump_ulsch(eNB,frame,subframe,UE_id); exit(-1);}
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// if (timing_advance_update < -10) { dump_ulsch(eNB,frame,subframe,UE_id); exit(-1);}
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switch (eNB->frame_parms.N_RB_DL) {
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switch (eNB->frame_parms.N_RB_DL) {
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case 6:
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case 6: /* nothing to do */ break;
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pdu->rx_indication_rel8.timing_advance = timing_advance_update;
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case 15: timing_advance_update /= 2; break;
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break;
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case 25: timing_advance_update /= 4; break;
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case 15:
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case 50: timing_advance_update /= 8; break;
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pdu->rx_indication_rel8.timing_advance = timing_advance_update/2;
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case 75: timing_advance_update /= 12; break;
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break;
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case 100: timing_advance_update /= 16; break;
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case 25:
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default: abort();
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pdu->rx_indication_rel8.timing_advance = timing_advance_update/4;
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break;
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case 50:
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pdu->rx_indication_rel8.timing_advance = timing_advance_update/8;
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break;
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case 75:
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pdu->rx_indication_rel8.timing_advance = timing_advance_update/12;
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break;
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case 100:
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pdu->rx_indication_rel8.timing_advance = timing_advance_update/16;
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break;
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}
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}
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// put timing advance command in 0..63 range
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// put timing advance command in 0..63 range
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pdu->rx_indication_rel8.timing_advance += 31;
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timing_advance_update += 31;
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if (pdu->rx_indication_rel8.timing_advance < 0) pdu->rx_indication_rel8.timing_advance = 0;
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if (timing_advance_update < 0) timing_advance_update = 0;
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if (pdu->rx_indication_rel8.timing_advance > 63) pdu->rx_indication_rel8.timing_advance = 63;
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if (timing_advance_update > 63) timing_advance_update = 63;
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pdu->rx_indication_rel8.timing_advance = timing_advance_update;
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// estimate UL_CQI for MAC (from antenna port 0 only)
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// estimate UL_CQI for MAC (from antenna port 0 only)
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int SNRtimes10 = dB_fixed_times10(eNB->pusch_vars[UE_id]->ulsch_power[0]) - 200;//(10*eNB->measurements.n0_power_dB[0]);
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int SNRtimes10 = dB_fixed_times10(eNB->pusch_vars[UE_id]->ulsch_power[0]) - 200;//(10*eNB->measurements.n0_power_dB[0]);
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if (SNRtimes10 < -640) pdu->rx_indication_rel8.ul_cqi=0;
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if (SNRtimes10 < -640) pdu->rx_indication_rel8.ul_cqi=0;
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else if (SNRtimes10 > 635) pdu->rx_indication_rel8.ul_cqi=255;
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else if (SNRtimes10 > 635) pdu->rx_indication_rel8.ul_cqi=255;
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else pdu->rx_indication_rel8.ul_cqi=(640+SNRtimes10)/5;
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else pdu->rx_indication_rel8.ul_cqi=(640+SNRtimes10)/5;
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LOG_D(PHY,"[PUSCH %d] Filling RX_indication with SNR %d (%d), timing_advance %d (update %d)\n",
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LOG_D(PHY,"[PUSCH %d] Filling RX_indication with SNR %d (%d), timing_advance %d (update %d)\n",
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harq_pid,SNRtimes10,pdu->rx_indication_rel8.ul_cqi,pdu->rx_indication_rel8.timing_advance,
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harq_pid,SNRtimes10,pdu->rx_indication_rel8.ul_cqi,pdu->rx_indication_rel8.timing_advance,
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timing_advance_update);
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timing_advance_update);
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eNB->UL_INFO.rx_ind.number_of_pdus++;
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eNB->UL_INFO.rx_ind.number_of_pdus++;
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pthread_mutex_unlock(&eNB->UL_INFO_mutex);
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pthread_mutex_unlock(&eNB->UL_INFO_mutex);
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}
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}
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void release_harq(PHY_VARS_eNB *eNB,int UE_id,int tb,uint16_t frame,uint8_t subframe,uint16_t mask) {
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void release_harq(PHY_VARS_eNB *eNB,int UE_id,int tb,uint16_t frame,uint8_t subframe,uint16_t mask) {
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@@ -749,7 +749,7 @@ void generate_Msg4(module_id_t module_idP,int CC_idP,frame_t frameP,sub_frame_t
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(unsigned short*)&rrc_sdu_length, //
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(unsigned short*)&rrc_sdu_length, //
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&lcid, // sdu_lcid
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&lcid, // sdu_lcid
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255, // no drx
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255, // no drx
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0, // no timing advance
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31, // no timing advance
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RA_template->cont_res_id, // contention res id
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RA_template->cont_res_id, // contention res id
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msg4_padding, // no padding
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msg4_padding, // no padding
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msg4_post_padding);
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msg4_post_padding);
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@@ -913,7 +913,7 @@ void generate_Msg4(module_id_t module_idP,int CC_idP,frame_t frameP,sub_frame_t
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(unsigned short*)&rrc_sdu_length, //
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(unsigned short*)&rrc_sdu_length, //
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&lcid, // sdu_lcid
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&lcid, // sdu_lcid
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255, // no drx
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255, // no drx
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0, // no timing advance
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31, // no timing advance
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RA_template->cont_res_id, // contention res id
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RA_template->cont_res_id, // contention res id
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msg4_padding, // no padding
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msg4_padding, // no padding
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msg4_post_padding);
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msg4_post_padding);
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@@ -169,7 +169,7 @@ generate_dlsch_header(
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last_size=1;
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last_size=1;
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}
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}
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if (timing_advance_cmd != 0) {
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if (timing_advance_cmd != 31) {
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if (first_element>0) {
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if (first_element>0) {
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mac_header_ptr->E = 1;
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mac_header_ptr->E = 1;
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mac_header_ptr++;
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mac_header_ptr++;
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@@ -457,6 +457,7 @@ schedule_ue_spec(
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nfapi_dl_config_request_body_t *dl_req;
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nfapi_dl_config_request_body_t *dl_req;
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nfapi_dl_config_request_pdu_t *dl_config_pdu;
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nfapi_dl_config_request_pdu_t *dl_config_pdu;
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int tdd_sfa;
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int tdd_sfa;
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int ta_update;
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#if 0
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#if 0
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if (UE_list->head==-1) {
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if (UE_list->head==-1) {
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@@ -816,7 +817,18 @@ schedule_ue_spec(
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// check first for RLC data on DCCH
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// check first for RLC data on DCCH
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// add the length for all the control elements (timing adv, drx, etc) : header + payload
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// add the length for all the control elements (timing adv, drx, etc) : header + payload
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ta_len = (ue_sched_ctl->ta_update!=0) ? 2 : 0;
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if (ue_sched_ctl->ta_timer == 0) {
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ta_update = ue_sched_ctl->ta_update;
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/* if we send TA then set timer to not send it for a while */
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if (ta_update != 31)
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ue_sched_ctl->ta_timer = 20;
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/* reset ta_update */
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ue_sched_ctl->ta_update = 31;
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} else {
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ta_update = 31;
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}
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ta_len = (ta_update != 31) ? 2 : 0;
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header_len_dcch = 2; // 2 bytes DCCH SDU subheader
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header_len_dcch = 2; // 2 bytes DCCH SDU subheader
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@@ -1094,17 +1106,17 @@ schedule_ue_spec(
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sdu_lengths, //
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sdu_lengths, //
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sdu_lcids,
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sdu_lcids,
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255, // no drx
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255, // no drx
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ue_sched_ctl->ta_update, // timing advance
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ta_update, // timing advance
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NULL, // contention res id
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NULL, // contention res id
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padding,
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padding,
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post_padding);
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post_padding);
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//#ifdef DEBUG_eNB_SCHEDULER
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//#ifdef DEBUG_eNB_SCHEDULER
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if (ue_sched_ctl->ta_update) {
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if (ta_update != 31) {
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LOG_D(MAC,
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LOG_D(MAC,
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"[eNB %d][DLSCH] Frame %d Generate header for UE_id %d on CC_id %d: sdu_length_total %d, num_sdus %d, sdu_lengths[0] %d, sdu_lcids[0] %d => payload offset %d,timing advance value : %d, padding %d,post_padding %d,(mcs %d, TBS %d, nb_rb %d),header_dcch %d, header_dtch %d\n",
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"[eNB %d][DLSCH] Frame %d Generate header for UE_id %d on CC_id %d: sdu_length_total %d, num_sdus %d, sdu_lengths[0] %d, sdu_lcids[0] %d => payload offset %d,timing advance value : %d, padding %d,post_padding %d,(mcs %d, TBS %d, nb_rb %d),header_dcch %d, header_dtch %d\n",
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module_idP,frameP, UE_id, CC_id, sdu_length_total,num_sdus,sdu_lengths[0],sdu_lcids[0],offset,
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module_idP,frameP, UE_id, CC_id, sdu_length_total,num_sdus,sdu_lengths[0],sdu_lcids[0],offset,
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ue_sched_ctl->ta_update,padding,post_padding,mcs,TBS,nb_rb,header_len_dcch,header_len_dtch);
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ta_update,padding,post_padding,mcs,TBS,nb_rb,header_len_dcch,header_len_dtch);
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}
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}
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//#endif
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//#endif
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#ifdef DEBUG_eNB_SCHEDULER
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#ifdef DEBUG_eNB_SCHEDULER
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@@ -1116,6 +1128,7 @@ schedule_ue_spec(
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LOG_T(MAC,"\n");
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LOG_T(MAC,"\n");
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#endif
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#endif
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// cycle through SDUs and place in dlsch_buffer
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// cycle through SDUs and place in dlsch_buffer
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memcpy(&UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0][offset],dlsch_buffer,sdu_length_total);
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memcpy(&UE_list->DLSCH_pdu[CC_id][0][UE_id].payload[0][offset],dlsch_buffer,sdu_length_total);
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// memcpy(RC.mac[0].DLSCH_pdu[0][0].payload[0][offset],dcch_buffer,sdu_lengths[0]);
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// memcpy(RC.mac[0].DLSCH_pdu[0][0].payload[0][offset],dcch_buffer,sdu_lengths[0]);
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@@ -1724,6 +1724,8 @@ int add_new_ue(module_id_t mod_idP, int cc_idP, rnti_t rntiP,int harq_pidP
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memset((void*)&UE_list->UE_sched_ctrl[UE_id],0,sizeof(UE_sched_ctrl));
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memset((void*)&UE_list->UE_sched_ctrl[UE_id],0,sizeof(UE_sched_ctrl));
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memset((void*)&UE_list->eNB_UE_stats[cc_idP][UE_id],0,sizeof(eNB_UE_STATS));
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memset((void*)&UE_list->eNB_UE_stats[cc_idP][UE_id],0,sizeof(eNB_UE_STATS));
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UE_list->UE_sched_ctrl[UE_id].ta_update = 31;
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for (j=0; j<8; j++) {
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for (j=0; j<8; j++) {
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UE_list->UE_template[cc_idP][UE_id].oldNDI[j] = (j==0)?1:0; // 1 because first transmission is with format1A (Msg4) for harq_pid 0
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UE_list->UE_template[cc_idP][UE_id].oldNDI[j] = (j==0)?1:0; // 1 because first transmission is with format1A (Msg4) for harq_pid 0
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UE_list->UE_template[cc_idP][UE_id].oldNDI_UL[j] = (j==harq_pidP)?0:1; // 1st transmission is with Msg3;
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UE_list->UE_template[cc_idP][UE_id].oldNDI_UL[j] = (j==harq_pidP)?0:1; // 1st transmission is with Msg3;
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@@ -115,6 +115,8 @@ void rx_sdu(const module_id_t enb_mod_idP,
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UE_list->UE_sched_ctrl[UE_id].ul_inactivity_timer = 0;
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UE_list->UE_sched_ctrl[UE_id].ul_inactivity_timer = 0;
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UE_list->UE_sched_ctrl[UE_id].ul_failure_timer = 0;
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UE_list->UE_sched_ctrl[UE_id].ul_failure_timer = 0;
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UE_list->UE_sched_ctrl[UE_id].ul_scheduled &= (~(1<<harq_pid));
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UE_list->UE_sched_ctrl[UE_id].ul_scheduled &= (~(1<<harq_pid));
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/* don't take into account TA if timer is running */
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if (UE_list->UE_sched_ctrl[UE_id].ta_timer == 0)
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UE_list->UE_sched_ctrl[UE_id].ta_update = timing_advance;
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UE_list->UE_sched_ctrl[UE_id].ta_update = timing_advance;
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UE_list->UE_sched_ctrl[UE_id].ul_cqi = ul_cqi;
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UE_list->UE_sched_ctrl[UE_id].ul_cqi = ul_cqi;
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UE_list->UE_sched_ctrl[UE_id].ul_consecutive_errors = 0;
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UE_list->UE_sched_ctrl[UE_id].ul_consecutive_errors = 0;
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@@ -894,6 +894,8 @@ void dlsch_scheduler_pre_processor_reset (int module_idP,
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LOG_D(MAC,"Running preprocessor for UE %d (%x)\n",UE_id,rnti);
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LOG_D(MAC,"Running preprocessor for UE %d (%x)\n",UE_id,rnti);
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// initialize harq_pid and round
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// initialize harq_pid and round
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if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--;
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/*
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/*
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eNB_UE_stats *eNB_UE_stats;
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eNB_UE_stats *eNB_UE_stats;
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