Merge remote-tracking branch 'origin/remove-dead-code' into integration_2026_w05 (!3831)

semi-manual remove of not used #define commands

As i was upset to see all these #define with no code under, i made a
global pass to remove the obvious cases semi-manual remove of not used
bodies

manual script, then a lot of manual review

    grep -IRs "#define" ../openair* ../common/* ../executables/ ../nfapi/ ../radio/ | \
        fgrep -v '(' | fgrep -v '//' |awk '{print $2}' | egrep -v "#define *$n"| \
            while read n ; do
              grep -IRs $n ../openair* ../common/* ../executables/ ../nfapi/ ../radio/  | grep -v "#define *$n" | grep -q $n || echo $n;
            done

will give a decent list of #define never used.  Then, I think we should
keep lists of # define when it comes from standards, even if the code
doesn't use it right now
This commit is contained in:
Robert Schmidt
2026-01-29 08:23:41 +01:00
172 changed files with 32 additions and 2467 deletions
-1
View File
@@ -42,7 +42,6 @@
#endif
#define NR_LDPC_PROFILER_DETAIL
#define NR_LDPC_ENABLE_PARITY_CHECK
ldpc_interface_t ldpc_orig, ldpc_toCompare;
// 4-bit quantizer
-1
View File
@@ -38,7 +38,6 @@
#define MAX_TURBO_ITERATIONS_MBSFN 8
#define MAX_TURBO_ITERATIONS max_turbo_iterations
#define MAX_LDPC_ITERATIONS_MBSFN 4
#define LTE_NULL 2
typedef struct {
-1
View File
@@ -19,7 +19,6 @@
* contact@openairinterface.org
*/
extern double cpuf;
extern decoder_if_t *decoder16;
extern decoder_if_t *decoder8;
extern encoder_if_t *encoder;
-6
View File
@@ -30,15 +30,9 @@
#include <stdint.h> // for uint8/16/32_t
#define CRC24_A_NB_IoT 0
#define CRC24_B_NB_IoT 1
#define CRC16_NB_IoT 2
#define CRC8_NB_IoT 3
//#define MAX_TURBO_ITERATIONS_MBSFN 8 // no MBSFN
#define MAX_TURBO_ITERATIONS_NB_IoT 4
#define LTE_NULL_NB_IoT 2 // defined also in PHY/LTE_TRANSPORT/defs_NB_IoT.h
/** \fn uint32_t sub_block_interleaving_cc(uint32_t D, uint8_t *d,uint8_t *w)
\brief This is the subblock interleaving algorithm for convolutionally coded blocks from 36-212 (Release 13.4, 2017).
@@ -53,8 +53,6 @@
#define PRINT_CRC_CHECK(a)
#endif
// extern double cpuf;
#include "nfapi/open-nFAPI/nfapi/public_inc/nfapi_interface.h"
#include "nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h"
@@ -40,7 +40,6 @@
/** Number of columns in BG1 */
#define NR_LDPC_NCOL_BG1 68
/** Number of rows in BG1 */
#define NR_LDPC_NROW_BG1 46
/** Number of edges/entries in BG1 */
#define NR_LDPC_NUM_EDGE_BG1 316
/** Number of check node (CN) groups in BG1
@@ -67,9 +66,7 @@
/** Number of columns in BG2 */
#define NR_LDPC_NCOL_BG2 52
/** Number of rows in BG2 */
#define NR_LDPC_NROW_BG2 42
/** Number of edges/entries in BG2 */
#define NR_LDPC_NUM_EDGE_BG2 197
/** Number of check node (CN) groups in BG2
A CN group is defined by its number of connected bit nodes. */
#define NR_LDPC_NUM_CN_GROUPS_BG2 6
@@ -5,7 +5,6 @@
#ifndef __NR_POLAR_PUCCH_DEFS__H__
#define __NR_POLAR_PUCCH_DEFS__H__
#define NR_POLAR_PUCCH_PAYLOAD_BITS 16
// Ref. 38-212 v15.0.1
#define NR_POLAR_PUCCH_N_MAX 10 // uint8_t <------
@@ -16,7 +15,6 @@
// Ref. 38-212 v15.0.1, Section 7.1.5: Rate Matching
#define NR_POLAR_PUCCH_I_BIL 0 // uint8_t
#define NR_POLAR_PUCCH_E 864 // uint16_t
/*
* TEST CODE
@@ -35,23 +35,13 @@
#define NR_POLAR_UCI_PUCCH_MESSAGE_TYPE 2 // int8_t
#define NR_POLAR_PUCCH_CRC_ERROR_CORRECTION_BITS 3
#define NR_POLAR_PUCCH_PAYLOAD_BITS 32
#define NR_POLAR_PUCCH_E 32
// Ref. 38-212, Section 6.3.1.2.1
#define NR_POLAR_PUCCH_CRC_PARITY_BITS_SHORT 6
#define NR_POLAR_PUCCH_CRC_PARITY_BITS_LONG 11
#define NR_POLAR_PUCCH_I_SEG_LONG 1
#define NR_POLAR_PUCCH_I_SEG_SHORT 0
// Ref. 38-212, Section 6.3.1.3.1
#define NR_POLAR_PUCCH_N_MAX 10
#define NR_POLAR_PUCCH_I_IL 0
#define NR_POLAR_PUCCH_N_PC_SHORT 3
#define NR_POLAR_PUCCH_N_PC_LONG 0
#define NR_POLAR_PUCCH_N_PC_WM_LONG 0
#define NR_POLAR_PUCCH_N_PC_WM_SHORT 1
// Ref. 38-212, Section 6.3.1.4.1
#define NR_POLAR_PUCCH_I_BIL 1
@@ -41,7 +41,6 @@
#define NR_SMALL_BLOCK_CODED_BITS 32
#define L1d_CLS 64
uint32_t encodeSmallBlock(int in, int len);
-3
View File
@@ -24,9 +24,6 @@
#define MOD_TABLE_SIZE_SHORT 304
#define MOD_TABLE_QPSK_OFFSET 1
#define MOD_TABLE_16QAM_OFFSET 5
#define MOD_TABLE_64QAM_OFFSET 21
#define MOD_TABLE_PSS_OFFSET 85
short mod_table[MOD_TABLE_SIZE_SHORT] = {0,0,768,768,768,-768,-768,768,-768,-768,343,343,343,1030,1030,343,1030,1030,343,-343,343,-1030,1030,-343,1030,-1030,-343,343,-343,1030,-1030,343,-1030,1030,-343,-343,-343,-1030,-1030,-343,-1030,-1030,503,503,503,168,168,503,168,168,503,838,503,1173,168,838,168,1173,838,503,838,168,1173,503,1173,168,838,838,838,1173,1173,838,1173,1173,503,-503,503,-168,168,-503,168,-168,503,-838,503,-1173,168,-838,168,-1173,838,-503,838,-168,1173,-503,1173,-168,838,-838,838,-1173,1173,-838,1173,-1173,-503,503,-503,168,-168,503,-168,168,-503,838,-503,1173,-168,838,-168,1173,-838,503,-838,168,-1173,503,-1173,168,-838,838,-838,1173,-1173,838,-1173,1173,-503,-503,-503,-168,-168,-503,-168,-168,-503,-838,-503,-1173,-168,-838,-168,-1173,-838,-503,-838,-168,-1173,-503,-1173,-168,-838,-838,-838,-1173,-1173,-838,-1173,-1173,1086,0,1081,-108,1065,-215,1038,-320,1001,-422,954,-519,897,-612,832,-698,758,-777,677,-849,589,-912,495,-966,397,-1011,294,-1046,189,-1070,81,-1083,-27,-1086,-135,-1078,-242,-1059,-346,-1030,-447,-990,-543,-941,-634,-882,-719,-814,-796,-739,-866,-656,-927,-566,-979,-471,-1021,-371,-1053,-268,-1074,-162,-1085,-54,-1085,54,-1074,162,-1053,268,-1021,371,-979,471,-927,566,-866,656,-796,739,-719,814,-634,882,-543,941,-447,990,-346,1030,-242,1059,-135,1078,-27,1086,81,1083,189,1070,294,1045,397,1011,495,966,589,912,677,849,758,777,832,698,897,612,954,519,1001,422,1038,320,1065,215,1081,108,16384,0,8192,0,4096,0,2048,0};
#endif
-42
View File
@@ -699,7 +699,6 @@ struct DCI1A_RA_5MHz_TDD_1_6 {
} __attribute__ ((__packed__));
typedef struct DCI1A_RA_5MHz_TDD_1_6 DCI1A_RA_5MHz_TDD_1_6_t;
#define sizeof_DCI1A_RA_5MHz_TDD_1_6_t 27
/// DCI Format Type 1A (5 MHz, TDD, frame 0, 27 bits)
/*
@@ -717,7 +716,6 @@ struct DCI1A_5MHz_TDD_0 {
} __attribute__ ((__packed__));
typedef struct DCI1A_5MHz_TDD_0 DCI1A_5MHz_TDD_0_t;
#define sizeof_DCI1A_5MHz_TDD_0_t 27
*/
/// DCI Format Type 1B (5 MHz, FDD, 2 Antenna Ports, 27 bits)
@@ -745,7 +743,6 @@ struct DCI1B_5MHz_2A_FDD {
} __attribute__ ((__packed__));
typedef struct DCI1B_5MHz_2A_FDD DCI1B_5MHz_2A_FDD_t;
#define sizeof_DCI1B_5MHz_FDD_t 27
/// DCI Format Type 1B (5 MHz, TDD, 2 Antenna Ports, 29 bits)
struct DCI1B_5MHz_2A_TDD {
@@ -772,7 +769,6 @@ struct DCI1B_5MHz_2A_TDD {
} __attribute__ ((__packed__));
typedef struct DCI1B_5MHz_2A_TDD DCI1B_5MHz_2A_TDD_t;
#define sizeof_DCI1B_5MHz_2A_TDD_t 29
/// DCI Format Type 1B (5 MHz, FDD, 4 Antenna Ports, 28 bits)
struct DCI1B_5MHz_4A_FDD {
@@ -797,7 +793,6 @@ struct DCI1B_5MHz_4A_FDD {
} __attribute__ ((__packed__));
typedef struct DCI1B_5MHz_4A_FDD DCI1B_5MHz_4A_FDD_t;
#define sizeof_DCI1B_5MHz_4A_FDD_t 28
/// DCI Format Type 1B (5 MHz, TDD, 4 Antenna Ports, 31 bits)
struct DCI1B_5MHz_4A_TDD {
@@ -824,7 +819,6 @@ struct DCI1B_5MHz_4A_TDD {
} __attribute__ ((__packed__));
typedef struct DCI1B_5MHz_4A_TDD DCI1B_5MHz_4A_TDD_t;
#define sizeof_DCI1B_5MHz_4A_TDD_t 31
/// DCI Format Type 1C (1.4 MHz, 8 bits)
struct DCI1C_1_5MHz
@@ -876,7 +870,6 @@ struct DCI1C_15MHz
} __attribute__ ((__packed__));
typedef struct DCI1C_15MHz DCI1C_15MHz_t;
#define sizeof_DCI1C_15MHz_t X
/// DCI Format Type 1C (20 MHz, 15 bits)
struct DCI1C_20MHz
@@ -919,7 +912,6 @@ struct DCI1D_5MHz_2A_FDD {
} __attribute__ ((__packed__));
typedef struct DCI1D_5MHz_2A_FDD DCI1D_5MHz_2A_FDD_t;
#define sizeof_DCI1D_5MHz_2A_FDD_t 27
/// DCI Format Type 1D (5 MHz, TDD, 2 Antenna Ports, 30 bits)
struct DCI1D_5MHz_2A_TDD {
@@ -948,7 +940,6 @@ struct DCI1D_5MHz_2A_TDD {
} __attribute__ ((__packed__));
typedef struct DCI1D_5MHz_2A_TDD DCI1D_5MHz_2A_TDD_t;
#define sizeof_DCI1D_5MHz_2A_TDD_t 30
/// DCI Format Type 1D (5 MHz, FDD, 4 Antenna Ports, 29 bits)
struct DCI1D_5MHz_4A_FDD {
@@ -975,7 +966,6 @@ struct DCI1D_5MHz_4A_FDD {
} __attribute__ ((__packed__));
typedef struct DCI1D_5MHz_4A_FDD DCI1D_5MHz_4A_FDD_t;
#define sizeof_DCI1D_5MHz_4A_FDD_t 29
/// DCI Format Type 1D (5 MHz, TDD, 4 Antenna Ports, 33 bits)
struct DCI1D_5MHz_4A_TDD {
@@ -1006,7 +996,6 @@ struct DCI1D_5MHz_4A_TDD {
} __attribute__ ((__packed__));
typedef struct DCI1D_5MHz_4A_TDD DCI1D_5MHz_4A_TDD_t;
#define sizeof_DCI1D_5MHz_4A_TDD_t 33
///******************NEW DCI Format for MU-MIMO****************///////////
@@ -2121,7 +2110,6 @@ struct DCI2B_1_5MHz_TDD {
} __attribute__ ((__packed__));
typedef struct DCI2B_1_5MHz_TDD DCI2B_1_5MHz_TDD_t;
#define sizeof_DCI2B_1_5MHz_TDD_t 33
/// DCI Format Type 2B (5 MHz, TDD, 39 bits)
struct DCI2B_5MHz_TDD {
@@ -2156,7 +2144,6 @@ struct DCI2B_5MHz_TDD {
} __attribute__ ((__packed__));
typedef struct DCI2B_5MHz_TDD DCI2B_5MHz_TDD_t;
#define sizeof_DCI2B_5MHz_TDD_t 39
/// DCI Format Type 2B (10 MHz, TDD, 43 bits)
struct DCI2B_10MHz_TDD {
@@ -2191,7 +2178,6 @@ struct DCI2B_10MHz_TDD {
} __attribute__ ((__packed__));
typedef struct DCI2B_10MHz_TDD DCI2B_10MHz_TDD_t;
#define sizeof_DCI2B_10MHz_TDD_t 43
/// DCI Format Type 2B (20 MHz, TDD, 51 bits)
struct DCI2B_20MHz_TDD {
@@ -2226,7 +2212,6 @@ struct DCI2B_20MHz_TDD {
} __attribute__ ((__packed__));
typedef struct DCI2B_20MHz_TDD DCI2B_20MHz_TDD_t;
#define sizeof_DCI2B_20MHz_TDD_t 51
/// DCI Format Type 2B (1.5 MHz, FDD, 28 bits)
struct DCI2B_1_5MHz_FDD {
@@ -2255,7 +2240,6 @@ struct DCI2B_1_5MHz_FDD {
} __attribute__ ((__packed__));
typedef struct DCI2B_1_5MHz_FDD DCI2B_1_5MHz_FDD_t;
#define sizeof_DCI2B_1_5MHz_FDD_t 28
/// DCI Format Type 2B (5 MHz, FDD, 36 bits)
struct DCI2B_5MHz_FDD {
@@ -2285,7 +2269,6 @@ struct DCI2B_5MHz_FDD {
uint64_t rah:1;
} __attribute__ ((__packed__));
#define sizeof_DCI2B_5MHz_FDD_t 36
typedef struct DCI2B_5MHz_FDD DCI2B_5MHz_FDD_t;
/// DCI Format Type 2B (10 MHz, FDD, 41 bits)
@@ -2318,7 +2301,6 @@ struct DCI2B_10MHz_FDD {
uint64_t padding0:1;
} __attribute__ ((__packed__));
#define sizeof_DCI2B_10MHz_FDD_t 41
typedef struct DCI2B_10MHz_FDD DCI2B_10MHz_FDD_t;
/// DCI Format Type 2B (20 MHz, FDD, 48 bits)
@@ -2349,7 +2331,6 @@ struct DCI2B_20MHz_FDD {
uint64_t rah:1;
} __attribute__ ((__packed__));
#define sizeof_DCI2B_20MHz_FDD_t 48
typedef struct DCI2B_20MHz_FDD DCI2B_20MHz_FDD_t;
// *******************************************************************
@@ -2386,7 +2367,6 @@ struct DCI2C_1_5MHz_TDD {
} __attribute__ ((__packed__));
typedef struct DCI2C_1_5MHz_TDD DCI2C_1_5MHz_TDD_t;
#define sizeof_DCI2C_1_5MHz_TDD_t 34
/// DCI Format Type 2C (5 MHz, TDD, 41 bits)
struct DCI2C_5MHz_TDD {
@@ -2421,7 +2401,6 @@ struct DCI2C_5MHz_TDD {
} __attribute__ ((__packed__));
typedef struct DCI2C_5MHz_TDD DCI2C_5MHz_TDD_t;
#define sizeof_DCI2C_5MHz_TDD_t 41
/// DCI Format Type 2C (10 MHz, TDD, 45 bits)
struct DCI2C_10MHz_TDD {
@@ -2456,7 +2435,6 @@ struct DCI2C_10MHz_TDD {
} __attribute__ ((__packed__));
typedef struct DCI2C_10MHz_TDD DCI2C_10MHz_TDD_t;
#define sizeof_DCI2C_10MHz_TDD_t 45
/// DCI Format Type 2C (20 MHz, TDD, 53 bits)
struct DCI2C_20MHz_TDD {
@@ -2491,7 +2469,6 @@ struct DCI2C_20MHz_TDD {
} __attribute__ ((__packed__));
typedef struct DCI2C_20MHz_TDD DCI2C_20MHz_TDD_t;
#define sizeof_DCI2C_20MHz_TDD_t 53
/// DCI Format Type 2C (1.5 MHz, FDD, 30 bits)
struct DCI2C_1_5MHz_FDD {
@@ -2520,7 +2497,6 @@ struct DCI2C_1_5MHz_FDD {
} __attribute__ ((__packed__));
typedef struct DCI2C_1_5MHz_FDD DCI2C_1_5MHz_FDD_t;
#define sizeof_DCI2C_1_5MHz_FDD_t 30
/// DCI Format Type 2C (5 MHz, FDD, 38 bits)
struct DCI2C_5MHz_FDD {
@@ -2550,7 +2526,6 @@ struct DCI2C_5MHz_FDD {
uint64_t rah:1;
} __attribute__ ((__packed__));
#define sizeof_DCI2C_5MHz_FDD_t 38
typedef struct DCI2C_5MHz_FDD DCI2C_5MHz_FDD_t;
/// DCI Format Type 2C (10 MHz, FDD, 42 bits)
@@ -2581,7 +2556,6 @@ struct DCI2C_10MHz_FDD {
uint64_t rah:1;
} __attribute__ ((__packed__));
#define sizeof_DCI2C_10MHz_FDD_t 43
typedef struct DCI2C_10MHz_FDD DCI2C_10MHz_FDD_t;
/// DCI Format Type 2C (20 MHz, FDD, 50 bits)
@@ -2612,7 +2586,6 @@ struct DCI2C_20MHz_FDD {
uint64_t rah:1;
} __attribute__ ((__packed__));
#define sizeof_DCI2C_20MHz_FDD_t 50
typedef struct DCI2C_20MHz_FDD DCI2C_20MHz_FDD_t;
// *******************************************************************
@@ -2651,7 +2624,6 @@ struct DCI2D_1_5MHz_TDD {
} __attribute__ ((__packed__));
typedef struct DCI2D_1_5MHz_TDD DCI2D_1_5MHz_TDD_t;
#define sizeof_DCI2D_1_5MHz_TDD_t 36
/// DCI Format Type 2D (5 MHz, TDD, 43 bits)
struct DCI2D_5MHz_TDD {
@@ -2688,7 +2660,6 @@ struct DCI2D_5MHz_TDD {
} __attribute__ ((__packed__));
typedef struct DCI2D_5MHz_TDD DCI2D_5MHz_TDD_t;
#define sizeof_DCI2D_5MHz_TDD_t 43
/// DCI Format Type 2D (10 MHz, TDD, 47 bits)
struct DCI2D_10MHz_TDD {
@@ -2725,7 +2696,6 @@ struct DCI2D_10MHz_TDD {
} __attribute__ ((__packed__));
typedef struct DCI2D_10MHz_TDD DCI2D_10MHz_TDD_t;
#define sizeof_DCI2D_10MHz_TDD_t 47
/// DCI Format Type 2D (20 MHz, TDD, 55 bits)
struct DCI2D_20MHz_TDD {
@@ -2762,7 +2732,6 @@ struct DCI2D_20MHz_TDD {
} __attribute__ ((__packed__));
typedef struct DCI2D_20MHz_TDD DCI2D_20MHz_TDD_t;
#define sizeof_DCI2D_20MHz_TDD_t 55
/// DCI Format Type 2D (1.5 MHz, FDD, 33 bits)
struct DCI2D_1_5MHz_FDD {
@@ -2795,7 +2764,6 @@ struct DCI2D_1_5MHz_FDD {
} __attribute__ ((__packed__));
typedef struct DCI2D_1_5MHz_FDD DCI2D_1_5MHz_FDD_t;
#define sizeof_DCI2D_1_5MHz_FDD_t 33
/// DCI Format Type 2D (5 MHz, FDD, 41 bits)
struct DCI2D_5MHz_FDD {
@@ -2829,7 +2797,6 @@ struct DCI2D_5MHz_FDD {
uint64_t padding0:1;
} __attribute__ ((__packed__));
#define sizeof_DCI2D_5MHz_FDD_t 41
typedef struct DCI2D_5MHz_FDD DCI2D_5MHz_FDD_t;
/// DCI Format Type 2D (10 MHz, FDD, 45 bits)
@@ -2864,7 +2831,6 @@ struct DCI2D_10MHz_FDD {
uint64_t padding0:1;
} __attribute__ ((__packed__));
#define sizeof_DCI2D_10MHz_FDD_t 45
typedef struct DCI2D_10MHz_FDD DCI2D_10MHz_FDD_t;
/// DCI Format Type 2D (20 MHz, FDD, 52 bits)
@@ -2895,7 +2861,6 @@ struct DCI2D_20MHz_FDD {
uint64_t rah:1;
} __attribute__ ((__packed__));
#define sizeof_DCI2D_20MHz_FDD_t 52
typedef struct DCI2D_20MHz_FDD DCI2D_20MHz_FDD_t;
@@ -2904,14 +2869,12 @@ typedef struct __attribute__ ((__packed__))
uint32_t TPC:28;
}
DCI3_5MHz_TDD_0_t;
#define sizeof_DCI3_5MHz_TDD_0_t 27
typedef struct __attribute__ ((__packed__))
{
uint32_t TPC:28;
}
DCI3_5MHz_TDD_1_6_t;
#define sizeof_DCI3_5MHz_TDD_1_6_t 27
typedef struct __attribute__ ((__packed__))
@@ -2919,7 +2882,6 @@ typedef struct __attribute__ ((__packed__))
uint32_t TPC:26;
}
DCI3_5MHz_FDD_t;
#define sizeof_DCI3_5MHz_FDD_t 25
/// DCI Format Type 0 (1.5 MHz,9 bits)
struct DCI0A_1_5MHz {
@@ -2932,7 +2894,6 @@ struct DCI0A_1_5MHz {
/// Hopping flag
uint32_t hopping:1;
} __attribute__ ((__packed__));
#define sizeof_DCI0A_1_5MHz 9
/// DCI Format Type 0 (5 MHz,13 bits)
struct DCI0A_5MHz {
@@ -2945,7 +2906,6 @@ struct DCI0A_5MHz {
/// Hopping flag
uint32_t hopping:1;
} __attribute__ ((__packed__));
#define sizeof_DCI0A_5MHz 13
/// DCI Format Type 0 (10 MHz,15 bits)
struct DCI0A_10_MHz {
@@ -2958,7 +2918,6 @@ struct DCI0A_10_MHz {
/// Hopping flag
uint32_t hopping:1;
} __attribute__ ((__packed__));
#define sizeof_DCI0A_10MHz 15
/// DCI Format Type 0 (20 MHz,17 bits)
struct DCI0A_20_MHz {
@@ -2971,7 +2930,6 @@ struct DCI0A_20_MHz {
/// Hopping flag
uint32_t hopping:1;
} __attribute__ ((__packed__));
#define sizeof_DCI0A_20MHz 17
#define MAX_DCI_SIZE_BITS 45
-6
View File
@@ -203,7 +203,6 @@ typedef union DCI_CONTENT {
} __attribute__ ((__packed__));
typedef struct DCIN0 DCIN0_t;
#define sizeof_DCIN0_t 23
struct DCIN1_RAR{
// DCI subframe repetition Number, 2 bits
@@ -227,7 +226,6 @@ struct DCIN1_RAR{
} __attribute__ ((__packed__));
typedef struct DCIN1_RAR DCIN1_RAR_t;
#define sizeof_DCIN1_RAR_t 23
struct DCIN1{
// DCI subframe repetition Number, 2 bits
@@ -251,7 +249,6 @@ struct DCIN1{
} __attribute__ ((__packed__));
typedef struct DCIN1 DCIN1_t;
#define sizeof_DCIN1_t 23
// DCI Format Type N2 for direct indication, 15 bits
struct DCIN2_Ind{
@@ -264,7 +261,6 @@ struct DCIN2_Ind{
} __attribute__ ((__packed__));;
typedef struct DCIN2_Ind DCIN2_Ind_t;
#define sizeof_DCIN2_Ind_t 15
// DCI Format Type N2 for Paging, 15 bits
struct DCIN2_Pag{
@@ -282,8 +278,6 @@ struct DCIN2_Pag{
typedef struct DCIN2_Pag DCIN2_Pag_t;
#define sizeof_DCIN2_Pag_t 15
#define MAX_DCI_SIZE_BITS_NB_IoT 23
#endif
-4
View File
@@ -29,14 +29,10 @@
//#include "dci_nb_iot.h"
//#define MOD_TABLE_QPSK_OFFSET 1
//#define MOD_TABLE_16QAM_OFFSET 5
//#define MOD_TABLE_64QAM_OFFSET 21
//#define MOD_TABLE_PSS_OFFSET 85
//
//// structures below implement 36-211 and 36-212
//
//#define NSOFT 1827072
#define LTE_NULL_NB_IoT 2
//
//// maximum of 3 segments before each coding block if data length exceeds 6144 bits.
//
-3
View File
@@ -267,7 +267,6 @@ struct DCI6_0B_5MHz {
} __attribute__ ((__packed__));
typedef struct DCI6_0B_5MHz DCI6_0B_5MHz_t;
#define sizeof_DCI6_0B_5MHz_t 17
/// basic DCI Format Type 6-1B (5 MHz)
struct DCI6_1B_5MHz {
@@ -315,7 +314,6 @@ struct DCI6_0B_10MHz {
} __attribute__ ((__packed__));
typedef struct DCI6_0B_10MHz DCI6_0B_10MHz_t;
#define sizeof_DCI6_0B_10MHz_t 18
/// basic DCI Format Type 6-1B (10 MHz)
struct DCI6_1B_10MHz {
@@ -363,7 +361,6 @@ struct DCI6_0B_20MHz {
} __attribute__ ((__packed__));
typedef struct DCI6_0B_20MHz DCI6_0B_20MHz_t;
#define sizeof_DCI6_0B_20MHz_t 18
/// basic DCI Format Type 6-1B (10 MHz)
struct DCI6_1B_20MHz {
@@ -36,14 +36,10 @@
#include <stdint.h>
/* PUCCH format3 >> */
#define D_I 0
#define D_Q 1
#define D_IQDATA 2
#define D_NSLT1SF 2
#define D_NSYM1SLT 7
#define D_NSYM1SF 2*7
#define D_NSC1RB 12
#define D_NRB1PUCCH 2
#define D_NPUCCH_SF5 5
#define D_NPUCCH_SF4 4
@@ -40,9 +40,6 @@
//#endif
#define MOD_TABLE_QPSK_OFFSET 1
#define MOD_TABLE_16QAM_OFFSET 5
#define MOD_TABLE_64QAM_OFFSET 21
#define MOD_TABLE_PSS_OFFSET 85
// structures below implement 36-211 and 36-212
@@ -72,7 +69,6 @@
#define PMI_2A_1j 2
#define PMI_2A_1mj 3
//2 layers
#define PMI_2A_R1_10 0
#define PMI_2A_R1_11 1
#define PMI_2A_R1_1j 2
-28
View File
@@ -45,7 +45,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
wideband_cqi_rank1_2A_1_5MHz_NB_IoT ;
#define sizeof_wideband_cqi_rank1_2A_1_5MHz_NB_IoT 16
typedef struct __attribute__((packed))
{
@@ -55,7 +54,6 @@ typedef struct __attribute__((packed))
uint16_t cqi1:4;
}
wideband_cqi_rank2_2A_1_5MHz_NB_IoT ;
#define sizeof_wideband_cqi_rank2_2A_1_5MHz_NB_IoT 14
typedef struct __attribute__((packed))
{
@@ -64,7 +62,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_nopmi_1_5MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_nopmi_1_5MHz_NB_IoT 16
typedef struct __attribute__((packed))
{
@@ -74,7 +71,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_rank1_2A_1_5MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_rank1_2A_1_5MHz_NB_IoT 18
typedef struct __attribute__((packed))
{
@@ -86,7 +82,6 @@ typedef struct __attribute__((packed))
uint64_t cqi1:4;
}
HLC_subband_cqi_rank2_2A_1_5MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_rank2_2A_1_5MHz_NB_IoT 33
typedef struct __attribute__((packed))
{
@@ -95,7 +90,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_modes123_1_5MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_modes123_1_5MHz_NB_IoT 16
typedef struct __attribute__((packed))
{
@@ -104,7 +98,6 @@ typedef struct __attribute__((packed))
uint32_t mcs:5;
}
HLC_subband_cqi_mcs_CBA_1_5MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz_NB_IoT 21
// **********************************************5 MHz***************************************************************************
@@ -115,7 +108,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
wideband_cqi_rank1_2A_5MHz_NB_IoT ;
#define sizeof_wideband_cqi_rank1_2A_5MHz_NB_IoT 18
typedef struct __attribute__((packed))
{
@@ -125,7 +117,6 @@ typedef struct __attribute__((packed))
uint16_t cqi1:4;
}
wideband_cqi_rank2_2A_5MHz_NB_IoT ;
#define sizeof_wideband_cqi_rank2_2A_5MHz_NB_IoT 15
typedef struct __attribute__((packed))
{
@@ -134,7 +125,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_nopmi_5MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_nopmi_5MHz_NB_IoT 18
typedef struct __attribute__((packed))
{
@@ -144,7 +134,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_rank1_2A_5MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_rank1_2A_5MHz_NB_IoT 20
typedef struct __attribute__((packed))
{
@@ -156,7 +145,6 @@ typedef struct __attribute__((packed))
uint64_t cqi1:4;
}
HLC_subband_cqi_rank2_2A_5MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_rank2_2A_5MHz_NB_IoT 37
typedef struct __attribute__((packed))
{
@@ -165,7 +153,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_modes123_5MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_modes123_5MHz_NB_IoT 18
typedef struct __attribute__((packed))
{
@@ -174,7 +161,6 @@ typedef struct __attribute__((packed))
uint32_t mcs:5;
}
HLC_subband_cqi_mcs_CBA_5MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_mcs_CBA_5MHz_NB_IoT 21
// **********************************************10 MHz***************************************************************************
typedef struct __attribute__((packed))
@@ -184,7 +170,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
wideband_cqi_rank1_2A_10MHz_NB_IoT ;
#define sizeof_wideband_cqi_rank1_2A_10MHz_NB_IoT 22
typedef struct __attribute__((packed))
{
@@ -194,7 +179,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
wideband_cqi_rank2_2A_10MHz_NB_IoT ;
#define sizeof_wideband_cqi_rank2_2A_10MHz_NB_IoT 17
typedef struct __attribute__((packed))
{
@@ -203,7 +187,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_nopmi_10MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_nopmi_10MHz_NB_IoT 22
typedef struct __attribute__((packed))
{
@@ -213,7 +196,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_rank1_2A_10MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_rank1_2A_10MHz_NB_IoT 24
typedef struct __attribute__((packed))
{
@@ -225,7 +207,6 @@ typedef struct __attribute__((packed))
uint64_t cqi1:4;
}
HLC_subband_cqi_rank2_2A_10MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_rank2_2A_10MHz_NB_IoT 45
typedef struct __attribute__((packed))
{
@@ -234,7 +215,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_modes123_10MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_modes123_10MHz_NB_IoT 22
typedef struct __attribute__((packed))
{
@@ -243,7 +223,6 @@ typedef struct __attribute__((packed))
uint32_t mcs:5;
}
HLC_subband_cqi_mcs_CBA_10MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_mcs_CBA_10MHz_NB_IoT 21
// **********************************************20 MHz***************************************************************************
typedef struct __attribute__((packed))
@@ -253,7 +232,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
wideband_cqi_rank1_2A_20MHz_NB_IoT ;
#define sizeof_wideband_cqi_rank1_2A_20MHz_NB_IoT 20
typedef struct __attribute__((packed))
{
@@ -263,7 +241,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
wideband_cqi_rank2_2A_20MHz_NB_IoT ;
#define sizeof_wideband_cqi_rank2_2A_20MHz_NB_IoT 21
typedef struct __attribute__((packed))
{
@@ -272,7 +249,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_nopmi_20MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_nopmi_20MHz_NB_IoT 30
typedef struct __attribute__((packed))
{
@@ -282,7 +258,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_rank1_2A_20MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_rank1_2A_20MHz_NB_IoT 32
typedef struct __attribute__((packed))
{
@@ -294,7 +269,6 @@ typedef struct __attribute__((packed))
uint64_t cqi1:4;
}
HLC_subband_cqi_rank2_2A_20MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_rank2_2A_20MHz_NB_IoT 61
typedef struct __attribute__((packed))
{
@@ -303,7 +277,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_modes123_20MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_modes123_20MHz_NB_IoT 30
typedef struct __attribute__((packed))
{
@@ -313,7 +286,6 @@ typedef struct __attribute__((packed))
}
HLC_subband_cqi_mcs_CBA_20MHz_NB_IoT;
#define sizeof_HLC_subband_cqi_mcs_CBA_20MHz_NB_IoT 21
#define MAX_CQI_PAYLOAD_NB_IoT (sizeof(HLC_subband_cqi_rank2_2A_20MHz_NB_IoT)*8*20)
#define MAX_CQI_BITS_NB_IoT (sizeof(HLC_subband_cqi_rank2_2A_20MHz_NB_IoT)*8)
-12
View File
@@ -74,7 +74,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_rank1_2A_1_5MHz;
#define sizeof_HLC_subband_cqi_rank1_2A_1_5MHz 18
typedef struct __attribute__((packed))
{
@@ -86,7 +85,6 @@ typedef struct __attribute__((packed))
uint64_t cqi1:4;
}
HLC_subband_cqi_rank2_2A_1_5MHz;
#define sizeof_HLC_subband_cqi_rank2_2A_1_5MHz 33
typedef struct __attribute__((packed))
{
@@ -95,7 +93,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_modes123_1_5MHz;
#define sizeof_HLC_subband_cqi_modes123_1_5MHz 16
typedef struct __attribute__((packed))
{
@@ -144,7 +141,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_rank1_2A_5MHz;
#define sizeof_HLC_subband_cqi_rank1_2A_5MHz 20
typedef struct __attribute__((packed))
{
@@ -156,7 +152,6 @@ typedef struct __attribute__((packed))
uint64_t cqi1:4;
}
HLC_subband_cqi_rank2_2A_5MHz;
#define sizeof_HLC_subband_cqi_rank2_2A_5MHz 37
typedef struct __attribute__((packed))
{
@@ -165,7 +160,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_modes123_5MHz;
#define sizeof_HLC_subband_cqi_modes123_5MHz 18
typedef struct __attribute__((packed))
{
@@ -213,7 +207,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_rank1_2A_10MHz;
#define sizeof_HLC_subband_cqi_rank1_2A_10MHz 24
typedef struct __attribute__((packed))
{
@@ -225,7 +218,6 @@ typedef struct __attribute__((packed))
uint64_t cqi1:4;
}
HLC_subband_cqi_rank2_2A_10MHz;
#define sizeof_HLC_subband_cqi_rank2_2A_10MHz 45
typedef struct __attribute__((packed))
{
@@ -234,7 +226,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_modes123_10MHz;
#define sizeof_HLC_subband_cqi_modes123_10MHz 22
typedef struct __attribute__((packed))
{
@@ -282,7 +273,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_rank1_2A_20MHz;
#define sizeof_HLC_subband_cqi_rank1_2A_20MHz 32
typedef struct __attribute__((packed))
{
@@ -294,7 +284,6 @@ typedef struct __attribute__((packed))
uint64_t cqi1:4;
}
HLC_subband_cqi_rank2_2A_20MHz;
#define sizeof_HLC_subband_cqi_rank2_2A_20MHz 61
typedef struct __attribute__((packed))
{
@@ -303,7 +292,6 @@ typedef struct __attribute__((packed))
uint32_t cqi1:4;
}
HLC_subband_cqi_modes123_20MHz;
#define sizeof_HLC_subband_cqi_modes123_20MHz 30
typedef struct __attribute__((packed))
{
-1
View File
@@ -293,7 +293,6 @@ uint16_t get_dmrs_freq_idx_ul(uint16_t n, uint8_t k_prime, uint8_t delta, uint8_
*
*********************************************************************/
#define CHECK_DMRS_PBCH_SEQUENCE
/* return the position of next dmrs symbol in a slot */
int8_t get_next_dmrs_symbol_in_slot(uint16_t ul_dmrs_symb_pos, uint8_t counter, uint8_t end_symbol)
-4
View File
@@ -23,10 +23,6 @@
#define __PHY_NR_REFSIG_NR_MOD_TABLE__H__
#define NR_MOD_TABLE_SIZE_SHORT 686
#define NR_MOD_TABLE_BPSK_OFFSET 1
#define NR_MOD_TABLE_QAM16_OFFSET 7
#define NR_MOD_TABLE_QAM64_OFFSET 23
#define NR_MOD_TABLE_QAM256_OFFSET 87
extern c16_t nr_qpsk_mod_table[4];
extern simde__m128i nr_qpsk_byte_mod_table[256];
-2
View File
@@ -36,8 +36,6 @@
#include "PHY/defs_nr_common.h"
#include "nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h"
#define NR_PDSCH_DMRS_ANTENNA_PORT0 1000
#define NR_PDSCH_DMRS_NB_ANTENNA_PORTS 12
void get_antenna_ports(uint8_t *ap, uint8_t n_symbs, uint8_t config);
void get_Wt(int *Wt, const int ap, const nfapi_nr_dmrs_type_e config);
@@ -50,8 +50,6 @@
#define PRINT_CRC_CHECK(a)
#endif
// extern double cpuf;
void free_gNB_ulsch(NR_gNB_ULSCH_t *ulsch, uint16_t N_RB_UL)
{
uint16_t a_segments = MAX_NUM_NR_ULSCH_SEGMENTS_PER_LAYER * NR_MAX_NB_LAYERS; // number of segments to be allocated
@@ -15,7 +15,6 @@
#include <sys/time.h>
#include "PHY/log_tools.h"
#define INVALID_VALUE 255
#if T_TRACER
static void copy_c16_data_to_slot_memory(c16_t *src, c16_t *dst_slot, int nb_re_pusch, int symbol)
@@ -122,7 +122,7 @@ void nr_ue_ssb_rsrp_measurements(PHY_VARS_NR_UE *ue,
typedef struct {
UE_nr_rxtx_proc_t proc;
PHY_VARS_NR_UE *ue;
c16_t *rxdata[NB_RX_ANTENNAS_MAX];
c16_t *rxdata[NB_ANTENNAS_RX];
uint32_t rxdata_size;
c16_t rxdata_ant[];
} nr_meas_task_args_t;
-2
View File
@@ -65,8 +65,6 @@
#endif
#define NR_NBR_CORESET_ACT_BWP 3 // The number of CoreSets per BWP is limited to 3 (including initial CORESET: ControlResourceId 0)
#define NR_NBR_SEARCHSPACE_ACT_BWP \
10 // The number of SearSpaces per BWP is limited to 10 (including initial SEARCHSPACE: SearchSpaceId 0)
#define RE_PER_RB 12
// after removing the 3 DMRS RE, the RB contains 9 RE with PDCCH
-36
View File
@@ -45,7 +45,6 @@ int main(int argc, char **argv) {
CONFIG_CLEARRTFLAG(CONFIG_NOEXITONHELP);
lock_memory_to_ram();
int N_RB=50;
int sampling_rate=30.72e6;
int DFT=2048;
int TxAdvanceInDFTSize=12;
@@ -57,20 +56,8 @@ int main(int argc, char **argv) {
char * usrp_addrs="type=b200";
openair0_config_t openair0_cfg= {
//! Module ID for this configuration
.Mod_id=0,
//! duplexing mode
.duplex_mode=0,
//! number of downlink resource blocks
.num_rb_dl=N_RB,
//! number of samples per frame
.samples_per_frame=0,
//! the sample rate for both transmit and receive.
.sample_rate=sampling_rate,
//device is doing mmapped DMA transfers
.mmapped_dma=0,
//! offset in samples between TX and RX paths
.tx_sample_advance=0,
//! samples per packet on the fronthaul interface
.samples_per_packet=1024,
//! number of RX channels (=RX antennas)
@@ -83,17 +70,9 @@ int main(int argc, char **argv) {
//! \brief Center frequency in Hz for TX.
//! index: [0..rx_num_channels[ !!! see lte-ue.c:427 FIXME iterates over rx_num_channels
.tx_freq={freq,freq,freq,freq},
//! \brief memory
//! \brief Pointer to Calibration table for RX gains
.rx_gain_calib_table=NULL,
//! mode for rxgain (ExpressMIMO2)
.rxg_mode={0},
//! \brief Gain for RX in dB.
//! index: [0..rx_num_channels]
.rx_gain={rxGain,rxGain,rxGain,rxGain},
//! \brief Gain offset (for calibration) in dB
//! index: [0..rx_num_channels]
.rx_gain_offset={0},
//! gain for TX in dB
.tx_gain={txGain,txGain,txGain,txGain},
//! RX bandwidth in Hz
@@ -106,24 +85,9 @@ int main(int argc, char **argv) {
.time_source=internal, //internal gpsdo external
//! Manual SDR IP address
.sdr_addrs=usrp_addrs,
//! Auto calibration flag
.autocal={0},
//! Configuration file for LMS7002M
.configFilename="",
//! record player configuration, definition in record_player.h
.recplay_mode=0,
.recplay_conf=NULL,
//! number of samples per tti
.samples_per_tti=0,
};
//-----------------------
openair0_device_t rfdevice= {
/*!tx write thread*/
//.write_thread={0},
/*!brief Module ID of this device */
.Mod_id=0,
/*!brief Component Carrier ID of this device */
.CC_id=0,
/*!brief Type of this device */
.type=NONE_DEV,
/*!brief Transport protocol type that the device supports (in case I/Q samples need to be transported) */
-1
View File
@@ -35,7 +35,6 @@
#include <malloc.h>
#include "assertions.h"
#include "common/utils/LOG/log.h"
#define OAIDFTS_LOADER
#include "tools_defs.h"
#include "common/config/config_userapi.h"
#include "common/utils/load_module_shlib.h"
-13
View File
@@ -45,11 +45,6 @@
#include "defs_eNB.h"
//#include <complex.h>
#include "assertions.h"
#if ENABLE_RAL
#include "collection/hashtable/hashtable.h"
#include "COMMON/ral_messages_types.h"
#include "UTIL/queue.h"
#endif
#include "common/utils/LOG/log.h"
#define msg(aRGS...) LOG_D(PHY, ##aRGS)
//use msg in the real-time thread context
@@ -59,8 +54,6 @@
#define malloc16(x) memalign(32,x)
#endif
#define free16(y,x) free(y)
#define bigmalloc malloc
#define bigmalloc16 malloc16
#define openair_free(y,x) free((y))
#define PAGE_SIZE 4096
@@ -86,7 +79,6 @@ static inline void* malloc16_clear( size_t size )
*/
// #define PAGE_MASK 0xfffff000
// #define virt_to_phys(x) (x)
// #define openair_sched_exit() exit(-1)
@@ -963,11 +955,6 @@ typedef struct {
time_stats_t dlsch_llr_stripping_unit_SIC_stats;
time_stats_t dlsch_unscrambling_SIC_stats;
#if ENABLE_RAL
hash_table_t *ral_thresholds_timed;
SLIST_HEAD(ral_thresholds_gen_poll_s, ral_threshold_phy_t) ral_thresholds_gen_polled[RAL_LINK_PARAM_GEN_MAX];
SLIST_HEAD(ral_thresholds_lte_poll_s, ral_threshold_phy_t) ral_thresholds_lte_polled[RAL_LINK_PARAM_LTE_MAX];
#endif
*/
} PHY_VARS_UE_NB_IoT;
-6
View File
@@ -76,11 +76,6 @@
#define stop_UE_TIMING(a)
#endif
#if ENABLE_RAL
#include "collection/hashtable/hashtable.h"
#include "COMMON/ral_messages_types.h"
#include "UTIL/queue.h"
#endif
#include "common/utils/LOG/log.h"
#define msg(aRGS...) LOG_D(PHY, ##aRGS)
@@ -551,7 +546,6 @@ typedef struct {
uint8_t CC_id;
/// \brief Mapping of CC_id antennas to cards
openair0_rf_map_t rf_map;
//uint8_t local_flag;
/// \brief Indicator of current run mode of UE (normal_txrx, rx_calib_ue, no_L2_connect, debug_prach)
runmode_t mode;
/// \brief Indicator that UE is configured for FeMBMS functionality (This flag should be avoided) ... just kept for PBCH initical scan (TODO)
-4
View File
@@ -75,7 +75,6 @@
#define RX_NB_TH_MAX 2
#define RX_NB_TH 2
#define RX_NB_TH_DL 14
#define LTE_SLOTS_PER_SUBFRAME 2
@@ -96,7 +95,6 @@
#define MAX_MBSFN_AREA 8
#define NB_RX_ANTENNAS_MAX 64
#define TC_NSEC_x32768 16667
@@ -936,13 +934,11 @@ typedef enum {SF_DL, SF_UL, SF_S} lte_subframe_t;
#define MAX_FRAME_NUMBER 0x400
#define NUMBER_OF_RN_MAX 3
typedef enum {no_relay=1,unicast_relay_type1,unicast_relay_type2, multicast_relay} relaying_type_t;
#define MCS_COUNT 29
#define MCS_TABLE_LENGTH_MAX 64
#define NUM_DCI_MAX 32
-11
View File
@@ -56,11 +56,6 @@
#include "actor.h"
//#include "openair1/SCHED_NR_UE/defs.h"
#if ENABLE_RAL
#include "common/utils/hashtable/hashtable.h"
#include "COMMON/ral_messages_types.h"
#include "UTIL/queue.h"
#endif
#define msg(aRGS...) LOG_D(PHY, ##aRGS)
// use msg in the real-time thread context
#define msg_nrt printf
@@ -69,12 +64,9 @@
#define malloc16(x) memalign(32,x)
#endif
#define free16(y,x) free(y)
#define bigmalloc malloc
#define bigmalloc16 malloc16
#define openair_free(y,x) free((y))
#define PAGE_SIZE 4096
#define PAGE_MASK 0xfffff000
#define virt_to_phys(x) (x)
#define openair_sched_exit() exit(-1)
@@ -266,7 +258,6 @@ typedef struct {
#define NR_PDCCH_DEFS_NR_UE
#define NR_NBR_CORESET_ACT_BWP 3 // The number of CoreSets per BWP is limited to 3 (including initial CORESET: ControlResourceId 0)
#define NR_NBR_SEARCHSPACE_ACT_BWP 10 // The number of SearchSpaces per BWP is limited to 10 (including initial SEARCHSPACE: SearchSpaceId 0)
#ifdef NR_PDCCH_DEFS_NR_UE
#define MAX_NR_DCI_DECODED_SLOT 10 // This value is not specified
@@ -288,8 +279,6 @@ typedef struct {
fapi_nr_dl_config_dci_dl_pdu_rel15_t pdcch_config[FAPI_NR_MAX_SS];
} NR_UE_PDCCH_CONFIG;
#define NR_PSBCH_MAX_NB_CARRIERS 132
#define NR_PSBCH_MAX_NB_MOD_SYMBOLS 99
#define NR_PSBCH_DMRS_LENGTH 297 // in mod symbols
#define NR_PSBCH_DMRS_LENGTH_DWORD 20 // ceil(2(QPSK)*NR_PBCH_DMRS_LENGTH/32)
-9
View File
@@ -46,23 +46,16 @@
#define NR_SYMBOLS_PER_SLOT NR_NUMBER_OF_SYMBOLS_PER_SLOT
#define ONE_OVER_SQRT2_Q15 23170
#define ONE_OVER_TWO_Q15 16384
#define NR_MOD_TABLE_SIZE_SHORT 686
#define NR_MOD_TABLE_BPSK_OFFSET 1
#define NR_MOD_TABLE_QAM16_OFFSET 7
#define NR_MOD_TABLE_QAM64_OFFSET 23
#define NR_MOD_TABLE_QAM256_OFFSET 87
#define NR_PSS_LENGTH 127
#define NR_SSS_LENGTH 127
#define NR_MAX_PRS_LENGTH 3264 //272*6(max allocation per RB)*2(QPSK)
#define NR_MAX_PRS_INIT_LENGTH_DWORD 102 // ceil(NR_MAX_CSI_RS_LENGTH/32)
#define NR_MAX_NUM_PRS_SYMB 12
#define NR_MAX_PRS_COMB_SIZE 12
#define NR_MAX_PRS_RESOURCES_PER_SET 64
#define NR_MAX_PRS_MUTING_PATTERN_LENGTH 32
#define NR_PBCH_DMRS_LENGTH 144 // in mod symbols
#define NR_PBCH_DMRS_LENGTH_DWORD 10 // ceil(2(QPSK)*NR_PBCH_DMRS_LENGTH/32)
@@ -70,7 +63,6 @@
/*used for the resource mapping*/
#define NR_MAX_PDCCH_DMRS_LENGTH 576 // 16(L)*2(QPSK)*3(3 DMRS symbs per REG)*6(REG per CCE)
#define NR_MAX_PDCCH_SIZE 8192 // It seems it is the max polar coded block size
#define NR_MAX_DCI_PAYLOAD_SIZE 64
#define NR_MAX_DCI_SIZE 1728 //16(L)*2(QPSK)*9(12 RE per REG - 3(DMRS))*6(REG per CCE)
#define NR_MAX_DCI_SIZE_DWORD 54 // ceil(NR_MAX_DCI_SIZE/32)
@@ -87,7 +79,6 @@
#define MAX_NUM_NR_SRS_SYMBOLS 4
#define MAX_NUM_NR_SRS_AP 4
#define NR_NB_NSCID 2
#define MAX_DELAY_COMP 20
-3
View File
@@ -46,7 +46,6 @@
// 11 RBs for PSBCH in one symbol * 12 REs
#define SL_NR_NUM_PSBCH_RE_IN_ONE_SYMBOL 132
// 3 DMRS REs per RB * 11 RBS in one symbol
#define SL_NR_NUM_PSBCH_DMRS_RE_IN_ONE_SYMBOL 33
// 9 PSBCH DATA REs * 11 RBS in one symbol
#define SL_NR_NUM_PSBCH_DATA_RE_IN_ONE_SYMBOL 99
#define SL_NR_NUM_PSBCH_RBS_IN_ONE_SYMBOL 11
@@ -54,7 +53,6 @@
// 11 * (12-3 DMRS REs) * 9 symbols for PSBCH
#define SL_NR_NUM_PSBCH_MODULATED_SYMBOLS 891
#define SL_NR_NUM_PSBCH_DATA_RE_IN_ONE_RB 9
#define SL_NR_NUM_PSBCH_DMRS_RE_IN_ONE_RB 3
// 11 * (12-3 DMRS REs) * 9 symbols for PSBCH
#define SL_NR_NUM_PSBCH_DATA_RE_IN_ALL_SYMBOLS 891
@@ -63,7 +61,6 @@
#define SL_NR_NUM_PSS_SYMBOLS 2
#define SL_NR_NUM_SSS_SYMBOLS 2
#define SL_NR_PSS_START_SYMBOL 1
#define SL_NR_SSS_START_SYMBOL 3
#define SL_NR_NUM_PSS_OR_SSS_SYMBOLS 2
#define SL_NR_PSS_SEQUENCE_LENGTH 127
#define SL_NR_SSS_SEQUENCE_LENGTH 127
-4
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@@ -489,10 +489,6 @@ typedef struct {
uint16_t dl_GapDurationCoeff;
} DL_GapConfig_NB_IoT;
#define NBIOT_INBAND_LTEPCI 0
#define NBIOT_INBAND_IOTPCI 1
#define NBIOT_INGUARD 2
#define NBIOT_STANDALONE 3
typedef struct {
-3
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@@ -325,9 +325,6 @@ typedef struct {
*
************************************************************************/
#define MAX_NR_RATE_MATCH_PATTERNS 4
#define MAX_NR_ZP_CSI_RS_RESOURCES 32
#define MAX_NR_OF_DL_ALLOCATIONS 16
#define MAX_NR_OF_UL_ALLOCATIONS (16)
typedef enum {
-39
View File
@@ -128,10 +128,6 @@
#define EXTENSION_TYPE (PHY_config->PHY_framing.Extension_type)
#define NUMBER_OF_OFDM_CARRIERS_BYTES NUMBER_OF_OFDM_CARRIERS*4
//#define NUMBER_OF_USEFUL_CARRIERS_BYTES NUMBER_OF_USEFUL_CARRIERS*4
#define HALF_NUMBER_OF_USER_CARRIERS_BYTES NUMBER_OF_USEFUL_CARRIERS/2
#define CYCLIC_PREFIX_LENGTH (frame_parms->nb_prefix_samples)
#define CYCLIC_PREFIX_LENGTH_SAMPLES (CYCLIC_PREFIX_LENGTH*2)
#define CYCLIC_PREFIX_LENGTH_BYTES (CYCLIC_PREFIX_LENGTH*4)
@@ -191,8 +187,6 @@
#define MIN_RF_GAIN 80
#define PHY_SYNCH_OFFSET ((OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES)-1) // OFFSET of BEACON SYNCH
#define PHY_SYNCH_MIN_POWER 1000
#define PHY_SYNCH_THRESHOLD 100
@@ -224,30 +218,6 @@
///Third Amplitude for QAM256 (\f$ 2^{15} \times 2/\sqrt{170}\f$)
#define QAM256_n3 5026
/// First Amplitude for QAM16 for TM5 (\f$ 2^{15} \times 2/sqrt(20)\f$)
#define QAM16_TM5_n1 14654
/// Second Amplitude for QAM16 for TM5 Receiver (\f$ 2^{15} \times 1/\sqrt{20}\f$)
#define QAM16_TM5_n2 7327
///First Amplitude for QAM64 (\f$ 2^{15} \times 4/\sqrt{84}\f$)
#define QAM64_TM5_n1 14301
///Second Amplitude for QAM64 (\f$ 2^{15} \times 2/\sqrt{84}\f$)
#define QAM64_TM5_n2 7150
///Third Amplitude for QAM64 for TM5 Receiver (\f$ 2^{15} \times 1/\sqrt{84}\f$)
#define QAM64_TM5_n3 3575
#ifdef BIT8_RXMUX
#define PERROR_SHIFT 0
#else
#define PERROR_SHIFT 10
#endif
#define BIT8_TX_SHIFT 2
#define BIT8_TX_SHIFT_DB 12
//#define CHBCH_RSSI_MIN -75
#ifdef BIT8_TX
#define AMP_SHIFT 7
#else
@@ -259,14 +229,6 @@
#define AMP_OVER_SQRT2 ((AMP*ONE_OVER_SQRT2_Q15)>>15)
#define AMP_OVER_2 (AMP>>1)
/// Threshold for PUCCH Format 1 detection
#define PUCCH1_THRES 0
/// Threshold for PUCCH Format 1a/1b detection
#define PUCCH1a_THRES 4
//#if defined(UPGRADE_RAT_NR)
#if 1
#define NB_NUMEROLOGIES_NR (5)
#define NR_MAX_SLOTS_PER_FRAME (160) /* number of slots per frame */
@@ -277,7 +239,6 @@
#define NR_MAX_ULSCH_HARQ_PROCESSES (NR_MAX_HARQ_PROCESSES) /* cf 38.214 6.1 UE procedure for receiving the physical uplink shared channel */
#define NR_MAX_DLSCH_HARQ_PROCESSES (NR_MAX_HARQ_PROCESSES) /* cf 38.214 5.1 UE procedure for receiving the physical downlink shared channel */
#endif
/// Data structure for transmission.
typedef struct {
-1
View File
@@ -34,7 +34,6 @@
#define __PHY_IMPLEMENTATION_DEFS_NB_IOT_H__
#include "common/openairinterface5g_limits.h"
#define ONE_OVER_SQRT2_Q15_NB_IoT 23170
#define NUMBER_OF_SUBBANDS_MAX_NB_IoT 13
typedef enum {no_relay_NB_IoT=1,unicast_relay_type1_NB_IoT,unicast_relay_type2_NB_IoT, multicast_relay_NB_IoT} relaying_type_t_NB_IoT;
-2
View File
@@ -176,7 +176,5 @@ static const int8_t delta_PUSCH_abs[4] = {-4, -1, 1, 4};
static const int8_t delta_PUSCH_acc[4] = {-1, 0, 1, 3};
extern uint8_t max_turbo_iterations;
extern double cpuf;
#endif /*__PHY_EXTERN_H__ */
-8
View File
@@ -38,10 +38,6 @@ enum THREAD_INDEX { OPENAIR_THREAD_INDEX = 0,
openair_SCHED_NB_THREADS
}; // do not modify this line
#define OPENAIR_THREAD_PRIORITY 255
#define OPENAIR_THREAD_STACK_SIZE PTHREAD_STACK_MIN //4096 //RTL_PTHREAD_STACK_MIN*6
//#define DLC_THREAD_STACK_SIZE 4096 //DLC stack size
//#define UE_SLOT_PARALLELISATION
@@ -77,10 +73,6 @@ enum openair_HARQ_TYPE {
openair_harq_RA
};
#define DAQ_AGC_ON 1
#define DAQ_AGC_OFF 0
/** @addtogroup _PHY_PROCEDURES_
* @{
*/
-7
View File
@@ -38,10 +38,6 @@
openair_SCHED_NB_THREADS
};*/ // do not modify this line
#define OPENAIR_THREAD_PRIORITY 255
#define OPENAIR_THREAD_STACK_SIZE PTHREAD_STACK_MIN //4096 //RTL_PTHREAD_STACK_MIN*6
//#define DLC_THREAD_STACK_SIZE 4096 //DLC stack size
//#define UE_SLOT_PARALLELISATION
@@ -78,9 +74,6 @@
openair_harq_RA
};*/
#define DAQ_AGC_ON 1
#define DAQ_AGC_OFF 0
/** @addtogroup _PHY_PROCEDURES_
* @{
*/
@@ -70,8 +70,6 @@
static const char mode_string[4][20] = {"NOT SYNCHED","PRACH","RAR","PUSCH"};
extern double cpuf;
void Msg1_transmitted(module_id_t module_idP, uint8_t CC_id, frame_t frameP, uint8_t eNB_id);
void Msg3_transmitted(module_id_t module_idP, uint8_t CC_id, frame_t frameP, uint8_t eNB_id);
-3
View File
@@ -852,13 +852,10 @@ int main(int argc, char **argv)
if (g_rbSize < 0) g_rbSize = N_RB_DL - g_rbStart;
double fs,txbw,rxbw;
uint32_t samples;
get_samplerate_and_bw(mu,
N_RB_DL,
frame_parms->threequarter_fs,
&fs,
&samples,
&txbw,
&rxbw);
+1 -3
View File
@@ -437,9 +437,7 @@ int main(int argc, char **argv)
double fs=0, eps;
double scs = 30000;
double txbw, rxbw;
uint32_t samples;
get_samplerate_and_bw(mu, N_RB_DL, frame_parms->threequarter_fs, &fs, &samples, &txbw, &rxbw);
get_samplerate_and_bw(mu, N_RB_DL, frame_parms->threequarter_fs, &fs, &txbw, &rxbw);
// cfo with respect to sub-carrier spacing
eps = cfo/scs;
-3
View File
@@ -444,13 +444,10 @@ int main(int argc, char **argv)
gNB->common_vars.rxdataF[0][i] = malloc16_clear(gNB->frame_parms.samples_per_frame_wCP * sizeof(c16_t));
double fs,txbw,rxbw;
uint32_t samples;
get_samplerate_and_bw(mu,
N_RB_DL,
frame_parms->threequarter_fs,
&fs,
&samples,
&txbw,
&rxbw);
+1 -2
View File
@@ -325,8 +325,7 @@ int main(int argc, char *argv[])
snr1 = snr0 + 10;
double sampling_rate, tx_bandwidth, rx_bandwidth;
uint32_t samples;
get_samplerate_and_bw(mu, N_RB_DL, threequarter_fs, &sampling_rate, &samples, &tx_bandwidth, &rx_bandwidth);
get_samplerate_and_bw(mu, N_RB_DL, threequarter_fs, &sampling_rate, &tx_bandwidth, &rx_bandwidth);
// Initialize gNB
gNB = calloc_or_fail(1, sizeof(PHY_VARS_gNB));
-2
View File
@@ -711,12 +711,10 @@ int main(int argc, char *argv[])
snr1 = snr0 + 10;
double sampling_frequency, tx_bandwidth, rx_bandwidth;
uint32_t samples;
get_samplerate_and_bw(mu,
N_RB_DL,
threequarter_fs,
&sampling_frequency,
&samples,
&tx_bandwidth,
&rx_bandwidth);