From a17b08f70aa42101e08278964c6aa10e9c4ef9ab Mon Sep 17 00:00:00 2001 From: Guy De Souza Date: Fri, 10 Aug 2018 15:33:00 +0200 Subject: [PATCH] Symbol DMRS mapping fix --- openair1/PHY/NR_TRANSPORT/nr_dci.c | 43 ++++++++++--------- openair1/PHY/NR_TRANSPORT/nr_dci.h | 2 +- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 4 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 2 +- 4 files changed, 28 insertions(+), 23 deletions(-) diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index c830278b44..f58561fecc 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -154,14 +154,14 @@ void nr_pdcch_scrambling(uint32_t *in, uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, t_nrPolar_paramsPtr *nrPolar_params, - uint32_t *gold_pdcch_dmrs, + uint32_t **gold_pdcch_dmrs, int32_t** txdataF, int16_t amp, NR_DL_FRAME_PARMS frame_parms, nfapi_nr_config_request_t config) { - int16_t mod_dmrs[NR_MAX_PDCCH_DMRS_LENGTH>>1]; + int16_t mod_dmrs[3][NR_MAX_PDCCH_DMRS_LENGTH>>1]; // 3 for the max coreset duration uint8_t idx=0; uint16_t a; int k,l,k_prime,dci_idx, dmrs_idx; @@ -173,20 +173,31 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, uint16_t dmrs_length = dci_alloc.L*36; //2(QPSK)*3(per RB)*6(REG per CCE) uint16_t encoded_length = dci_alloc.L*108; //2(QPSK)*9(per RB)*6(REG per CCE) + /*The coreset is initialised + * in frequency: the first subcarrier is obtained by adding the first CRB overlapping the SSB and the rb_offset + * in time: by its first slot and its first symbol*/ + uint8_t cset_start_sc = frame_parms.first_carrier_offset + ((int)floor(frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_params.rb_offset)*NR_NB_SC_PER_RB; + uint8_t cset_start_symb = pdcch_params.first_slot*frame_parms.symbols_per_slot + pdcch_params.first_symbol; + dci_idx = 0; + dmrs_idx = 0; + /// DMRS QPSK modulation /*There is a need to shift from which index the pregenerated DMRS sequence is used * see 38211 r15.2.0 section 7.4.1.3.2: assumption is the reference point for k refers to the DMRS sequence*/ if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG) gold_pdcch_dmrs += ((int)floor(frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_params.rb_offset)*3/32; - for (int i=0; i>1; i++) { - idx = ((((gold_pdcch_dmrs[(i<<1)>>5])>>((i<<1)&0x1f))&1)<<1) ^ (((gold_pdcch_dmrs[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1); - mod_dmrs[i<<1] = nr_mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; - mod_dmrs[(i<<1)+1] = nr_mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; -#ifdef DEBUG_PDCCH_DMRS - printf("i %d idx %d gold seq %u b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, gold_pdcch_dmrs[(i<<1)>>5], (((gold_pdcch_dmrs[(i<<1)>>5])>>((i<<1)&0x1f))&1), - (((gold_pdcch_dmrs[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), mod_dmrs[(i<<1)], mod_dmrs[(i<<1)+1]); -#endif + for (int symb=cset_start_symb; symb>1; i++) { + idx = ((((gold_pdcch_dmrs[symb][(i<<1)>>5])>>((i<<1)&0x1f))&1)<<1) ^ (((gold_pdcch_dmrs[symb][((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1); + mod_dmrs[symb][i<<1] = nr_mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1]; + mod_dmrs[symb][(i<<1)+1] = nr_mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1]; + #ifdef DEBUG_PDCCH_DMRS + printf("symb %d i %d idx %d gold seq %u b0-b1 %d-%d mod_dmrs %d %d\n", symb, i, idx, gold_pdcch_dmrs[symb][(i<<1)>>5], + (((gold_pdcch_dmrs[symb][(i<<1)>>5])>>((i<<1)&0x1f))&1), (((gold_pdcch_dmrs[symb][((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), + mod_dmrs[symb][(i<<1)], mod_dmrs[symb][(i<<1)+1]); + #endif + } } /// DCI payload processing @@ -225,14 +236,6 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, /// Resource mapping a = (config.rf_config.tx_antenna_ports.value == 1) ? amp : (amp*ONE_OVER_SQRT2_Q15)>>15; - /*The coreset is initialised - * in frequency: the first subcarrier is obtained by adding the first CRB overlapping the SSB and the rb_offset - * in time: by its first slot and its first symbol*/ - uint8_t cset_start_sc = frame_parms.first_carrier_offset + ((int)floor(frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_params.rb_offset)*NR_NB_SC_PER_RB; - uint8_t cset_start_symb = pdcch_params.first_slot*frame_parms.symbols_per_slot + pdcch_params.first_symbol; - dci_idx = 0; - dmrs_idx = 0; - for (int aa = 0; aa < config.rf_config.tx_antenna_ports.value; aa++) { if (cset_start_sc >= frame_parms.ofdm_symbol_size) @@ -248,8 +251,8 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, k_prime = 0; for (int m=0; m> 15; - ((int16_t*)txdataF[aa])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (a * mod_dmrs[(dmrs_idx<<1) + 1]) >> 15; + ((int16_t*)txdataF[aa])[(l*frame_parms.ofdm_symbol_size + k)<<1] = (a * mod_dmrs[l][dmrs_idx<<1]) >> 15; + ((int16_t*)txdataF[aa])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (a * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15; k_prime++; dmrs_idx++; } diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.h b/openair1/PHY/NR_TRANSPORT/nr_dci.h index e1e56becbe..f7c885b499 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.h +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.h @@ -34,7 +34,7 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars, t_nrPolar_paramsPtr *nrPolar_params, - uint32_t *gold_pdcch_dmrs, + uint32_t **gold_pdcch_dmrs, int32_t** txdataF, int16_t amp, NR_DL_FRAME_PARMS frame_parms, diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 6ec1fb0409..c3325cb289 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -186,10 +186,12 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, LOG_I(PHY, "[gNB %d] Frame %d subframe %d \ Calling nr_generate_dci_top (number of DCI %d)\n", gNB->Mod_id, frame, subframe, num_dci); + uint8_t slot_idx = gNB->pdcch_vars.dci_alloc[0].pdcch_params.first_slot; + if (nfapi_mode == 0 || nfapi_mode == 1) nr_generate_dci_top(gNB->pdcch_vars, &gNB->nrPolar_params, - gNB->nr_gold_pdcch_dmrs[0][0], + gNB->nr_gold_pdcch_dmrs[slot_idx], gNB->common_vars.txdataF, AMP, *fp, *cfg); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 1868d987a4..339cb14151 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -85,7 +85,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, params_rel15->rnti = 0x03; params_rel15->rnti_type = NFAPI_NR_RNTI_RA; params_rel15->dci_format = NFAPI_NR_DL_DCI_FORMAT_1_0; - params_rel15->aggregation_level = 1; + //params_rel15->aggregation_level = 1; LOG_I(MAC, "DCI type 1 params: rmsi_pdcch_config %d, rnti %d, rnti_type %d, dci_format %d\n \ coreset params: mux_pattern %d, n_rb %d, n_symb %d, rb_offset %d \n \ ss params : nb_ss_sets_per_slot %d, first symb %d, nb_slots %d, sfn_mod2 %d, first slot %d\n",