Move config_uldci() to primitives
This commit is contained in:
Robert Schmidt
@@ -352,82 +352,6 @@ void nr_preprocessor_phytest(module_id_t module_id,
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vrb_map[rb + sched_ctrl->rbStart] = 1;
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vrb_map[rb + sched_ctrl->rbStart] = 1;
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}
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}
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void config_uldci(NR_BWP_Uplink_t *ubwp,
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nfapi_nr_pusch_pdu_t *pusch_pdu,
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
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dci_pdu_rel15_t *dci_pdu_rel15,
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int *dci_formats, int *rnti_types,
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int time_domain_assignment, uint8_t tpc,
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int n_ubwp, int bwp_id) {
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switch(dci_formats[(pdcch_pdu_rel15->numDlDci)-1]) {
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case NR_UL_DCI_FORMAT_0_0:
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dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
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pusch_pdu->rb_start,
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NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275));
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dci_pdu_rel15->time_domain_assignment.val = time_domain_assignment;
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dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping;
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dci_pdu_rel15->mcs = pusch_pdu->mcs_index;
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dci_pdu_rel15->format_indicator = 0;
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dci_pdu_rel15->ndi = pusch_pdu->pusch_data.new_data_indicator;
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dci_pdu_rel15->rv = pusch_pdu->pusch_data.rv_index;
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dci_pdu_rel15->harq_pid = pusch_pdu->pusch_data.harq_process_id;
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dci_pdu_rel15->tpc = tpc;
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break;
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case NR_UL_DCI_FORMAT_0_1:
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dci_pdu_rel15->ndi = pusch_pdu->pusch_data.new_data_indicator;
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dci_pdu_rel15->rv = pusch_pdu->pusch_data.rv_index;
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dci_pdu_rel15->harq_pid = pusch_pdu->pusch_data.harq_process_id;
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dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping;
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dci_pdu_rel15->dai[0].val = 0; //TODO
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// bwp indicator
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if (n_ubwp < 4)
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dci_pdu_rel15->bwp_indicator.val = bwp_id;
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else
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dci_pdu_rel15->bwp_indicator.val = bwp_id - 1; // as per table 7.3.1.1.2-1 in 38.212
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// frequency domain assignment
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if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->resourceAllocation==NR_PUSCH_Config__resourceAllocation_resourceAllocationType1)
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dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
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pusch_pdu->rb_start,
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NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275));
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else
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AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n");
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// time domain assignment
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dci_pdu_rel15->time_domain_assignment.val = time_domain_assignment;
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// mcs
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dci_pdu_rel15->mcs = pusch_pdu->mcs_index;
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// tpc command for pusch
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dci_pdu_rel15->tpc = tpc;
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// SRS resource indicator
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if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->txConfig != NULL) {
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if (*ubwp->bwp_Dedicated->pusch_Config->choice.setup->txConfig == NR_PUSCH_Config__txConfig_codebook)
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dci_pdu_rel15->srs_resource_indicator.val = 0; // taking resource 0 for SRS
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else
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AssertFatal(1==0,"Non Codebook configuration non supported\n");
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}
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// Antenna Ports
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dci_pdu_rel15->antenna_ports.val = 0; // TODO for now it is hardcoded, it should depends on cdm group no data and rank
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// DMRS sequence initialization
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dci_pdu_rel15->dmrs_sequence_initialization.val = pusch_pdu->scid;
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break;
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default :
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AssertFatal(1==0,"Valid UL formats are 0_0 and 0_1 \n");
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}
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LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
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pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci],
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dci_pdu_rel15->frequency_domain_assignment.val,
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dci_pdu_rel15->time_domain_assignment.val,
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dci_pdu_rel15->frequency_hopping_flag.val,
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dci_pdu_rel15->mcs,
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dci_pdu_rel15->tpc,
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dci_pdu_rel15->ndi,
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dci_pdu_rel15->rv);
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}
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void nr_ul_preprocessor_phytest(module_id_t module_id,
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void nr_ul_preprocessor_phytest(module_id_t module_id,
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frame_t frame,
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frame_t frame,
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sub_frame_t slot,
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sub_frame_t slot,
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@@ -637,6 +637,81 @@ void nr_fill_nfapi_dl_pdu(int Mod_idP,
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dl_req->nPDUs += 2;
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dl_req->nPDUs += 2;
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}
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}
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void config_uldci(NR_BWP_Uplink_t *ubwp,
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nfapi_nr_pusch_pdu_t *pusch_pdu,
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
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dci_pdu_rel15_t *dci_pdu_rel15,
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int *dci_formats, int *rnti_types,
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int time_domain_assignment, uint8_t tpc,
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int n_ubwp, int bwp_id) {
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const int bw = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
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switch (dci_formats[(pdcch_pdu_rel15->numDlDci) - 1]) {
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case NR_UL_DCI_FORMAT_0_0:
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dci_pdu_rel15->frequency_domain_assignment.val =
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PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, pusch_pdu->rb_start, bw);
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dci_pdu_rel15->time_domain_assignment.val = time_domain_assignment;
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dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping;
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dci_pdu_rel15->mcs = pusch_pdu->mcs_index;
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dci_pdu_rel15->format_indicator = 0;
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dci_pdu_rel15->ndi = pusch_pdu->pusch_data.new_data_indicator;
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dci_pdu_rel15->rv = pusch_pdu->pusch_data.rv_index;
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dci_pdu_rel15->harq_pid = pusch_pdu->pusch_data.harq_process_id;
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dci_pdu_rel15->tpc = tpc;
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break;
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case NR_UL_DCI_FORMAT_0_1:
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dci_pdu_rel15->ndi = pusch_pdu->pusch_data.new_data_indicator;
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dci_pdu_rel15->rv = pusch_pdu->pusch_data.rv_index;
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dci_pdu_rel15->harq_pid = pusch_pdu->pusch_data.harq_process_id;
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dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping;
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dci_pdu_rel15->dai[0].val = 0; //TODO
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// bwp indicator
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if (n_ubwp < 4)
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dci_pdu_rel15->bwp_indicator.val = bwp_id;
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else
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dci_pdu_rel15->bwp_indicator.val = bwp_id - 1; // as per table 7.3.1.1.2-1 in 38.212
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// frequency domain assignment
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AssertFatal(ubwp->bwp_Dedicated->pusch_Config->choice.setup->resourceAllocation
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== NR_PUSCH_Config__resourceAllocation_resourceAllocationType1,
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"Only frequency resource allocation type 1 is currently supported\n");
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dci_pdu_rel15->frequency_domain_assignment.val =
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PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, pusch_pdu->rb_start, bw);
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// time domain assignment
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dci_pdu_rel15->time_domain_assignment.val = time_domain_assignment;
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// mcs
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dci_pdu_rel15->mcs = pusch_pdu->mcs_index;
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// tpc command for pusch
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dci_pdu_rel15->tpc = tpc;
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// SRS resource indicator
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if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->txConfig != NULL) {
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AssertFatal(*ubwp->bwp_Dedicated->pusch_Config->choice.setup->txConfig == NR_PUSCH_Config__txConfig_codebook,
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"Non Codebook configuration non supported\n");
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dci_pdu_rel15->srs_resource_indicator.val = 0; // taking resource 0 for SRS
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}
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// Antenna Ports
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dci_pdu_rel15->antenna_ports.val = 0; // TODO for now it is hardcoded, it should depends on cdm group no data and rank
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// DMRS sequence initialization
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dci_pdu_rel15->dmrs_sequence_initialization.val = pusch_pdu->scid;
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break;
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default :
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AssertFatal(0, "Valid UL formats are 0_0 and 0_1\n");
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}
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LOG_D(MAC,
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"%s() ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, "
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"time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
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__func__,
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pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci],
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dci_pdu_rel15->frequency_domain_assignment.val,
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dci_pdu_rel15->time_domain_assignment.val,
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dci_pdu_rel15->frequency_hopping_flag.val,
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dci_pdu_rel15->mcs,
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dci_pdu_rel15->tpc,
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dci_pdu_rel15->ndi,
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dci_pdu_rel15->rv);
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}
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void nr_configure_pdcch(gNB_MAC_INST *nr_mac,
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void nr_configure_pdcch(gNB_MAC_INST *nr_mac,
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu,
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu,
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uint16_t rnti,
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uint16_t rnti,
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