maki/openairinterface5g
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

First-level of support for new aarch64 machines

Browse Source 
Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators.

- Changes:
- use SIMDE consistently
- adaptations of LDPC decoder generator for ARMv8 performance
- SIMDe modifications of Intel CRC to allow for aarch64 build.
  optimizations for 128-bit to improve performance of LDPC encode/decode
  on aarch64 (Neoverse 1)
- added BG2 files for 128-bit ldpc encoder (aarch64)
- testing on Xeon
- testing on x86
- minor changes to build/run on x86
- change in crc.h after returning to aarch64
- removed some warning in ldpc decoder generator for x86_64
- char
- Delete irrelevant constants
- Correctly declare variables
- Define stdbool for all architectures
- Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE
- Remove commented code
- Fix CMakeLists.txt
- Include SIMDE avx2 functions in tools_defs.h
This commit is contained in:
Raymond Knopp
2023-09-13 17:19:20 +02:00
committed by Robert Schmidt
parent 79fd37b489
commit a7bc282302
168 changed files with 30595 additions and 21476 deletions
Download Patch File Download Diff File Expand all files Collapse all files
openair1/PHY/CODING/nrLDPC_encoder/ldpc_BG2_Zc320_byte.c
+4 -3
View File
@@ -1,9 +1,9 @@
#ifdef __AVX2__
#include "PHY/sse_intrin.h"
// generated code for Zc=320, byte encoding
static inline __attribute__ ((no_sanitize("address", "undefined"))) void ldpc_BG2_Zc320_byte(uint8_t *c,uint8_t *d) {
__m256i *csimd=(__m256i *)c,*dsimd=(__m256i *)d;
__m256i *c2,*d2;
simde__m256i *csimd=(simde__m256i *)c,*dsimd=(simde__m256i *)d;
simde__m256i *c2,*d2;
int i2;
for (i2=0; i2<10; i2++) {
@@ -137,3 +137,4 @@ static inline __attribute__ ((no_sanitize("address", "undefined"))) void ldpc_BG
d2[410]=simde_mm256_xor_si256(c2[4601],simde_mm256_xor_si256(c2[4401],simde_mm256_xor_si256(c2[6205],simde_mm256_xor_si256(c2[2002],simde_mm256_xor_si256(c2[4621],simde_mm256_xor_si256(c2[4421],simde_mm256_xor_si256(c2[4024],simde_mm256_xor_si256(c2[5622],simde_mm256_xor_si256(c2[20],simde_mm256_xor_si256(c2[4641],simde_mm256_xor_si256(c2[4441],simde_mm256_xor_si256(c2[1042],simde_mm256_xor_si256(c2[4661],simde_mm256_xor_si256(c2[4461],simde_mm256_xor_si256(c2[3665],simde_mm256_xor_si256(c2[5064],simde_mm256_xor_si256(c2[4481],simde_mm256_xor_si256(c2[6281],simde_mm256_xor_si256(c2[5684],simde_mm256_xor_si256(c2[4501],simde_mm256_xor_si256(c2[1706],simde_mm256_xor_si256(c2[500],simde_mm256_xor_si256(c2[4721],simde_mm256_xor_si256(c2[4521],simde_mm256_xor_si256(c2[2924],simde_mm256_xor_si256(c2[522],simde_mm256_xor_si256(c2[4541],simde_mm256_xor_si256(c2[3143],simde_mm256_xor_si256(c2[4561],simde_mm256_xor_si256(c2[565],simde_mm256_xor_si256(c2[2363],simde_mm256_xor_si256(c2[4781],simde_mm256_xor_si256(c2[4581],simde_mm256_xor_si256(c2[2783],c2[983]))))))))))))))))))))))))))))))))));
}
}
#endif