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First-level of support for new aarch64 machines

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Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators.

- Changes:
- use SIMDE consistently
- adaptations of LDPC decoder generator for ARMv8 performance
- SIMDe modifications of Intel CRC to allow for aarch64 build.
  optimizations for 128-bit to improve performance of LDPC encode/decode
  on aarch64 (Neoverse 1)
- added BG2 files for 128-bit ldpc encoder (aarch64)
- testing on Xeon
- testing on x86
- minor changes to build/run on x86
- change in crc.h after returning to aarch64
- removed some warning in ldpc decoder generator for x86_64
- char
- Delete irrelevant constants
- Correctly declare variables
- Define stdbool for all architectures
- Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE
- Remove commented code
- Fix CMakeLists.txt
- Include SIMDE avx2 functions in tools_defs.h
This commit is contained in:
Raymond Knopp
2023-09-13 17:19:20 +02:00
committed by Robert Schmidt
parent 79fd37b489
commit a7bc282302
168 changed files with 30595 additions and 21476 deletions
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openair1/PHY/CODING/nrLDPC_encoder/ldpc_BG2_Zc352_byte.c
+4 -2
View File
@@ -1,9 +1,10 @@
#ifdef __AVX2__
#include "PHY/sse_intrin.h"
// generated code for Zc=352, byte encoding
static inline __attribute__ ((no_sanitize("address", "undefined"))) void ldpc_BG2_Zc352_byte(uint8_t *c,uint8_t *d) {
__m256i *csimd=(__m256i *)c,*dsimd=(__m256i *)d;
simde__m256i *csimd=(simde__m256i *)c,*dsimd=(simde__m256i *)d;
__m256i *c2,*d2;
simde__m256i *c2,*d2;
int i2;
for (i2=0; i2<11; i2++) {
@@ -137,3 +138,4 @@ static inline __attribute__ ((no_sanitize("address", "undefined"))) void ldpc_BG
d2[451]=simde_mm256_xor_si256(c2[885],simde_mm256_xor_si256(c2[665],simde_mm256_xor_si256(c2[5280],simde_mm256_xor_si256(c2[1983],simde_mm256_xor_si256(c2[5086],simde_mm256_xor_si256(c2[4866],simde_mm256_xor_si256(c2[3327],simde_mm256_xor_si256(c2[6183],simde_mm256_xor_si256(c2[906],simde_mm256_xor_si256(c2[4884],simde_mm256_xor_si256(c2[4664],simde_mm256_xor_si256(c2[4669],simde_mm256_xor_si256(c2[2486],simde_mm256_xor_si256(c2[2266],simde_mm256_xor_si256(c2[1828],simde_mm256_xor_si256(c2[4029],simde_mm256_xor_si256(c2[1410],simde_mm256_xor_si256(c2[5590],simde_mm256_xor_si256(c2[4713],simde_mm256_xor_si256(c2[1870],simde_mm256_xor_si256(c2[1434],simde_mm256_xor_si256(c2[1430],simde_mm256_xor_si256(c2[3653],simde_mm256_xor_si256(c2[3433],simde_mm256_xor_si256(c2[6733],simde_mm256_xor_si256(c2[5412],simde_mm256_xor_si256(c2[2795],simde_mm256_xor_si256(c2[157],simde_mm256_xor_si256(c2[4141],simde_mm256_xor_si256(c2[4800],simde_mm256_xor_si256(c2[5456],simde_mm256_xor_si256(c2[862],simde_mm256_xor_si256(c2[642],simde_mm256_xor_si256(c2[2842],c2[3721]))))))))))))))))))))))))))))))))));
}
}
#endif