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First-level of support for new aarch64 machines

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Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators.

- Changes:
- use SIMDE consistently
- adaptations of LDPC decoder generator for ARMv8 performance
- SIMDe modifications of Intel CRC to allow for aarch64 build.
  optimizations for 128-bit to improve performance of LDPC encode/decode
  on aarch64 (Neoverse 1)
- added BG2 files for 128-bit ldpc encoder (aarch64)
- testing on Xeon
- testing on x86
- minor changes to build/run on x86
- change in crc.h after returning to aarch64
- removed some warning in ldpc decoder generator for x86_64
- char
- Delete irrelevant constants
- Correctly declare variables
- Define stdbool for all architectures
- Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE
- Remove commented code
- Fix CMakeLists.txt
- Include SIMDE avx2 functions in tools_defs.h
This commit is contained in:
Raymond Knopp
2023-09-13 17:19:20 +02:00
committed by Robert Schmidt
parent 79fd37b489
commit a7bc282302
168 changed files with 30595 additions and 21476 deletions
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openair1/PHY/CODING/nrLDPC_encoder/ldpc_BG2_Zc96_byte.c
+4 -2
View File
@@ -1,9 +1,10 @@
#ifdef __AVX2__
#include "PHY/sse_intrin.h"
// generated code for Zc=96, byte encoding
static inline __attribute__ ((no_sanitize("address", "undefined"))) void ldpc_BG2_Zc96_byte(uint8_t *c,uint8_t *d) {
__m256i *csimd=(__m256i *)c,*dsimd=(__m256i *)d;
simde__m256i *csimd=(simde__m256i *)c,*dsimd=(simde__m256i *)d;
__m256i *c2,*d2;
simde__m256i *c2,*d2;
int i2;
for (i2=0; i2<3; i2++) {
@@ -137,3 +138,4 @@ static inline __attribute__ ((no_sanitize("address", "undefined"))) void ldpc_BG
d2[123]=simde_mm256_xor_si256(c2[601],simde_mm256_xor_si256(c2[541],simde_mm256_xor_si256(c2[1322],simde_mm256_xor_si256(c2[1202],simde_mm256_xor_si256(c2[1747],simde_mm256_xor_si256(c2[1687],simde_mm256_xor_si256(c2[788],simde_mm256_xor_si256(c2[186],simde_mm256_xor_si256(c2[1147],simde_mm256_xor_si256(c2[133],simde_mm256_xor_si256(c2[73],simde_mm256_xor_si256(c2[613],simde_mm256_xor_si256(c2[1818],simde_mm256_xor_si256(c2[1758],simde_mm256_xor_si256(c2[1880],simde_mm256_xor_si256(c2[980],simde_mm256_xor_si256(c2[684],simde_mm256_xor_si256(c2[566],simde_mm256_xor_si256(c2[746],simde_mm256_xor_si256(c2[1411],simde_mm256_xor_si256(c2[211],simde_mm256_xor_si256(c2[450],simde_mm256_xor_si256(c2[217],simde_mm256_xor_si256(c2[157],simde_mm256_xor_si256(c2[1598],simde_mm256_xor_si256(c2[1358],simde_mm256_xor_si256(c2[1363],simde_mm256_xor_si256(c2[1064],simde_mm256_xor_si256(c2[1249],simde_mm256_xor_si256(c2[830],simde_mm256_xor_si256(c2[1430],simde_mm256_xor_si256(c2[535],simde_mm256_xor_si256(c2[475],simde_mm256_xor_si256(c2[1855],c2[1315]))))))))))))))))))))))))))))))))));
}
}
#endif