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First-level of support for new aarch64 machines

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Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators.

- Changes:
- use SIMDE consistently
- adaptations of LDPC decoder generator for ARMv8 performance
- SIMDe modifications of Intel CRC to allow for aarch64 build.
  optimizations for 128-bit to improve performance of LDPC encode/decode
  on aarch64 (Neoverse 1)
- added BG2 files for 128-bit ldpc encoder (aarch64)
- testing on Xeon
- testing on x86
- minor changes to build/run on x86
- change in crc.h after returning to aarch64
- removed some warning in ldpc decoder generator for x86_64
- char
- Delete irrelevant constants
- Correctly declare variables
- Define stdbool for all architectures
- Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE
- Remove commented code
- Fix CMakeLists.txt
- Include SIMDE avx2 functions in tools_defs.h
This commit is contained in:
Raymond Knopp
2023-09-13 17:19:20 +02:00
committed by Robert Schmidt
parent 79fd37b489
commit a7bc282302
168 changed files with 30595 additions and 21476 deletions
Download Patch File Download Diff File Expand all files Collapse all files
openair1/PHY/CODING/nrSmallBlock/decodeSmallBlock.c
+10 -13
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@@ -54,9 +54,9 @@ uint16_t decodeSmallBlock(int8_t *in, uint8_t len){
Rhat[j] += in[k] * hadamard32InterleavedTransposed[j][k];
for (int i = 0; i < NR_SMALL_BLOCK_CODED_BITS; i += 16) {
__m256i a15_a0 = simde_mm256_loadu_si256((__m256i*)&Rhat[i]);
simde__m256i a15_a0 = simde_mm256_loadu_si256((simde__m256i*)&Rhat[i]);
a15_a0 = simde_mm256_abs_epi16(a15_a0);
simde_mm256_storeu_si256((__m256i*)(&Rhatabs[i]), a15_a0);
simde_mm256_storeu_si256((simde__m256i*)(&Rhatabs[i]), a15_a0);
}
maxVal = Rhatabs[0];
for (int k = 1; k < jmax; ++k){
@@ -82,23 +82,20 @@ uint16_t decodeSmallBlock(int8_t *in, uint8_t len){
#if !defined(__AVX512F__)
int8_t DmatrixElement[NR_SMALL_BLOCK_CODED_BITS] = {0};
#endif
__m256i _in_256 = simde_mm256_loadu_si256 ((__m256i*)&in[0]);
__m256i _maskD_256, _Dmatrixj_256, _maskH_256, _DmatrixElement_256;
simde__m256i _in_256 = simde_mm256_loadu_si256 ((simde__m256i*)&in[0]);
simde__m256i _maskD_256, _Dmatrixj_256, _maskH_256, _DmatrixElement_256;
for (int j = 0; j < ( 1<<(len-6) ); ++j) {
_maskD_256 = simde_mm256_loadu_si256 ((__m256i*)(&maskD[j][0]));
_maskD_256 = simde_mm256_loadu_si256 ((simde__m256i*)(&maskD[j][0]));
_Dmatrixj_256 = simde_mm256_sign_epi8 (_in_256, _maskD_256);
for (int k = 0; k < NR_SMALL_BLOCK_CODED_BITS; ++k) {
_maskH_256 = simde_mm256_loadu_si256 ((__m256i*)(&hadamard32InterleavedTransposed[k][0]));
_maskH_256 = simde_mm256_loadu_si256 ((simde__m256i*)(&hadamard32InterleavedTransposed[k][0]));
_DmatrixElement_256 = simde_mm256_sign_epi8 (_Dmatrixj_256, _maskH_256);
#if defined(__AVX512F__)
DmatrixElementVal = _mm512_reduce_add_epi32 (
_mm512_add_epi32(
_mm512_cvtepi8_epi32 (simde_mm256_extracti128_si256 (_DmatrixElement_256, 1)),
_mm512_cvtepi8_epi32 (simde_mm256_castsi256_si128 (_DmatrixElement_256))
)
);
DmatrixElementVal = simde_mm512_reduce_add_epi32(
simde_mm512_add_epi32(simde_mm512_cvtepi8_epi32(simde_mm256_extracti128_si256(_DmatrixElement_256, 1)),
simde_mm512_cvtepi8_epi32(simde_mm256_castsi256_si128(_DmatrixElement_256))));
#else
simde_mm256_storeu_si256((__m256i*)(&DmatrixElement[0]), _DmatrixElement_256);
simde_mm256_storeu_si256((simde__m256i*)(&DmatrixElement[0]), _DmatrixElement_256);
for (int i = 0; i < NR_SMALL_BLOCK_CODED_BITS; ++i)
DmatrixElementVal += DmatrixElement[i];
#endif