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First-level of support for new aarch64 machines

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Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators.

- Changes:
- use SIMDE consistently
- adaptations of LDPC decoder generator for ARMv8 performance
- SIMDe modifications of Intel CRC to allow for aarch64 build.
  optimizations for 128-bit to improve performance of LDPC encode/decode
  on aarch64 (Neoverse 1)
- added BG2 files for 128-bit ldpc encoder (aarch64)
- testing on Xeon
- testing on x86
- minor changes to build/run on x86
- change in crc.h after returning to aarch64
- removed some warning in ldpc decoder generator for x86_64
- char
- Delete irrelevant constants
- Correctly declare variables
- Define stdbool for all architectures
- Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE
- Remove commented code
- Fix CMakeLists.txt
- Include SIMDE avx2 functions in tools_defs.h
This commit is contained in:
Raymond Knopp
2023-09-13 17:19:20 +02:00
committed by Robert Schmidt
parent 79fd37b489
commit a7bc282302
168 changed files with 30595 additions and 21476 deletions
Download Patch File Download Diff File Expand all files Collapse all files
radio/IRIS/iris_lib.cpp
+8 -18
View File
@@ -139,20 +139,14 @@ trx_iris_write(openair0_device *device, openair0_timestamp timestamp, void **buf
int flag = 0;
iris_state_t *s = (iris_state_t *) device->priv;
int nsamps2; // aligned to upper 32 or 16 byte boundary
#if defined(__x86_64) || defined(__i386__)
int nsamps2; // aligned to upper 32 or 16 byte boundary
nsamps2 = (nsamps+7)>>3;
__m256i buff_tx[2][nsamps2];
#else
#error unsupported CPU architecture, iris device cannot be built
#endif
simde__m256i buff_tx[2][nsamps2];
// bring RX data into 12 LSBs for softmodem RX
for (int i=0; i<cc; i++) {
for (int j=0; j<nsamps2; j++) {
#if defined(__x86_64__) || defined(__i386__)
buff_tx[i][j] = simde_mm256_slli_epi16(((__m256i *)buff[i])[j],4);
#endif
for (int j = 0; j < nsamps2; j++) {
buff_tx[i][j] = simde_mm256_slli_epi16(((simde__m256i *)buff[i])[j], 4);
}
}
@@ -228,11 +222,9 @@ static int trx_iris_read(openair0_device *device, openair0_timestamp *ptimestamp
int r;
int m = s->rx_num_channels;
int nsamps2; // aligned to upper 32 or 16 byte boundary
#if defined(__x86_64) || defined(__i386__)
int nsamps2; // aligned to upper 32 or 16 byte boundary
nsamps2 = (nsamps+7)>>3;
__m256i buff_tmp[2][nsamps2];
#endif
simde__m256i buff_tmp[2][nsamps2];
for (r = 0; r < s->device_num; r++) {
flags = 0;
@@ -301,10 +293,8 @@ static int trx_iris_read(openair0_device *device, openair0_timestamp *ptimestamp
// bring RX data into 12 LSBs for softmodem RX
for (int i=0; i<cc; i++) {
for (int j=0; j<nsamps2; j++) {
#if defined(__x86_64__) || defined(__i386__)
((__m256i *)buff[i])[j] = simde_mm256_srai_epi16(buff_tmp[i][j],4);
#endif
for (int j = 0; j < nsamps2; j++) {
((simde__m256i *)buff[i])[j] = simde_mm256_srai_epi16(buff_tmp[i][j], 4);
}
}
}