First-level of support for new aarch64 machines
Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators. - Changes: - use SIMDE consistently - adaptations of LDPC decoder generator for ARMv8 performance - SIMDe modifications of Intel CRC to allow for aarch64 build. optimizations for 128-bit to improve performance of LDPC encode/decode on aarch64 (Neoverse 1) - added BG2 files for 128-bit ldpc encoder (aarch64) - testing on Xeon - testing on x86 - minor changes to build/run on x86 - change in crc.h after returning to aarch64 - removed some warning in ldpc decoder generator for x86_64 - char - Delete irrelevant constants - Correctly declare variables - Define stdbool for all architectures - Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE - Remove commented code - Fix CMakeLists.txt - Include SIMDE avx2 functions in tools_defs.h
This commit is contained in:
Raymond Knopp
committed by
Robert Schmidt
Robert Schmidt
parent
79fd37b489
commit
a7bc282302
+52
-85
@@ -470,33 +470,20 @@ static int trx_usrp_write(openair0_device *device,
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last_packet_state = true;
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}
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if(usrp_tx_thread == 0){
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#if defined(__x86_64) || defined(__i386__)
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if (usrp_tx_thread == 0) {
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nsamps2 = (nsamps+7)>>3;
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__m256i buff_tx[cc<2?2:cc][nsamps2];
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#elif defined(__arm__) || defined(__aarch64__)
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nsamps2 = (nsamps+3)>>2;
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int16x8_t buff_tx[cc<2?2:cc][nsamps2];
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#else
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#error Unsupported CPU architecture, USRP device cannot be built
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#endif
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simde__m256i buff_tx[cc < 2 ? 2 : cc][nsamps2];
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// bring RX data into 12 LSBs for softmodem RX
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for (int i=0; i<cc; i++) {
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for (int j=0; j<nsamps2; j++) {
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#if defined(__x86_64__) || defined(__i386__)
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if ((((uintptr_t) buff[i])&0x1F)==0) {
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buff_tx[i][j] = simde_mm256_slli_epi16(((__m256i *)buff[i])[j],4);
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// bring RX data into 12 LSBs for softmodem RX
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for (int i = 0; i < cc; i++) {
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for (int j = 0; j < nsamps2; j++) {
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if ((((uintptr_t)buff[i]) & 0x1F) == 0) {
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buff_tx[i][j] = simde_mm256_slli_epi16(((simde__m256i *)buff[i])[j], 4);
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} else {
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simde__m256i tmp = simde_mm256_loadu_si256(((simde__m256i *)buff[i]) + j);
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buff_tx[i][j] = simde_mm256_slli_epi16(tmp, 4);
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}
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}
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else
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{
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__m256i tmp = simde_mm256_loadu_si256(((__m256i *)buff[i])+j);
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buff_tx[i][j] = simde_mm256_slli_epi16(tmp,4);
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}
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#elif defined(__arm__) || defined(__aarch64__)
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buff_tx[i][j] = vshlq_n_s16(((int16x8_t *)buff[i])[j],4);
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#endif
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}
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}
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s->tx_md.has_time_spec = true;
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@@ -529,33 +516,35 @@ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_SWITCHI
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if (ret != nsamps) LOG_E(HW,"[xmit] tx samples %d != %d\n",ret,nsamps);
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return ret;
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}
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else{
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pthread_mutex_lock(&write_thread->mutex_write);
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} else {
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pthread_mutex_lock(&write_thread->mutex_write);
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if(write_thread->count_write >= MAX_WRITE_THREAD_PACKAGE){
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LOG_W(HW,"Buffer overflow, count_write = %d, start = %d end = %d, resetting write package\n", write_thread->count_write, write_thread->start, write_thread->end);
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write_thread->end = write_thread->start;
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write_thread->count_write = 0;
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if (write_thread->count_write >= MAX_WRITE_THREAD_PACKAGE) {
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LOG_W(HW,
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"Buffer overflow, count_write = %d, start = %d end = %d, resetting write package\n",
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write_thread->count_write,
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write_thread->start,
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write_thread->end);
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write_thread->end = write_thread->start;
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write_thread->count_write = 0;
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}
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end = write_thread->end;
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write_package[end].timestamp = timestamp;
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write_package[end].nsamps = nsamps;
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write_package[end].cc = cc;
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write_package[end].first_packet = first_packet_state;
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write_package[end].last_packet = last_packet_state;
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write_package[end].flags_gpio = flags_gpio;
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for (int i = 0; i < cc; i++)
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write_package[end].buff[i] = buff[i];
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write_thread->count_write++;
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write_thread->end = (write_thread->end + 1) % MAX_WRITE_THREAD_PACKAGE;
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LOG_D(HW, "Signaling TX TS %llu\n", (unsigned long long)timestamp);
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pthread_cond_signal(&write_thread->cond_write);
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pthread_mutex_unlock(&write_thread->mutex_write);
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return 0;
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}
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end = write_thread->end;
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write_package[end].timestamp = timestamp;
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write_package[end].nsamps = nsamps;
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write_package[end].cc = cc;
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write_package[end].first_packet = first_packet_state;
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write_package[end].last_packet = last_packet_state;
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write_package[end].flags_gpio = flags_gpio;
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for (int i = 0; i < cc; i++)
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write_package[end].buff[i] = buff[i];
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write_thread->count_write++;
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write_thread->end = (write_thread->end + 1)% MAX_WRITE_THREAD_PACKAGE;
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LOG_D(HW,"Signaling TX TS %llu\n",(unsigned long long)timestamp);
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pthread_cond_signal(&write_thread->cond_write);
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pthread_mutex_unlock(&write_thread->mutex_write);
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return 0;
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}
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}
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//-----------------------start--------------------------
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@@ -609,34 +598,22 @@ void *trx_usrp_write_thread(void * arg){
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LOG_W(HW,"count write = %d, start = %d, end = %d\n", write_thread->count_write, write_thread->start, write_thread->end);
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}*/
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#if defined(__x86_64) || defined(__i386__)
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nsamps2 = (nsamps+7)>>3;
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__m256i buff_tx[cc<2?2:cc][nsamps2];
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#elif defined(__arm__) || defined(__aarch64__)
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nsamps2 = (nsamps+3)>>2;
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int16x8_t buff_tx[cc<2?2:cc][nsamps2];
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#else
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#error Unsupported CPU architecture, USRP device cannot be built
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#endif
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simde__m256i buff_tx[cc < 2 ? 2 : cc][nsamps2];
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// bring RX data into 12 LSBs for softmodem RX
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for (int i=0; i<cc; i++) {
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for (int j=0; j<nsamps2; j++) {
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#if defined(__x86_64__) || defined(__i386__)
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// bring RX data into 12 LSBs for softmodem RX
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for (int i = 0; i < cc; i++) {
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for (int j = 0; j < nsamps2; j++) {
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if ((((uintptr_t) buff[i])&0x1F)==0) {
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buff_tx[i][j] = simde_mm256_slli_epi16(((__m256i *)buff[i])[j],4);
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buff_tx[i][j] = simde_mm256_slli_epi16(((simde__m256i *)buff[i])[j], 4);
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}
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else
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{
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__m256i tmp = simde_mm256_loadu_si256(((__m256i *)buff[i])+j);
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simde__m256i tmp = simde_mm256_loadu_si256(((simde__m256i *)buff[i]) + j);
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buff_tx[i][j] = simde_mm256_slli_epi16(tmp,4);
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}
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#elif defined(__arm__) || defined(__aarch64__)
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buff_tx[i][j] = vshlq_n_s16(((int16x8_t *)buff[i])[j],4);
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#endif
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}
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}
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}
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}
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s->tx_md.has_time_spec = true;
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s->tx_md.start_of_burst = (s->tx_count==0) ? true : first_packet;
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@@ -723,14 +700,9 @@ static void trx_usrp_write_reset(openair0_thread_t *wt) {
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static int trx_usrp_read(openair0_device *device, openair0_timestamp *ptimestamp, void **buff, int nsamps, int cc) {
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usrp_state_t *s = (usrp_state_t *)device->priv;
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int samples_received=0;
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int nsamps2; // aligned to upper 32 or 16 byte boundary
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#if defined(__x86_64) || defined(__i386__)
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int nsamps2; // aligned to upper 32 or 16 byte boundary
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nsamps2 = (nsamps+7)>>3;
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__m256i buff_tmp[cc<2 ? 2 : cc][nsamps2];
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#elif defined(__arm__) || defined(__aarch64__)
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nsamps2 = (nsamps+3)>>2;
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int16x8_t buff_tmp[cc<2 ? 2 : cc][nsamps2];
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#endif
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simde__m256i buff_tmp[cc < 2 ? 2 : cc][nsamps2];
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static int read_count = 0;
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int rxshift;
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switch (device->type) {
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@@ -772,21 +744,16 @@ static int trx_usrp_read(openair0_device *device, openair0_timestamp *ptimestamp
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// bring RX data into 12 LSBs for softmodem RX
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for (int i=0; i<cc; i++) {
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for (int j=0; j<nsamps2; j++) {
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#if defined(__x86_64__) || defined(__i386__)
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for (int j = 0; j < nsamps2; j++) {
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// FK: in some cases the buffer might not be 32 byte aligned, so we cannot use avx2
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if ((((uintptr_t) buff[i])&0x1F)==0) {
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((__m256i *)buff[i])[j] = simde_mm256_srai_epi16(buff_tmp[i][j],rxshift);
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((simde__m256i *)buff[i])[j] = simde_mm256_srai_epi16(buff_tmp[i][j], rxshift);
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} else {
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__m256i tmp = simde_mm256_srai_epi16(buff_tmp[i][j],rxshift);
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simde_mm256_storeu_si256(((__m256i *)buff[i])+j, tmp);
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simde__m256i tmp = simde_mm256_srai_epi16(buff_tmp[i][j], rxshift);
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simde_mm256_storeu_si256(((simde__m256i *)buff[i]) + j, tmp);
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}
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}
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#elif defined(__arm__) || defined(__aarch64__)
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for (int j=0; j<nsamps2; j++)
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((int16x8_t *)buff[i])[j] = vshrq_n_s16(buff_tmp[i][j],rxshift);
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#endif
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}
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if (samples_received < nsamps) {
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