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simplify thread pool configuration

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fix segv

fix bug redeclaration of same struct in phy sim

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This commit is contained in:
laurent
2022-09-02 11:36:47 +02:00
parent 8229f00d0e
commit aa2a36768c
63 changed files with 81 additions and 153 deletions
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ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml
+1 -1
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@@ -52,7 +52,7 @@
<testCase id="090102">
<class>Initialize_OAI_UE</class>
<desc>Initialize NR UE USRP</desc>
<Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --ue-rxgain 50 --rrc_config_path . --dlsch-parallel 4 --log_config.global_log_options level,nocolor,time</Initialize_OAI_UE_args>
<Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --ue-rxgain 50 --rrc_config_path . --log_config.global_log_options level,nocolor,time</Initialize_OAI_UE_args>
<air_interface>NR</air_interface>
</testCase>
ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml
+1 -1
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@@ -52,7 +52,7 @@
<testCase id="090104">
<class>Initialize_OAI_UE</class>
<desc>Initialize NR UE USRP</desc>
<Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --ue-rxgain 75 --rrc_config_path . --dlsch-parallel 4 --log_config.global_log_options level,nocolor,time</Initialize_OAI_UE_args>
<Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --ue-rxgain 75 --rrc_config_path . --log_config.global_log_options level,nocolor,time</Initialize_OAI_UE_args>
<air_interface>NR</air_interface>
</testCase>