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Merge remote-tracking branch 'NR_RRC_harq_hacks'

Browse Source 
Conflicts:
	openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c
	openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
	openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
	openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
This commit is contained in:
Thomas Schlichter
2020-07-09 10:27:27 +02:00
parent 52e49fd8ec 614af99745
commit aea3bc2d42
87 changed files with 5983 additions and 3266 deletions
Download Patch File Download Diff File Expand all files Collapse all files
openair2/COMMON/platform_constants.h
+1
View File
@@ -101,6 +101,7 @@
#define NUMBER_OF_NR_DLSCH_MAX 2//16
#define NUMBER_OF_NR_ULSCH_MAX 2//16
#define NUMBER_OF_NR_PUCCH_MAX 2
#define NUMBER_OF_NR_SR_MAX 16
openair2/GNB_APP/RRC_nr_paramsvalues.h
+5 -5
View File
@@ -128,11 +128,11 @@
#define GNB_CONFIG_STRING_RARESPONSEWINDOW "ra_ResponseWindow"
#define GNB_CONFIG_STRING_SSBPERRACHOCCASIONANDCBPREAMBLESPERSSBPR "ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR"
#define GNB_CONFIG_STRING_SSBPERRACHOCCASIONANDCBPREAMBLESPERSSB "ssb_perRACH_OccasionAndCB_PreamblesPerSSB"
#define GNB_CONFIG_STRING_RACONTENTIONRESOLUTIONTIMER "ra_ContentionResolutionTimer"
#define GNB_CONFIG_STRING_RSRPTHRESHOLDSSB "rsrp_ThresholdSSB"
#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR "prach_RootSequenceIndex_PR"
#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX "prach_RootSequenceIndex"
#define GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING "msg1_SubcarrierSpacing"
#define GNB_CONFIG_STRING_RACONTENTIONRESOLUTIONTIMER "ra_ContentionResolutionTimer"
#define GNB_CONFIG_STRING_RSRPTHRESHOLDSSB "rsrp_ThresholdSSB"
#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR "prach_RootSequenceIndex_PR"
#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX "prach_RootSequenceIndex"
#define GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING "msg1_SubcarrierSpacing"
#define GNB_CONFIG_STRING_RESTRICTEDSETCONFIG "restrictedSetConfig"
#define GNB_CONFIG_STRING_MSG3TRANSFPREC "msg3_transformPrecoder"
#define GNB_CONFIG_STRING_PUSCHTIMEDOMAINALLOCATIONLIST "puschTimeDomainAllocationList"
openair2/GNB_APP/gnb_app.c
+1
View File
@@ -131,6 +131,7 @@ void *gNB_app_task(void *args_p)
uint32_t gnb_nb = RC.nb_nr_inst;
uint32_t gnb_id_start = 0;
uint32_t gnb_id_end = gnb_id_start + gnb_nb;
uint32_t gnb_id;
MessageDef *msg_p = NULL;
const char *msg_name = NULL;
openair2/LAYER2/NR_MAC_COMMON/nr_mac.h
+64
View File
@@ -230,6 +230,70 @@ typedef struct {
uint8_t TCRNTI_2: 8; // octet 7 [7:0]
} __attribute__ ((__packed__)) NR_MAC_RAR;
// DCI pdu structures. Used by both gNB and UE.
typedef struct {
uint16_t val;
uint8_t nbits;
} dci_field_t;
typedef struct {
uint8_t format_indicator; //1 bit
uint8_t ra_preamble_index; //6 bits
uint8_t ss_pbch_index; //6 bits
uint8_t prach_mask_index; //4 bits
uint8_t mcs; //5 bits
uint8_t ndi; //1 bit
uint8_t rv; //2 bits
uint8_t harq_pid; //4 bits
uint8_t tpc; //2 bits
uint8_t short_messages_indicator; //2 bits
uint8_t short_messages; //8 bits
uint8_t tb_scaling; //2 bits
uint8_t pucch_resource_indicator; //3 bits
uint8_t dmrs_sequence_initialization; //1 bit
uint8_t system_info_indicator; //1 bit
uint8_t slot_format_indicator_count;
uint8_t *slot_format_indicators;
uint8_t pre_emption_indication_count;
uint16_t *pre_emption_indications; //14 bit each
uint8_t block_number_count;
uint8_t *block_numbers;
uint8_t padding;
dci_field_t mcs2; //variable
dci_field_t ndi2; //variable
dci_field_t rv2; //variable
dci_field_t frequency_domain_assignment; //variable
dci_field_t time_domain_assignment; //variable
dci_field_t frequency_hopping_flag; //variable
dci_field_t vrb_to_prb_mapping; //variable
dci_field_t dai[2]; //variable
dci_field_t pdsch_to_harq_feedback_timing_indicator; //variable
dci_field_t carrier_indicator; //variable
dci_field_t bwp_indicator; //variable
dci_field_t prb_bundling_size_indicator; //variable
dci_field_t rate_matching_indicator; //variable
dci_field_t zp_csi_rs_trigger; //variable
dci_field_t transmission_configuration_indication; //variable
dci_field_t srs_request; //variable
dci_field_t cbgti; //variable
dci_field_t cbgfi; //variable
dci_field_t srs_resource_indicator; //variable
dci_field_t precoding_information; //variable
dci_field_t csi_request; //variable
dci_field_t ptrs_dmrs_association; //variable
dci_field_t beta_offset_indicator; //variable
dci_field_t cloded_loop_indicator; //variable
dci_field_t ul_sul_indicator; //variable
dci_field_t antenna_ports; //variable
dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
} dci_pdu_rel15_t;
// 38.321 ch6.2.1, 38.331
#define DL_SCH_LCID_CCCH 0x00
#define DL_SCH_LCID_DCCH 0x01
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
+177 -27
View File
@@ -32,6 +32,8 @@
#include "LAYER2/NR_MAC_gNB/mac_proto.h"
const uint8_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160};
// Table 6.3.3.1-5 (38.211) NCS for preamble formats with delta_f_RA = 1.25 KHz
uint16_t NCS_unrestricted_delta_f_RA_125[16] = {0,13,15,18,22,26,32,38,46,59,76,93,119,167,279,419};
uint16_t NCS_restricted_TypeA_delta_f_RA_125[15] = {15,18,22,26,32,38,46,55,68,82,100,128,158,202,237}; // high-speed case set Type A
@@ -46,11 +48,13 @@ uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,8
uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69};
const char *prachfmt[]={"A1","A2","A3","B1","B2","B3","B4","C0","C2"};
const uint16_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160};
const char *prachfmt03[]={"0","1","2","3"};
uint16_t get_NCS(uint8_t index, uint16_t format0, uint8_t restricted_set_config) {
LOG_D(MAC,"get_NCS: indx %d,format0 %d, restriced_set_config %d\n",
index,format0,restricted_set_config);
if (format0 < 3) {
switch(restricted_set_config){
case 0:
@@ -975,7 +979,7 @@ int get_nr_prach_info_from_index(uint8_t index,
if ( (frame%x)==y || (frame%x)==y2 ) {
slot_60khz = slot >> (mu-2); // in table slots are numbered wrt 60kHz
s_map = table_6_3_3_2_4_prachConfig_Index[index][5];
if ( (s_map>>slot_60khz)&0x01 ) {
if ( ((s_map>>slot_60khz)&0x01) ) {
if (mu == 3) {
if ( (table_6_3_3_2_4_prachConfig_Index[index][7] == 1) && (slot%2 == 0) )
return 0; // no prach in even slots @ 120kHz for 1 prach per 60khz slot
@@ -1015,7 +1019,7 @@ int get_nr_prach_info_from_index(uint8_t index,
s_map = table_6_3_3_2_3_prachConfig_Index[index][4];
if ( (s_map>>subframe)&0x01 ) {
if (mu == 1) {
if ( (table_6_3_3_2_3_prachConfig_Index[index][6] == 1) && (slot%2 == 0) )
if ( (table_6_3_3_2_3_prachConfig_Index[index][6] <= 1) && (slot%2 == 0) )
return 0; // no prach in even slots @ 30kHz for 1 prach per subframe
}
if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){
@@ -1025,9 +1029,9 @@ int get_nr_prach_info_from_index(uint8_t index,
if (table_6_3_3_2_3_prachConfig_Index[index][1] != -1)
format2 = (uint8_t) table_6_3_3_2_3_prachConfig_Index[index][1];
*format = ((uint8_t) table_6_3_3_2_3_prachConfig_Index[index][0]) | (format2<<8);
LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame,
LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d (col 6 %ld) absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame,
slot,
index,
index, table_6_3_3_2_3_prachConfig_Index[index][6],
pointa,
mu,
unpaired,
@@ -1051,7 +1055,7 @@ int get_nr_prach_info_from_index(uint8_t index,
s_map = table_6_3_3_2_2_prachConfig_Index[index][4];
if ( (s_map>>subframe)&0x01 ) {
if (mu == 1) {
if ( (table_6_3_3_2_2_prachConfig_Index[index][6] == 1) && (slot%2 == 0) )
if ( (table_6_3_3_2_2_prachConfig_Index[index][6] <= 1) && (slot%2 == 0) )
return 0; // no prach in even slots @ 30kHz for 1 prach per subframe
}
if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){
@@ -1136,7 +1140,7 @@ uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config,
uint8_t ncs_index = rach_config->rach_ConfigGeneric.zeroCorrelationZoneConfig;
uint16_t format0 = get_format0(config_index, unpaired);
uint16_t NCS = get_NCS(ncs_index, format0, rach_config->restrictedSetConfig);
uint16_t L_ra = (rach_config->prach_RootSequenceIndex.present) ? 139 : 839;
uint16_t L_ra = (rach_config->prach_RootSequenceIndex.present==NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139) ? 139 : 839;
uint16_t r,u,index,q,d_u,n_shift_ra,n_shift_ra_bar,d_start;
uint32_t w;
uint8_t found_preambles = 0;
@@ -1532,7 +1536,7 @@ int32_t get_nr_uldl_offset(int nr_bandP)
void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
int x_overhead,
uint8_t nodata_dmrs,
uint8_t numdmrscdmgroupnodata,
uint8_t tb_scaling) {
LOG_D(MAC, "TBS calculation\n");
@@ -1540,10 +1544,14 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_rel15 = &pdsch_pdu->pdsch_pdu_rel15;
uint16_t N_PRB_oh = x_overhead;
uint8_t N_PRB_DMRS;
if (nodata_dmrs)
N_PRB_DMRS = 12;
else
N_PRB_DMRS = (pdsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1)?6:4; //This only works for antenna port 1000
if (pdsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1) {
// if no data in dmrs cdm group is 1 only even REs have no data
// if no data in dmrs cdm group is 2 both odd and even REs have no data
N_PRB_DMRS = numdmrscdmgroupnodata*6;
}
else {
N_PRB_DMRS = numdmrscdmgroupnodata*4;
}
uint8_t N_sh_symb = pdsch_rel15->NrOfSymbols;
uint8_t Imcs = pdsch_rel15->mcsIndex[0];
uint16_t N_RE_prime = NR_NB_SC_PER_RB*N_sh_symb - N_PRB_DMRS - N_PRB_oh;
@@ -1723,6 +1731,48 @@ int get_num_dmrs(uint16_t dmrs_mask ) {
return(num_dmrs);
}
// Table 5.1.2.2.1-1 38.214
uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) {
AssertFatal(bwp_size<276,"BWP Size > 275\n");
if (bwp_size < 37) return (rbg_size_config ? 4 : 2);
if (bwp_size < 73) return (rbg_size_config ? 8 : 4);
if (bwp_size < 145) return (rbg_size_config ? 16 : 8);
if (bwp_size < 276) return 16;
}
uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) {
uint8_t rbg_size = getRBGSize(bwp_size,rbg_size_config);
return (uint8_t)ceil((bwp_size+(bwp_start % rbg_size))/rbg_size);
}
uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) {
uint8_t nbitsA = 0;
uint8_t nbitsB = 0;
uint8_t type,length,nbits;
if (typeA != NULL) {
type = (typeA->choice.setup->dmrs_Type==NULL) ? 1:2;
length = (typeA->choice.setup->maxLength==NULL) ? 1:2;
nbitsA = type + length + 2;
if (typeB == NULL) return nbitsA;
}
if (typeB != NULL) {
type = (typeB->choice.setup->dmrs_Type==NULL) ? 1:2;
length = (typeB->choice.setup->maxLength==NULL) ? 1:2;
nbitsB = type + length + 2;
if (typeA == NULL) return nbitsB;
}
nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB;
return nbits;
}
/*******************************************************************
*
* NAME : get_l0_ul
@@ -1829,11 +1879,17 @@ uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB) {
return 1;
}
uint16_t nr_dci_size(nr_dci_format_t format,
uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup,
dci_pdu_rel15_t *dci_pdu,
nr_dci_format_t format,
nr_rnti_type_t rnti_type,
uint16_t N_RB) {
uint16_t N_RB,
int bwp_id) {
uint16_t size = 0;
NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1];
NR_PDSCH_Config_t *pdsch_config = bwp->bwp_Dedicated->pdsch_Config->choice.setup;
switch(format) {
/*Only sizes for 0_0 and 1_0 are correct at the moment*/
@@ -1841,7 +1897,7 @@ uint16_t nr_dci_size(nr_dci_format_t format,
/// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20
size += 20;
size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated
size += nr_dci_size(NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size
size += nr_dci_size(secondaryCellGroup,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, bwp_id) - size; // Padding to match 1_0 size
// UL/SUL indicator assumed to be 0
break;
@@ -1874,29 +1930,123 @@ uint16_t nr_dci_size(nr_dci_format_t format,
break;
case NR_DL_DCI_FORMAT_1_1:
// General note: 0 bits condition is ignored as default nbits is 0.
// Format identifier
size = 1;
// Carrier indicator
size += 1; // Format identifier
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) {
dci_pdu->carrier_indicator.nbits=3;
size += dci_pdu->carrier_indicator.nbits;
}
// BWP Indicator
uint8_t n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count;
if (n_dl_bwp < 2)
dci_pdu->bwp_indicator.nbits = n_dl_bwp;
else
dci_pdu->bwp_indicator.nbits = 2;
size += dci_pdu->bwp_indicator.nbits;
// Freq domain assignment
// Time domain assignment
// VRB to PRB mapping
long rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size;
uint16_t numRBG = getNRBG(NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
rbg_size_config);
if (pdsch_config->resourceAllocation == 0)
dci_pdu->frequency_domain_assignment.nbits = numRBG;
else if (pdsch_config->resourceAllocation == 1)
dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
else
dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1;
size += dci_pdu->frequency_domain_assignment.nbits;
// Time domain assignment (see table 5.1.2.1.1-1 in 38.214
int num_entries;
if (pdsch_config->pdsch_TimeDomainAllocationList==NULL) {
if (bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList==NULL)
num_entries = 16; // num of entries in default table
else
num_entries = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count;
}
else
num_entries = pdsch_config->pdsch_TimeDomainAllocationList->choice.setup->list.count;
dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries));
size += dci_pdu->time_domain_assignment.nbits;
// VRB to PRB mapping
if ((pdsch_config->resourceAllocation == 1) && (bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver != NULL)) {
dci_pdu->vrb_to_prb_mapping.nbits = 1;
size += dci_pdu->vrb_to_prb_mapping.nbits;
}
// PRB bundling size indicator
if (pdsch_config->prb_BundlingType.present == NR_PDSCH_Config__prb_BundlingType_PR_dynamicBundling) {
dci_pdu->prb_bundling_size_indicator.nbits = 1;
size += dci_pdu->prb_bundling_size_indicator.nbits;
}
// Rate matching indicator
NR_RateMatchPatternGroup_t *group1 = pdsch_config->rateMatchPatternGroup1;
NR_RateMatchPatternGroup_t *group2 = pdsch_config->rateMatchPatternGroup2;
if ((group1 != NULL) && (group2 != NULL))
dci_pdu->rate_matching_indicator.nbits = 2;
if ((group1 != NULL) != (group2 != NULL))
dci_pdu->rate_matching_indicator.nbits = 1;
size += dci_pdu->rate_matching_indicator.nbits;
// ZP CSI-RS trigger
/// TB1- MCS 5, NDI 1, RV 2
if (pdsch_config->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList != NULL) {
uint8_t nZP = pdsch_config->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count;
dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1));
}
size += dci_pdu->zp_csi_rs_trigger.nbits;
// TB1- MCS 5, NDI 1, RV 2
size += 8;
// TB2
size += 4 ; // HARQ PID
long *maxCWperDCI = pdsch_config->maxNrofCodeWordsScheduledByDCI;
if ((maxCWperDCI != NULL) && (*maxCWperDCI == 2)) {
size += 8;
}
// HARQ PID
size += 4;
// DAI
size += 2; // TPC PUCCH
size += 3; // PUCCH resource indicator
size += 3; // PDSCH to HARQ timing indicator
if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic) { // FIXME in case of more than one serving cell
dci_pdu->dai[0].nbits = 2;
size += dci_pdu->dai[0].nbits;
}
// TPC PUCCH
size += 2;
// PUCCH resource indicator
size += 3;
// PDSCH to HARQ timing indicator
uint8_t I = ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count;
dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits = (int)ceil(log2(I));
size += dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits;
// Antenna ports
NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeA;
NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeB;
dci_pdu->antenna_ports.nbits = getAntPortBitWidth(typeA,typeB);
size += dci_pdu->antenna_ports.nbits;
// Tx Config Indication
size += 2; // SRS request
long *isTciEnable = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[bwp_id-1]->tci_PresentInDCI;
if (isTciEnable != NULL) {
dci_pdu->transmission_configuration_indication.nbits = 3;
size += dci_pdu->transmission_configuration_indication.nbits;
}
// SRS request
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink==NULL)
dci_pdu->srs_request.nbits = 2;
else
dci_pdu->srs_request.nbits = 3;
size += dci_pdu->srs_request.nbits;
// CBGTI
// CBGFI
size += 1; // DMRS sequence init
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) {
uint8_t maxCBGperTB = (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2;
long *maxCWperDCI_rrc = pdsch_config->maxNrofCodeWordsScheduledByDCI;
uint8_t maxCW = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc;
dci_pdu->cbgti.nbits = maxCBGperTB * maxCW;
size += dci_pdu->cbgti.nbits;
// CBGFI
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->codeBlockGroupFlushIndicator) {
dci_pdu->cbgfi.nbits = 1;
size += dci_pdu->cbgfi.nbits;
}
}
// DMRS sequence init
size += 1;
break;
case NR_DL_DCI_FORMAT_2_0:
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h
+8 -2
View File
@@ -33,7 +33,8 @@
#define __LAYER2_NR_MAC_COMMON_H__
#include "NR_PDSCH-Config.h"
#include "NR_ServingCellConfigCommon.h"
#include "NR_CellGroupConfig.h"
#include "nr_mac.h"
typedef enum {
NR_DL_DCI_FORMAT_1_0 = 0,
@@ -76,7 +77,12 @@ int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP);
int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP);
uint16_t nr_dci_size(nr_dci_format_t format, nr_rnti_type_t rnti_type, uint16_t N_RB);
uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup,
dci_pdu_rel15_t *dci_pdu,
nr_dci_format_t format,
nr_rnti_type_t rnti_type,
uint16_t N_RB,
int bwp_id);
void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss,
uint16_t *slot_period,
openair2/LAYER2/NR_MAC_UE/config_ue.c
+11 -12
View File
@@ -333,7 +333,7 @@ int nr_rrc_mac_config_req_ue(
// NR_ServingCellConfigCommon_t *sccP,
// NR_MAC_CellGroupConfig_t *mac_cell_group_configP,
// NR_PhysicalCellGroupConfig_t *phy_cell_group_configP,
NR_SpCellConfig_t *spCell_ConfigP ){
NR_CellGroupConfig_t *cell_group_config ){
NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
@@ -344,18 +344,17 @@ int nr_rrc_mac_config_req_ue(
if(mibP != NULL){
mac->mib = mibP; // update by every reception
}
if(spCell_ConfigP != NULL ){
mac->servCellIndex = *spCell_ConfigP->servCellIndex;
if (spCell_ConfigP->reconfigurationWithSync) {
mac->rach_ConfigDedicated = spCell_ConfigP->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink;
mac->scc = spCell_ConfigP->reconfigurationWithSync->spCellConfigCommon;
config_common_ue(mac,module_id,cc_idP);
mac->crnti = spCell_ConfigP->reconfigurationWithSync->newUE_Identity;
LOG_I(MAC,"Configuring CRNTI %x\n",mac->crnti);
if(cell_group_config != NULL ){
mac->servCellIndex = *cell_group_config->spCellConfig->servCellIndex;
if (cell_group_config->spCellConfig->reconfigurationWithSync) {
mac->rach_ConfigDedicated = cell_group_config->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink;
mac->scc = cell_group_config->spCellConfig->reconfigurationWithSync->spCellConfigCommon;
config_common_ue(mac,module_id,cc_idP);
mac->crnti = cell_group_config->spCellConfig->reconfigurationWithSync->newUE_Identity;
LOG_I(MAC,"Configuring CRNTI %x\n",mac->crnti);
}
mac->scd = spCell_ConfigP->spCellConfigDedicated;
mac->scg = cell_group_config;
/*
if(mac_cell_group_configP != NULL){
openair2/LAYER2/NR_MAC_UE/mac_defs.h
+2 -2
View File
@@ -61,7 +61,7 @@
#include "NR_MIB.h"
#include "NR_MAC-CellGroupConfig.h"
#include "NR_PhysicalCellGroupConfig.h"
#include "NR_SpCellConfig.h"
#include "NR_CellGroupConfig.h"
#include "NR_ServingCellConfig.h"
@@ -155,7 +155,7 @@ typedef enum {
typedef struct {
NR_ServingCellConfigCommon_t *scc;
NR_ServingCellConfig_t *scd;
NR_CellGroupConfig_t *scg;
NR_RACH_ConfigDedicated_t *rach_ConfigDedicated;
int servCellIndex;
//// MAC config
openair2/LAYER2/NR_MAC_UE/mac_extern.h
+3 -1
View File
@@ -90,4 +90,6 @@ extern const int32_t table_38213_10_1_1_c2[5];
// for PUSCH from TS 38.214 subclause 6.1.2.1.1
extern uint8_t table_6_1_2_1_1_2_time_dom_res_alloc_A[16][3];
// for PDSCH from TS 38.214 subclause 5.1.2.1.1
extern uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A[16][3];
extern uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A[16][3];
extern dci_pdu_rel15_t *def_dci_pdu_rel15;
openair2/LAYER2/NR_MAC_UE/mac_proto.h
+3 -3
View File
@@ -72,7 +72,7 @@ int nr_rrc_mac_config_req_ue(
uint8_t gNB_index,
NR_MIB_t *mibP,
//NR_ServingCellConfigCommon_t *sccP,
NR_SpCellConfig_t *spCell_ConfigP);
NR_CellGroupConfig_t *cell_group_config);
/**\brief initialization NR UE MAC instance(s), total number of MAC instance based on NB_NR_UE_MAC_INST*/
NR_UE_MAC_INST_t * nr_l2_init_ue(NR_UE_RRC_INST_t* rrc_inst);
@@ -101,7 +101,7 @@ uint32_t ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP,
int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe);
int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format);
int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format);
int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_index,fapi_nr_dci_indication_pdu_t *dci);
uint32_t get_ssb_frame(uint32_t test);
@@ -161,7 +161,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
uint8_t dci_length,
uint16_t rnti,
uint64_t *dci_pdu,
nr_dci_pdu_rel15_t *nr_pdci_info_extracted);
dci_pdu_rel15_t *nr_pdci_info_extracted);
uint8_t
openair2/LAYER2/NR_MAC_UE/main_ue_nr.c
+1 -1
View File
@@ -52,7 +52,7 @@ NR_UE_MAC_INST_t * nr_l2_init_ue(NR_UE_RRC_INST_t* rrc_inst)
//init mac here
nr_ue_mac_inst = (NR_UE_MAC_INST_t *)calloc(sizeof(NR_UE_MAC_INST_t),NB_NR_UE_MAC_INST);
if (rrc_inst) {
nr_rrc_mac_config_req_ue(0,0,0,NULL,rrc_inst->cell_group_config->spCellConfig);
nr_rrc_mac_config_req_ue(0,0,0,NULL,rrc_inst->cell_group_config);
if (IS_SOFTMODEM_NOS1){
if (rlc_module_init(0) != 0) {
openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c
+1
View File
@@ -334,6 +334,7 @@ void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint
// - retrieve TBS
// - add mac_rrc_nr_data_req_ue, etc ...
// - add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator)
uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources,
module_id_t mod_id,
int CC_id,
openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
+9 -9
View File
@@ -46,6 +46,7 @@
#endif
#define LOG_DCI_PARM(a...) LOG_D(PHY,"\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_generate_ue_ul_dlsch_params_from_dci)" a)
dci_pdu_rel15_t *def_dci_pdu_rel15;
void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15) {
@@ -63,7 +64,8 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd
void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl_config, frame_t frame, int slot) {
NR_ServingCellConfig_t *scd = mac->scd;
def_dci_pdu_rel15 = calloc(1,sizeof(dci_pdu_rel15_t));
NR_BWP_Downlink_t *bwp;
NR_BWP_DownlinkCommon_t *bwp_Common;
NR_BWP_DownlinkDedicated_t *dl_bwp_Dedicated;
@@ -76,6 +78,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl
NR_ControlResourceSet_t *coreset;
fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15;
NR_ServingCellConfig_t *scd = mac->scg->spCellConfig->spCellConfigDedicated;
uint8_t bwp_id = 1;
int ss_id, sps;
@@ -167,7 +170,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl
AssertFatal(mac->scc != NULL, "scc is null\n");
scc = mac->scc;
rel15->dci_format = NR_DL_DCI_FORMAT_1_0;
rel15->dci_format = NR_DL_DCI_FORMAT_1_1;
// CoReSet configuration
coreset = mac->coreset[0][0];
@@ -219,9 +222,9 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl
rel15->BWPSize = NRRIV2BW(initialDownlinkBWP->genericParameters.locationAndBandwidth, 275);
rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, 275); // NRRIV2PRBOFFSET(initialDownlinkBWP->genericParameters.locationAndBandwidth, 275);
rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing;
rel15->dci_length = nr_dci_size(rel15->dci_format, NR_RNTI_RA, rel15->BWPSize);
rel15->dci_length = nr_dci_size(mac->scg,def_dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize,bwp_id);
for (int i = 0; i < sps; i++){
for (int i = 0; i < sps; i++) {
if ((monitoringSymbolsWithinSlot >> (sps - 1 - i)) & 1) {
rel15->coreset.StartSymbolIndex = i;
break;
@@ -240,7 +243,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl
rel15->BWPSize = NRRIV2BW(bwp_Common->genericParameters.locationAndBandwidth, 275);
rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, 275);
rel15->SubcarrierSpacing = bwp_Common->genericParameters.subcarrierSpacing;
rel15->dci_length = nr_dci_size(rel15->dci_format, NR_RNTI_C, rel15->BWPSize);
rel15->dci_length = nr_dci_size(mac->scg,def_dci_pdu_rel15,rel15->dci_format,NR_RNTI_C,rel15->BWPSize,bwp_id);
// get UE-specific search space
for (ss_id = 0; ss_id < FAPI_NR_MAX_SS_PER_CORESET && mac->SSpace[0][0][ss_id] != NULL; ss_id++){
uss = mac->SSpace[0][0][ss_id];
@@ -264,10 +267,7 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl
rel15->coreset.scrambling_rnti = mac->t_crnti;
} else {
rel15->coreset.pdcch_dmrs_scrambling_id = *scc->physCellId;
if(mac->ra_state == WAIT_RAR)
rel15->coreset.scrambling_rnti = 0;
else
rel15->coreset.scrambling_rnti = rel15->rnti;
rel15->coreset.scrambling_rnti = 0;
}
if (add_dci){
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
+330 -244
View File
File diff suppressed because it is too large Load Diff
openair2/LAYER2/NR_MAC_gNB/config.c
+7 -2
View File
@@ -290,8 +290,7 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots,
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols,
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots,
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols
);
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols);
if (return_tdd !=0){
LOG_E(PHY,"TDD configuration can not be done\n");
@@ -374,6 +373,12 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
if (add_ue == 1) {
UE_id = add_new_nr_ue(Mod_idP,rnti);
UE_list->secondaryCellGroup[UE_id] = secondaryCellGroup;
uint8_t num_preamble = secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list.count;
UE_list->preambles[UE_id].num_preambles = num_preamble;
UE_list->preambles[UE_id].preamble_list = (uint8_t *) malloc(num_preamble*sizeof(uint8_t));
for (int i=0; i<num_preamble; i++) {
UE_list->preambles[UE_id].preamble_list[i] = secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list.array[i]->ra_PreambleIndex;
}
LOG_I(PHY,"Added new UE_id %d/%x with initial secondaryCellGroup\n",UE_id,rnti);
}
else { // secondaryCellGroup has been updated
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+78 -29
View File
@@ -59,6 +59,7 @@
#include "executables/softmodem-common.h"
const uint8_t slots_per_frame[5] = {10, 20, 40, 80, 160};
uint16_t nr_pdcch_order_table[6] = { 31, 31, 511, 2047, 2047, 8191 };
void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
@@ -304,12 +305,14 @@ void nr_schedule_pucch(int Mod_idP,
NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1];
nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0];
NR_sched_pucch *curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch;
NR_sched_pucch *temp_pucch;
int release_pucch = 0;
NR_sched_pucch *curr_pucch;
int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots;
if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0)
nr_ulmix_slots++;
if (curr_pucch != NULL) {
if ((frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) {
for (int k=0; k<nr_ulmix_slots; k++) {
curr_pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k];
if ((curr_pucch->dai_c > 0) && (frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) {
UL_tti_req->SFN = frameP;
UL_tti_req->Slot = slotP;
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE;
@@ -320,6 +323,8 @@ void nr_schedule_pucch(int Mod_idP,
O_ack = curr_pucch->dai_c;
O_uci = O_ack; // for now we are just sending acknacks in pucch
LOG_I(MAC, "Scheduling pucch reception for frame %d slot %d\n", frameP, slotP);
nr_configure_pucch(pucch_pdu,
scc,
ubwp,
@@ -328,16 +333,9 @@ void nr_schedule_pucch(int Mod_idP,
O_ack,
SR_flag);
release_pucch = 1;
curr_pucch->dai_c = 0;
}
}
if (release_pucch) {
temp_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch;
UE_list->UE_sched_ctrl[UE_id].sched_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch->next_sched_pucch;
free(temp_pucch);
}
}
bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot){
@@ -358,11 +356,34 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
protocol_ctxt_t ctxt;
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frame_txP, slot_txP,module_idP);
int CC_id, UE_id = 0;
int CC_id;
int UE_id;
uint64_t *dlsch_in_slot_bitmap=NULL;
uint64_t *ulsch_in_slot_bitmap=NULL;
int pucch_sched;
UE_id=0;
int bwp_id = 1;
gNB_MAC_INST *gNB = RC.nrmac[module_idP];
NR_UE_list_t *UE_list = &gNB->UE_list;
NR_UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
NR_COMMON_channels_t *cc = gNB->common_channels;
NR_sched_pucch *pucch_sched = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch));
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
int num_slots_per_tdd = (slots_per_frame[*scc->ssbSubcarrierSpacing])>>(7-scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity);
int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots;
if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0)
nr_ulmix_slots++;
if (slot_txP== 0 && (UE_list->fiveG_connected[UE_id] || get_softmodem_params()->phy_test)) {
for (int k=0; k<nr_ulmix_slots; k++) {
memset((void *) &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k],
0,
sizeof(NR_sched_pucch));
}
}
start_meas(&RC.nrmac[module_idP]->eNB_scheduler);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN);
@@ -373,10 +394,29 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
RC.nrmac[module_idP]->frame = frame_rxP;
RC.nrmac[module_idP]->slot = slot_rxP;
dlsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch
ulsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch
// hardcoding dlsch to be in slot 1
if (!(slot_txP%num_slots_per_tdd)) {
if(slot_txP==0)
*dlsch_in_slot_bitmap = 0x02;
else
*dlsch_in_slot_bitmap = 0x00;
}
// hardcoding ulsch to be in slot 8
if (!(slot_rxP%num_slots_per_tdd)) {
if(slot_rxP==0)
*ulsch_in_slot_bitmap = 0x100;
else
*ulsch_in_slot_bitmap = 0x00;
}
// Check if there are downlink symbols in the slot,
if (is_nr_DL_slot(cc->ServingCellConfigCommon,slot_txP)) {
memset(RC.nrmac[module_idP]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int));
memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1
for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
//mbsfn_status[CC_id] = 0;
@@ -392,7 +432,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
for (i = 0; i < MAX_MOBILES_PER_GNB; i++) {
if (UE_list->active[i]) {
nfapi_nr_config_request_t *cfg = &RC.nrmac[module_idP]->config[CC_id];
nfapi_nr_config_request_t *cfg = &RC.nrmac[module_idP]->config[CC_id];
rnti = 0;//UE_RNTI(module_idP, i);
CC_id = 0;//UE_PCCID(module_idP, i);
@@ -406,9 +446,14 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
schedule_nr_mib(module_idP, frame_txP, slot_txP);
}
if (get_softmodem_params()->phy_test == 0)
nr_schedule_RA(module_idP, frame_txP, slot_txP);
else
UE_list->fiveG_connected[UE_id] = true;
// Phytest scheduling
if (get_softmodem_params()->phy_test) {
NR_UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
// TbD once RACH is available, start ta_timer when UE is connected
if (ue_sched_ctl->ta_timer)
@@ -424,16 +469,15 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
/* MAC CE flag indicating TA length */
gNB->ta_len = 2;
}
if (slot_txP == 1){
nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL);
// resetting ta flag
gNB->ta_len = 0;
}
}
if (get_softmodem_params()->phy_test == 0)
nr_schedule_RA(module_idP, frame_txP, slot_txP);
if (UE_list->fiveG_connected[UE_id] && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) {
ue_sched_ctl->current_harq_pid = slot_txP % num_slots_per_tdd;
nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched);
nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL);
// resetting ta flag
gNB->ta_len = 0;
}
/*
// Allocate CCEs for good after scheduling is done
@@ -446,11 +490,16 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) {
if (get_softmodem_params()->phy_test == 0) {
if (UE_list->fiveG_connected[UE_id])
nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP);
schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP);
nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP);
}
if (get_softmodem_params()->phy_test && slot_rxP==8){
nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP);
if (get_softmodem_params()->phy_test){
nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP);
if (is_xlsch_in_slot(*ulsch_in_slot_bitmap,slot_rxP%num_slots_per_tdd)){
nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP);
}
}
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+44 -42
View File
@@ -42,7 +42,9 @@
#include "SIMULATION/TOOLS/sim.h" // for taus
extern RAN_CONTEXT_t RC;
extern const uint16_t nr_slots_per_frame[5];
const uint8_t nr_slots_per_frame_mac[5] = {10, 20, 40, 80, 160};
uint8_t DELTA[4]= {2,3,4,6};
void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) {
@@ -183,7 +185,7 @@ void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot,
tdd_period_slot++;
// computing start of next period
uint8_t start_next_period = (rach_slot-(rach_slot%tdd_period_slot)+tdd_period_slot)%nr_slots_per_frame[mu];
uint8_t start_next_period = (rach_slot-(rach_slot%tdd_period_slot)+tdd_period_slot)%nr_slots_per_frame_mac[mu];
*msg2_slot = start_next_period + last_dl_slot_period; // initializing scheduling of slot to next mixed (or last dl) slot
*msg2_frame = (*msg2_slot>(rach_slot))? rach_frame : (rach_frame +1);
@@ -215,15 +217,16 @@ void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot,
default:
AssertFatal(1==0,"Invalid response window value %d\n",response_window);
}
AssertFatal(slot_window<=nr_slots_per_frame[mu],"Msg2 response window needs to be lower or equal to 10ms");
AssertFatal(slot_window<=nr_slots_per_frame_mac[mu],"Msg2 response window needs to be lower or equal to 10ms");
// slot and frame limit to transmit msg2 according to response window
uint8_t slot_limit = (rach_slot + slot_window)%nr_slots_per_frame[mu];
uint8_t slot_limit = (rach_slot + slot_window)%nr_slots_per_frame_mac[mu];
//uint8_t frame_limit = (slot_limit>(rach_slot))? rach_frame : (rach_frame +1);
// go to previous slot if the current scheduled slot is beyond the response window
// and if the slot is not among the PDCCH monitored ones (38.213 10.1)
while ((*msg2_slot>slot_limit) || ((*msg2_frame*nr_slots_per_frame[mu]+*msg2_slot-monitoring_offset)%monitoring_slot_period !=0)) {
while ((*msg2_slot>slot_limit) || ((*msg2_frame*nr_slots_per_frame_mac[mu]+*msg2_slot-monitoring_offset)%monitoring_slot_period !=0)) {
if((*msg2_slot%tdd_period_slot) > 0)
(*msg2_slot)--;
else
@@ -243,18 +246,35 @@ void nr_initiate_ra_proc(module_id_t module_idP,
uint8_t ul_carrier_id = 0; // 0 for NUL 1 for SUL
NR_SearchSpace_t *ss;
int UE_id = 0;
// ra_rnti from 5.1.3 in 38.321
uint16_t ra_rnti=1+symbol+(slotP*14)+(freq_index*14*80)+(ul_carrier_id*14*80*8);
uint16_t msg2_frame, msg2_slot,monitoring_slot_period,monitoring_offset;
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
NR_UE_list_t *UE_list = &nr_mac->UE_list;
NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[0];
NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
NR_RA_t *ra = &cc->ra[0];
// if the preamble received correspond to one of the listed
// the UE sent a RACH either for starting RA procedure or RA procedure failed and UE retries
int pr_found=0;
for (int i=0;i<UE_list->preambles[UE_id].num_preambles;i++) {
if (preamble_index == UE_list->preambles[UE_id].preamble_list[i]) {
pr_found=1;
break;
}
}
if (pr_found)
UE_list->fiveG_connected[UE_id] = false;
else {
LOG_E(MAC, "[gNB %d][RAPROC] FAILURE: preamble %d does not correspond to any of the ones in rach_ConfigDedicated for UE_id %d\n",
module_idP, preamble_index, UE_id);
return; // if the PRACH preamble does not correspond to any of the ones sent through RRC abort RA proc
}
// This should be handled differently when we use the initialBWP for RA
ra->bwp_id=1;
NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id-1];
@@ -304,7 +324,7 @@ void nr_initiate_ra_proc(module_id_t module_idP,
ra->RA_rnti = ra_rnti;
ra->preamble_index = preamble_index;
UE_list->tc_rnti[UE_id] = ra->rnti;
LOG_I(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d using RA rnti %x\n",
module_idP,
@@ -377,11 +397,11 @@ void nr_get_Msg3alloc(NR_ServingCellConfigCommon_t *scc,
uint8_t k2 = *ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->k2;
temp_slot = current_slot + k2 + DELTA[mu]; // msg3 slot according to 8.3 in 38.213
ra->Msg3_slot = temp_slot%nr_slots_per_frame[mu];
if (nr_slots_per_frame[mu]>temp_slot)
ra->Msg3_slot = temp_slot%nr_slots_per_frame_mac[mu];
if (nr_slots_per_frame_mac[mu]>temp_slot)
ra->Msg3_frame = current_frame;
else
ra->Msg3_frame = current_frame + (temp_slot/nr_slots_per_frame[mu]);
ra->Msg3_frame = current_frame + (temp_slot/nr_slots_per_frame_mac[mu]);
ra->msg3_nb_rb = 18;
ra->msg3_first_rb = 0;
@@ -402,6 +422,7 @@ void nr_schedule_reception_msg3(module_id_t module_idP, int CC_id, frame_t frame
ul_req->pdus_list[ul_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
ul_req->pdus_list[ul_req->n_pdus].pusch_pdu = ra->pusch_pdu;
ul_req->n_pdus+=1;
ra->state = RA_IDLE;
}
}
}
@@ -517,16 +538,15 @@ void nr_generate_Msg2(module_id_t module_idP,
frame_t frameP,
sub_frame_t slotP){
int UE_id = 0, dci_formats[2], rnti_types[2], CCEIndex, mcsIndex;
int UE_id = 0, dci_formats[2], rnti_types[2], mcsIndex;
int startSymbolAndLength = 0, StartSymbolIndex = -1, NrOfSymbols = 14, StartSymbolIndex_tmp, NrOfSymbols_tmp, x_Overhead, time_domain_assignment;
int coreset_id, aggregation , search_space_type = 0;
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
NR_COMMON_channels_t *cc = &nr_mac->common_channels[0];
NR_RA_t *ra = &cc->ra[0];
NR_UE_list_t *UE_list = &nr_mac->UE_list;
NR_SearchSpace_t *ss = ra->ra_ss;
uint16_t RA_rnti = ra->RA_rnti, numDlDci;
uint16_t RA_rnti = ra->RA_rnti;
long locationAndBandwidth;
// uint8_t *vrb_map = cc[CC_id].vrb_map, CC_id;
@@ -561,20 +581,11 @@ void nr_generate_Msg2(module_id_t module_idP,
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15;
nfapi_nr_dl_dci_pdu_t *dci_pdu = &pdcch_pdu_rel15->dci_pdu;
numDlDci = pdcch_pdu_rel15->numDlDci;
aggregation = find_aggregation_level(ss);
coreset_id = *ss->controlResourceSetId;
// Checking if the DCI allocation is feasible in current subframe
if (dl_req->nPDUs == NFAPI_NR_MAX_DL_TTI_PDUS) {
LOG_I(MAC, "[RAPROC] Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", slotP, RA_rnti);
return;
} else {
LOG_D(MAC, "[RAPROC] Subframe %d: Checking CCE feasibility format : (%x,%d) \n", slotP, RA_rnti, aggregation);
CCEIndex = allocate_nr_CCEs(nr_mac, ra->bwp_id, coreset_id, aggregation, search_space_type, UE_id, 0);
AssertFatal(CCEIndex >= 0,"CCEIndex is negative %d\n",CCEIndex);
}
LOG_I(MAC,"[gNB %d] [RAPROC] CC_id %d Frame %d, slotP %d: Generating RAR DCI, state %d\n", module_idP, CC_id, frameP, slotP, ra->state);
@@ -649,34 +660,27 @@ void nr_generate_Msg2(module_id_t module_idP,
pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(NULL, scc->dmrs_TypeA_Position, NrOfSymbols);
dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
pdsch_pdu_rel15->rbStart,dci10_bw);
dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment;
dci_pdu_rel15[0].vrb_to_prb_mapping = 0;
dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment;
dci_pdu_rel15[0].vrb_to_prb_mapping.val = 0;
dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0];
dci_pdu_rel15[0].tb_scaling = 0;
LOG_I(MAC, "[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d \n",
dci_pdu_rel15[0].frequency_domain_assignment,
dci_pdu_rel15[0].frequency_domain_assignment.val,
pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize,
dci10_bw,
dci_pdu_rel15[0].time_domain_assignment,
dci_pdu_rel15[0].vrb_to_prb_mapping,
dci_pdu_rel15[0].time_domain_assignment.val,
dci_pdu_rel15[0].vrb_to_prb_mapping.val,
dci_pdu_rel15[0].mcs,
dci_pdu_rel15[0].tb_scaling);
nr_configure_pdcch(pdcch_pdu_rel15, 0, ss, scc, bwp);
nr_configure_pdcch(nr_mac, pdcch_pdu_rel15, RA_rnti, 0, ss, scc, bwp);
LOG_I(MAC, "Frame %d: Subframe %d : Adding common DL DCI for RA_RNTI %x CCEIndex %d\n", frameP, slotP, RA_rnti, CCEIndex);
LOG_I(MAC, "Frame %d: Subframe %d : Adding common DL DCI for RA_RNTI %x\n", frameP, slotP, RA_rnti);
dci_pdu->RNTI[numDlDci] = RA_rnti;
dci_pdu->ScramblingId[numDlDci] = *scc->physCellId;
dci_pdu->ScramblingRNTI[numDlDci] = 0;
dci_pdu->AggregationLevel[numDlDci] = aggregation;
dci_pdu->CceIndex[numDlDci] = CCEIndex;
dci_pdu->beta_PDCCH_1_0[numDlDci] = 0;
dci_pdu->powerControlOffsetSS[numDlDci] = 1;
dci_formats[0] = NR_DL_DCI_FORMAT_1_0;
rnti_types[0] = NR_RNTI_RA;
@@ -688,9 +692,7 @@ void nr_generate_Msg2(module_id_t module_idP,
pdcch_pdu_rel15->StartSymbolIndex,
pdcch_pdu_rel15->DurationSymbols);
pdcch_pdu_rel15->numDlDci++;
dci_pdu->PayloadSizeBits[0] = nr_dci_size(dci_formats[0], rnti_types[0], dci10_bw);
fill_dci_pdu_rel15(pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types,dci10_bw);
fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types,dci10_bw,ra->bwp_id);
dl_req->nPDUs+=2;
@@ -702,7 +704,7 @@ void nr_generate_Msg2(module_id_t module_idP,
LOG_D(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state);
x_Overhead = 0;
nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, 1, dci_pdu_rel15[0].tb_scaling);
nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, pdsch_pdu_rel15->numDmrsCdmGrpsNoData, dci_pdu_rel15[0].tb_scaling);
// DL TX request
tx_req->PDU_length = pdsch_pdu_rel15->TBSize[0];
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+149 -100
View File
@@ -250,11 +250,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
}
int configure_fapi_dl_pdu(int Mod_idP,
int *CCEIndex,
nfapi_nr_dl_tti_request_body_t *dl_req,
NR_sched_pucch *pucch_sched,
uint8_t *mcsIndex,
@@ -262,13 +258,18 @@ int configure_fapi_dl_pdu(int Mod_idP,
uint16_t *rbStart) {
gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP];
NR_COMMON_channels_t *cc = nr_mac->common_channels;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu;
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu;
int TBS, bwp_id = 1, UE_id = 0;
int TBS;
int bwp_id=1;
int UE_id = 0;
NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
@@ -280,10 +281,6 @@ int configure_fapi_dl_pdu(int Mod_idP,
AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n");
AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0,
"searchPsacesToAddModList is empty\n");
NR_SearchSpace_t *ss;
// TO BE FIXED we are just selecting the first search space here (only one is configured)
ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[0];
dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
@@ -312,11 +309,12 @@ int configure_fapi_dl_pdu(int Mod_idP,
pdsch_pdu_rel15->NrOfCodewords = 1;
int mcs = (mcsIndex!=NULL) ? *mcsIndex : 9;
int current_harq_pid = UE_list->UE_sched_ctrl[UE_id].current_harq_pid;
pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcs,0);
pdsch_pdu_rel15->qamModOrder[0] = 2;
pdsch_pdu_rel15->mcsIndex[0] = mcs;
pdsch_pdu_rel15->mcsTable[0] = 0;
pdsch_pdu_rel15->rvIndex[0] = 0;
pdsch_pdu_rel15->rvIndex[0] = (get_softmodem_params()->phy_test==1) ? 0 : UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].round;
pdsch_pdu_rel15->dataScramblingId = *scc->physCellId;
pdsch_pdu_rel15->nrOfLayers = 1;
pdsch_pdu_rel15->transmissionScheme = 0;
@@ -347,52 +345,87 @@ int configure_fapi_dl_pdu(int Mod_idP,
scc->dmrs_TypeA_Position,
pdsch_pdu_rel15->NrOfSymbols);
dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15_t));
dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
pdsch_pdu_rel15->rbStart,
NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275));
dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; // row index used here instead of SLIV;
dci_pdu_rel15[0].vrb_to_prb_mapping = 1;
// bwp indicator
int n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count;
if (n_dl_bwp < 4)
dci_pdu_rel15[0].bwp_indicator.val = bwp_id;
else
dci_pdu_rel15[0].bwp_indicator.val = bwp_id - 1; // as per table 7.3.1.1.2-1 in 38.212
// frequency domain assignment
if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation==NR_PDSCH_Config__resourceAllocation_resourceAllocationType1)
dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
pdsch_pdu_rel15->rbStart,
NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275));
else
AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n");
// time domain assignment
dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV;
// mcs ndi and rv
dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0];
dci_pdu_rel15[0].tb_scaling = 1;
dci_pdu_rel15[0].ra_preamble_index = 25;
dci_pdu_rel15[0].format_indicator = 1;
dci_pdu_rel15[0].ndi = 1;
dci_pdu_rel15[0].rv = 0;
dci_pdu_rel15[0].harq_pid = 0;
dci_pdu_rel15[0].dai = (pucch_sched->dai_c-1)&3;
dci_pdu_rel15[0].tpc = 2;
dci_pdu_rel15[0].rv = pdsch_pdu_rel15->rvIndex[0];
// harq pid
dci_pdu_rel15[0].harq_pid = current_harq_pid;
dci_pdu_rel15[0].ndi = UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].ndi;
// DAI
dci_pdu_rel15[0].dai[0].val = (pucch_sched->dai_c-1)&3;
// TPC for PUCCH
dci_pdu_rel15[0].tpc = 1; // table 7.2.1-1 in 38.213
// PUCCH resource indicator
dci_pdu_rel15[0].pucch_resource_indicator = pucch_sched->resource_indicator;
dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = pucch_sched->timing_indicator;
// PDSCH to HARQ TI
dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = pucch_sched->timing_indicator;
UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].feedback_slot = pucch_sched->ul_slot;
UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].is_waiting = 1;
// antenna ports
dci_pdu_rel15[0].antenna_ports.val = 0; // nb of cdm groups w/o data 1 and dmrs port 0
LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
dci_pdu_rel15[0].frequency_domain_assignment,
dci_pdu_rel15[0].frequency_domain_assignment.val,
pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize,
NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
dci_pdu_rel15[0].time_domain_assignment,
dci_pdu_rel15[0].vrb_to_prb_mapping,
dci_pdu_rel15[0].time_domain_assignment.val,
dci_pdu_rel15[0].vrb_to_prb_mapping.val,
dci_pdu_rel15[0].mcs,
dci_pdu_rel15[0].tb_scaling,
dci_pdu_rel15[0].ndi,
dci_pdu_rel15[0].rv);
nr_configure_pdcch(pdcch_pdu_rel15,
1, // ue-specific
ss,
scc,
bwp);
pdcch_pdu_rel15->numDlDci = 1;
pdcch_pdu_rel15->dci_pdu.AggregationLevel[0] = 4;
pdcch_pdu_rel15->dci_pdu.RNTI[0]=UE_list->rnti[0];
pdcch_pdu_rel15->dci_pdu.ScramblingRNTI[0]=UE_list->rnti[0];
pdcch_pdu_rel15->dci_pdu.CceIndex[0] = CCEIndex[0];
pdcch_pdu_rel15->dci_pdu.beta_PDCCH_1_0[0]=0;
pdcch_pdu_rel15->dci_pdu.powerControlOffsetSS[0]=1;
NR_SearchSpace_t *ss;
int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n");
AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0,
"searchPsacesToAddModList is empty\n");
int found=0;
for (int i=0;i<bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) {
ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i];
AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n");
AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n");
if (ss->searchSpaceType->present == target_ss) {
found=1;
break;
}
}
AssertFatal(found==1,"Couldn't find an adequate searchspace\n");
int ret = nr_configure_pdcch(nr_mac,
pdcch_pdu_rel15,
UE_list->rnti[UE_id],
1, // ue-specific
ss,
scc,
bwp);
if (ret < 0) {
LOG_I(MAC,"CCE list not empty, couldn't schedule PDSCH\n");
return (0);
}
int dci_formats[2];
int rnti_types[2];
@@ -403,8 +436,7 @@ int configure_fapi_dl_pdu(int Mod_idP,
rnti_types[0] = NR_RNTI_C;
pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,pdcch_pdu_rel15->BWPSize);
fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pdsch_pdu_rel15->BWPSize,bwp_id);
LOG_D(MAC, "DCI params: rnti %x, rnti_type %d, dci_format %d\n \
coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
@@ -416,7 +448,7 @@ int configure_fapi_dl_pdu(int Mod_idP,
pdcch_pdu_rel15->DurationSymbols);
int x_Overhead = 0; // should be 0 for initialBWP
nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead,1,0);
nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu,x_Overhead,pdsch_pdu_rel15->numDmrsCdmGrpsNoData,0);
// Hardcode it for now
TBS = dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0];
@@ -430,17 +462,18 @@ int configure_fapi_dl_pdu(int Mod_idP,
pdsch_pdu_rel15->NrOfCodewords,
pdsch_pdu_rel15->mcsIndex[0],
TBS);
return TBS; //Return TBS in bytes
}
void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) {
dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
pusch_pdu->rb_start,
NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275));
dci_pdu_rel15->time_domain_assignment = 2; // row index used here instead of SLIV;
dci_pdu_rel15->frequency_hopping_flag = 0;
dci_pdu_rel15->time_domain_assignment.val = 2; // row index used here instead of SLIV;
dci_pdu_rel15->frequency_hopping_flag.val = 0;
dci_pdu_rel15->mcs = 9;
dci_pdu_rel15->format_indicator = 0;
@@ -451,9 +484,9 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr
LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci],
dci_pdu_rel15->frequency_domain_assignment,
dci_pdu_rel15->time_domain_assignment,
dci_pdu_rel15->frequency_hopping_flag,
dci_pdu_rel15->frequency_domain_assignment.val,
dci_pdu_rel15->time_domain_assignment.val,
dci_pdu_rel15->frequency_hopping_flag.val,
dci_pdu_rel15->mcs,
dci_pdu_rel15->tpc,
dci_pdu_rel15->ndi,
@@ -510,11 +543,11 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
NR_sched_pucch *pucch_sched,
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *dlsch_config){
LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest \n");
LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest frame %d slot %d\n",frameP,slotP);
int post_padding = 0, ta_len = 0, header_length_total = 0, sdu_length_total = 0, num_sdus = 0;
int lcid, offset, i, header_length_last, TBS_bytes;
int UE_id = 0, CCEIndex = -1, CC_id = 0;
int UE_id = 0, CC_id = 0;
gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP];
//NR_COMMON_channels_t *cc = nr_mac->common_channels;
@@ -538,25 +571,15 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
ta_len = gNB_mac->ta_len;
CCEIndex = allocate_nr_CCEs(gNB_mac,
1, // bwp_id
0, // coreset_id
4, // aggregation,
1, // search_space, 0 common, 1 ue-specific
UE_id,
0); // m
AssertFatal(CCEIndex>0,"CCEIndex is negative\n");
int CCEIndices[2];
CCEIndices[0] = CCEIndex;
TBS_bytes = configure_fapi_dl_pdu(module_idP,
CCEIndices,
dl_req,
pucch_sched,
dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL,
dlsch_config!=NULL ? &dlsch_config->rbSize : NULL,
dlsch_config!=NULL ? &dlsch_config->rbStart : NULL);
if (TBS_bytes == 0)
return;
//The --NOS1 use case currently schedules DLSCH transmissions only when there is IP traffic arriving
//through the LTE stack
@@ -614,11 +637,13 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
break;
}
}
} //if (IS_SOFTMODEM_NOS1)
else {
//When the --NOS1 option is not enabled, DLSCH transmissions with random data
//occur every time that the current function is called (dlsch phytest mode)
LOG_D(MAC,"Configuring DL_TX in %d.%d\n", frameP, slotP);
// fill dlsch_buffer with random data
@@ -628,7 +653,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
}
//Sending SDUs with size 1
//Initialize elements of sdu_lcids and sdu_lengths
sdu_lcids[0] = 0x05; // DRB
sdu_lcids[0] = 0x3f; // DRB
sdu_lengths[0] = TBS_bytes - ta_len - 3;
header_length_total += 2 + (sdu_lengths[0] >= 128);
sdu_length_total += sdu_lengths[0];
@@ -728,9 +753,6 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n");
AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0,
"searchPsacesToAddModList is empty\n");
NR_SearchSpace_t *ss;
// TO BE FIXED we are just selecting the first search space here (only one is configured)
ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[0];
uint16_t rnti = UE_list->rnti[UE_id];
nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu;
@@ -776,6 +798,8 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
pusch_pdu->transform_precoding = 0;
pusch_pdu->data_scrambling_id = 0; //It equals the higher-layer parameter Data-scrambling-Identity if configured and the RNTI equals the C-RNTI, otherwise L2 needs to set it to physical cell id.;
pusch_pdu->nrOfLayers = 1;
//Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2]
pusch_pdu->resource_alloc = 1; //type 1
//pusch_pdu->rb_bitmap;// for ressource alloc type 0
pusch_pdu->rb_start = 0;
@@ -797,7 +821,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
pusch_pdu->ul_dmrs_scrambling_id = 0; // If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id
pusch_pdu->scid = 0; // DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]
// Should match what is sent in DCI 0_1, otherwise set to 0
//pusch_pdu->num_dmrs_cdm_grps_no_data;
pusch_pdu->num_dmrs_cdm_grps_no_data = 1;
//pusch_pdu->dmrs_ports; // DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports
// Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011,
// and for each bit 0: DMRS port not used 1: DMRS port used
@@ -826,21 +850,29 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
pusch_pdu->pusch_data.harq_process_id = 0;
pusch_pdu->pusch_data.new_data_indicator = 0;
uint8_t no_data_in_dmrs = 1; // temp implementation
uint8_t num_dmrs_symb = 0;
for(int dmrs_counter = pusch_pdu->start_symbol_index; dmrs_counter < pusch_pdu->start_symbol_index + pusch_pdu->nr_of_symbols; dmrs_counter++)
num_dmrs_symb += ((pusch_pdu->ul_dmrs_symb_pos >> dmrs_counter) & 1);
uint8_t N_PRB_DMRS;
if (pusch_pdu->dmrs_config_type == 0) {
N_PRB_DMRS = pusch_pdu->num_dmrs_cdm_grps_no_data*6;
}
else {
N_PRB_DMRS = pusch_pdu->num_dmrs_cdm_grps_no_data*4;
}
pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->qam_mod_order,
pusch_pdu->target_code_rate,
pusch_pdu->rb_size,
pusch_pdu->nr_of_symbols,
( no_data_in_dmrs ? 12 : ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1) ? 6 : 4) ) * num_dmrs_symb,
N_PRB_DMRS * num_dmrs_symb,
0, //nb_rb_oh
0,
pusch_pdu->nrOfLayers)>>3;
pusch_pdu->pusch_data.num_cb = 0; //CBG not supported
//pusch_pdu->pusch_data.cb_present_and_position;
//pusch_pdu->pusch_uci;
@@ -859,34 +891,51 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
int dci_formats[2];
int rnti_types[2];
int CCEIndex = allocate_nr_CCEs(nr_mac,
1, // bwp_id
0, // coreset_id
4, // aggregation,
1, // search_space, 0 common, 1 ue-specific
UE_id,
0); // m
NR_SearchSpace_t *ss;
int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n");
AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0,
"searchPsacesToAddModList is empty\n");
int found=0;
for (int i=0;i<bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) {
ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i];
AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n");
AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n");
if (ss->searchSpaceType->present == target_ss) {
found=1;
break;
}
}
AssertFatal(found==1,"Couldn't find an adequate searchspace\n");
if (ss->searchSpaceType->choice.ue_Specific->dci_Formats)
dci_formats[0] = NR_UL_DCI_FORMAT_0_1;
else
dci_formats[0] = NR_UL_DCI_FORMAT_0_0;
dci_formats[0] = NR_UL_DCI_FORMAT_0_0;
rnti_types[0] = NR_RNTI_C;
LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP);
nr_configure_pdcch(pdcch_pdu_rel15,
1, // ue-specific,
ss,
scc,
bwp);
dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
AssertFatal(CCEIndex>=0,"CCEIndex is negative \n");
pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex;
int ret = nr_configure_pdcch(nr_mac,
pdcch_pdu_rel15,
UE_list->rnti[UE_id],
1, // ue-specific,
ss,
scc,
bwp);
LOG_D(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci]);
config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,pdcch_pdu_rel15->BWPSize);
if (ret < 0) {
LOG_I(MAC,"CCE list not empty, couldn't schedule PUSCH\n");
UL_tti_req->n_pdus-=1;
return;
}
else {
dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,bwp_id);
}
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+337 -187
View File
@@ -129,29 +129,9 @@ static inline uint8_t get_max_cces(uint8_t scs) {
return (nr_max_number_of_cces_per_slot[scs]);
}
int find_aggregation_level (NR_SearchSpace_t *ss){
int level = 0;
if( ss->nrofCandidates->aggregationLevel1 != NR_SearchSpace__nrofCandidates__aggregationLevel1_n0)
level = 1;
if( ss->nrofCandidates->aggregationLevel2 != NR_SearchSpace__nrofCandidates__aggregationLevel2_n0)
level = 2;
if( ss->nrofCandidates->aggregationLevel4 != NR_SearchSpace__nrofCandidates__aggregationLevel4_n0)
level = 4;
if( ss->nrofCandidates->aggregationLevel8 != NR_SearchSpace__nrofCandidates__aggregationLevel8_n0)
level = 8;
if( ss->nrofCandidates->aggregationLevel16 != NR_SearchSpace__nrofCandidates__aggregationLevel16_n0)
level = 16;
AssertFatal(level!=0,"Unable to find aggregation level");
return level;
}
int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
int bwp_id,
int coreset_id,
int list_id,
int aggregation,
int search_space, // 0 common, 1 ue-specific
int UE_id,
@@ -172,15 +152,15 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
if (search_space == 1) {
coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[coreset_id];
coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[list_id];
}
else {
coreset = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet;
}
int coreset_id = coreset->controlResourceSetId;
int *cce_list = nr_mac->cce_list[bwp_id][coreset_id];
int n_rb=0;
for (int i=0;i<6;i++)
for (int j=0;j<8;j++) {
@@ -202,7 +182,7 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
}
int first_cce = aggregation * (( Y + (m*N_cce)/(aggregation*M_s_max) + n_CI ) % CEILIDIV(N_cce,aggregation));
for (int i=0;i<aggregation;i++)
for (int i=0;i<aggregation;i++)
if (cce_list[first_cce+i] != 0) return(-1);
for (int i=0;i<aggregation;i++) cce_list[first_cce+i] = 1;
@@ -429,12 +409,16 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
}
void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
int ss_type,
NR_SearchSpace_t *ss,
NR_ServingCellConfigCommon_t *scc,
NR_BWP_Downlink_t *bwp){
int nr_configure_pdcch(gNB_MAC_INST *nr_mac,
nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
uint16_t rnti,
int ss_type,
NR_SearchSpace_t *ss,
NR_ServingCellConfigCommon_t *scc,
NR_BWP_Downlink_t *bwp){
int CCEIndex = -1;
int cid = 0;
NR_ControlResourceSet_t *coreset = NULL;
if (bwp) { // This is not the InitialBWP
@@ -455,6 +439,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
temp_coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[i];
if (coresetid==temp_coreset->controlResourceSetId) {
coreset = temp_coreset;
cid = i;
break;
}
}
@@ -466,7 +451,6 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
pdcch_pdu->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275);
pdcch_pdu->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing;
pdcch_pdu->CyclicPrefix = (bwp->bwp_Common->genericParameters.cyclicPrefix==NULL) ? 0 : *bwp->bwp_Common->genericParameters.cyclicPrefix;
// first symbol
//AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored");
@@ -490,6 +474,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
for (int i=0;i<6;i++)
pdcch_pdu->FreqDomainResource[i] = coreset->frequencyDomainResources.buf[i];
//cce-REG-MappingType
pdcch_pdu->CceRegMappingType = coreset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved?
@@ -511,17 +496,45 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
//precoderGranularity
pdcch_pdu->precoderGranularity = coreset->precoderGranularity;
if (ss_type) {
for (int i=0;i<pdcch_pdu->numDlDci;i++) {
//pdcch-DMRS-ScramblingID
AssertFatal(coreset->pdcch_DMRS_ScramblingID != NULL,"coreset0->pdcch_DMRS_ScramblingID is null\n");
pdcch_pdu->dci_pdu.ScramblingId[i] = *coreset->pdcch_DMRS_ScramblingID;
}
pdcch_pdu->dci_pdu.RNTI[pdcch_pdu->numDlDci]=rnti;
if (coreset->pdcch_DMRS_ScramblingID != NULL &&
ss->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) {
pdcch_pdu->dci_pdu.ScramblingId[pdcch_pdu->numDlDci] = *coreset->pdcch_DMRS_ScramblingID;
pdcch_pdu->dci_pdu.ScramblingRNTI[pdcch_pdu->numDlDci]=rnti;
}
else {
pdcch_pdu->dci_pdu.ScramblingId[pdcch_pdu->numDlDci] = *scc->physCellId;
pdcch_pdu->dci_pdu.ScramblingRNTI[pdcch_pdu->numDlDci]=0;
}
}
uint8_t nr_of_candidates,aggregation_level;
find_aggregation_candidates(&aggregation_level,
&nr_of_candidates,
ss);
CCEIndex = allocate_nr_CCEs(nr_mac,
1, // bwp_id
cid,
aggregation_level,
ss->searchSpaceType->present-1, // search_space, 0 common, 1 ue-specific
0, // UE-id
0); // m
if (CCEIndex<0)
return (CCEIndex);
pdcch_pdu->dci_pdu.AggregationLevel[pdcch_pdu->numDlDci] = aggregation_level;
pdcch_pdu->dci_pdu.CceIndex[pdcch_pdu->numDlDci] = CCEIndex;
if (ss->searchSpaceType->choice.ue_Specific->dci_Formats==NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0)
pdcch_pdu->dci_pdu.beta_PDCCH_1_0[pdcch_pdu->numDlDci]=0;
pdcch_pdu->dci_pdu.powerControlOffsetSS[pdcch_pdu->numDlDci]=1;
pdcch_pdu->numDlDci++;
return (0);
}
else { // this is for InitialBWP
AssertFatal(1==0,"Fill in InitialBWP PDCCH configuration\n");
}
@@ -713,25 +726,92 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu,
}
void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup,
dci_pdu_rel15_t *dci_pdu_rel15,
nr_dci_format_t format,
int bwp_id) {
void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats,
int *rnti_types,
int N_RB) {
NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
switch(format) {
case NR_DL_DCI_FORMAT_1_1:
// format indicator
dci_pdu_rel15->format_indicator = 1;
// carrier indicator
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL)
AssertFatal(1==0,"Cross Carrier Scheduling Config currently not supported\n");
//vrb to prb mapping
if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver==NULL)
dci_pdu_rel15->vrb_to_prb_mapping.val = 0;
else
dci_pdu_rel15->vrb_to_prb_mapping.val = 1;
//bundling size indicator
if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present == NR_PDSCH_Config__prb_BundlingType_PR_dynamicBundling)
AssertFatal(1==0,"Dynamic PRB bundling type currently not supported\n");
//rate matching indicator
uint16_t msb = (bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1==NULL)?0:1;
uint16_t lsb = (bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2==NULL)?0:1;
dci_pdu_rel15->rate_matching_indicator.val = lsb | (msb<<1);
// aperiodic ZP CSI-RS trigger
if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList != NULL)
AssertFatal(1==0,"Aperiodic ZP CSI-RS currently not supported\n");
// transmission configuration indication
if (bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[bwp_id-1]->tci_PresentInDCI != NULL)
AssertFatal(1==0,"TCI in DCI currently not supported\n");
//srs resource set
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching!=NULL) {
NR_SRS_CarrierSwitching_t *cs = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching->choice.setup;
if (cs->srs_TPC_PDCCH_Group!=NULL){
switch(cs->srs_TPC_PDCCH_Group->present) {
case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_NOTHING:
dci_pdu_rel15->srs_request.val = 0;
break;
case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_typeA:
AssertFatal(1==0,"SRS TPC PRCCH group type A currently not supported\n");
break;
case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_typeB:
AssertFatal(1==0,"SRS TPC PRCCH group type B currently not supported\n");
break;
}
}
else
dci_pdu_rel15->srs_request.val = 0;
}
else
dci_pdu_rel15->srs_request.val = 0;
// CBGTI and CBGFI
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL)
AssertFatal(1==0,"CBG transmission currently not supported\n");
// dmrs sequence initialization
dci_pdu_rel15->dmrs_sequence_initialization = 0; // FIXME no information on what this bit should be in 38.212
break;
default :
AssertFatal(1==0,"Prepare dci currently only implemented for 1_1 \n");
}
}
void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats,
int *rnti_types,
int N_RB,
int bwp_id) {
uint8_t fsize=0, pos=0;
uint8_t nbits=0;
for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) {
uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->dci_pdu.Payload[d];
int dci_size = nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],N_RB,bwp_id);
pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d] = dci_size;
AssertFatal(pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported");
int dci_size = pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d];
*dci_pdu=0;
if(dci_formats[d]==NR_DL_DCI_FORMAT_1_1)
prepare_dci(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],bwp_id);
/// Payload generation
switch(dci_formats[d]) {
case NR_DL_DCI_FORMAT_1_0:
@@ -740,23 +820,17 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos=fsize;
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_size-pos));
#ifdef DEBUG_FILL_DCI
LOG_I(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,N_RB,dci_size-pos,*dci_pdu);
#endif
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<<fsize)-1)) << (dci_size-pos));
LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,N_RB,dci_size-pos,*dci_pdu);
// Time domain assignment
pos+=4;
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos));
#ifdef DEBUG_FILL_DCI
LOG_I(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu);
#endif
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val&0xf) << (dci_size-pos));
LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu);
// VRB to PRB mapping
pos++;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_size-pos);
#ifdef DEBUG_FILL_DCI
LOG_I(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu);
#endif
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&0x1)<<(dci_size-pos);
LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu);
// MCS
pos+=5;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos);
@@ -781,13 +855,13 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment (275rb >> fsize = 16)
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos+=fsize;
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_size-pos));
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<<fsize)-1)) << (dci_size-pos));
LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,dci_size-pos,*dci_pdu);
LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu);
uint16_t is_ra = 1;
for (int i=0; i<fsize; i++)
if (!((dci_pdu_rel15->frequency_domain_assignment>>i)&1)) {
if (!((dci_pdu_rel15->frequency_domain_assignment.val>>i)&1)) {
is_ra = 0;
break;
}
@@ -799,7 +873,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// UL/SUL indicator 1 bit
pos++;
*dci_pdu |= (dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos);
*dci_pdu |= (dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos);
// SS/PBCH index 6 bits
pos+=6;
@@ -816,13 +890,13 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Time domain assignment 4bit
pos+=4;
*dci_pdu |= ((dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos));
LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,4,dci_size-pos,*dci_pdu);
*dci_pdu |= ((dci_pdu_rel15->time_domain_assignment.val&0xf) << (dci_size-pos));
LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,4,dci_size-pos,*dci_pdu);
// VRB to PRB mapping 1bit
pos++;
*dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos);
LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu);
*dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos);
LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,1,dci_size-pos,*dci_pdu);
// MCS 5bit //bit over 32, so dci_pdu ++
pos+=5;
@@ -846,8 +920,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Downlink assignment index 2bit
pos+=2;
*dci_pdu |= ((dci_pdu_rel15->dai&3)<<(dci_size-pos));
LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu);
*dci_pdu |= ((dci_pdu_rel15->dai[0].val&3)<<(dci_size-pos));
LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai[0].val,2,dci_size-pos,*dci_pdu);
// TPC command for scheduled PUCCH 2bit
pos+=2;
@@ -861,8 +935,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// PDSCH-to-HARQ_feedback timing indicator 3bit
pos+=3;
*dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_size-pos));
LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator,3,dci_size-pos,*dci_pdu);
*dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val&0x7)<<(dci_size-pos));
LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,3,dci_size-pos,*dci_pdu);
} //end else
break;
@@ -878,12 +952,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4 bit
for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5 bit
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
@@ -899,12 +973,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4 bit
for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
@@ -920,12 +994,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4 bit
for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
@@ -940,7 +1014,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Downlink assignment index – 2 bits
for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->dai>>(1-i))&1)<<(dci_size-pos++);
*dci_pdu |= (((uint64_t)dci_pdu_rel15->dai[0].val>>(1-i))&1)<<(dci_size-pos++);
// TPC command for scheduled PUCCH – 2 bits
for (int i=0; i<2; i++)
@@ -953,7 +1027,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// PDSCH-to-HARQ_feedback timing indicator – 3 bits
for (int i=0; i<3; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_size-pos++);
*dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val>>(2-i))&1)<<(dci_size-pos++);
break;
}
@@ -968,12 +1042,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4bit
for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// Frequency hopping flag – 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++);
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++);
// MCS 5 bit
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
@@ -997,7 +1071,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// UL/SUL indicator – 1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++);
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++);
*/
break;
@@ -1008,12 +1082,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4bit
for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// Frequency hopping flag – 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++);
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++);
// MCS 5 bit
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
@@ -1038,12 +1112,119 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
/*
commented for now (RK): need to get this information from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++);
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++);
*/
break;
}
break;
case NR_DL_DCI_FORMAT_1_1:
// Indicating a DL DCI format 1bit
pos=1;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&0x1)<<(dci_size-pos);
// Carrier indicator
pos+=dci_pdu_rel15->carrier_indicator.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator.val&((1<<dci_pdu_rel15->carrier_indicator.nbits)-1))<<(dci_size-pos);
// BWP indicator
pos+=dci_pdu_rel15->bwp_indicator.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator.val&((1<<dci_pdu_rel15->bwp_indicator.nbits)-1))<<(dci_size-pos);
// Frequency domain resource assignment
pos+=dci_pdu_rel15->frequency_domain_assignment.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<<dci_pdu_rel15->frequency_domain_assignment.nbits)-1)) << (dci_size-pos);
// Time domain resource assignment
pos+=dci_pdu_rel15->time_domain_assignment.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment.val&((1<<dci_pdu_rel15->time_domain_assignment.nbits)-1)) << (dci_size-pos);
// VRB-to-PRB mapping
pos+=dci_pdu_rel15->vrb_to_prb_mapping.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&((1<<dci_pdu_rel15->vrb_to_prb_mapping.nbits)-1))<<(dci_size-pos);
// PRB bundling size indicator
pos+=dci_pdu_rel15->prb_bundling_size_indicator.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->prb_bundling_size_indicator.val&((1<<dci_pdu_rel15->prb_bundling_size_indicator.nbits)-1))<<(dci_size-pos);
// Rate matching indicator
pos+=dci_pdu_rel15->rate_matching_indicator.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rate_matching_indicator.val&((1<<dci_pdu_rel15->rate_matching_indicator.nbits)-1))<<(dci_size-pos);
// ZP CSI-RS trigger
pos+=dci_pdu_rel15->zp_csi_rs_trigger.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->zp_csi_rs_trigger.val&((1<<dci_pdu_rel15->zp_csi_rs_trigger.nbits)-1)) << (dci_size-pos);
//TB1
// MCS 5bit
pos+=5;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos);
// New data indicator 1bit
pos+=1;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&0x1)<<(dci_size-pos);
// Redundancy version 2bit
pos+=2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos);
//TB2
// MCS 5bit
pos+=dci_pdu_rel15->mcs2.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs2.val&((1<<dci_pdu_rel15->mcs2.nbits)-1))<<(dci_size-pos);
// New data indicator 1bit
pos+=dci_pdu_rel15->ndi2.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi2.val&((1<<dci_pdu_rel15->ndi2.nbits)-1))<<(dci_size-pos);
// Redundancy version 2bit
pos+=dci_pdu_rel15->rv2.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv2.val&((1<<dci_pdu_rel15->rv2.nbits)-1))<<(dci_size-pos);
// HARQ process number 4bit
pos+=4;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos);
// Downlink assignment index
pos+=dci_pdu_rel15->dai[0].nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[0].val&((1<<dci_pdu_rel15->dai[0].nbits)-1))<<(dci_size-pos);
// TPC command for scheduled PUCCH 2bit
pos+=2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc&0x3)<<(dci_size-pos);
// PUCCH resource indicator 3bit
pos+=3;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos);
// PDSCH-to-HARQ_feedback timing indicator
pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val&((1<<dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits)-1))<<(dci_size-pos);
// Antenna ports
pos+=dci_pdu_rel15->antenna_ports.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports.val&((1<<dci_pdu_rel15->antenna_ports.nbits)-1))<<(dci_size-pos);
// TCI
pos+=dci_pdu_rel15->transmission_configuration_indication.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->transmission_configuration_indication.val&((1<<dci_pdu_rel15->transmission_configuration_indication.nbits)-1))<<(dci_size-pos);
// SRS request
pos+=dci_pdu_rel15->srs_request.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request.val&((1<<dci_pdu_rel15->srs_request.nbits)-1))<<(dci_size-pos);
// CBG transmission information
pos+=dci_pdu_rel15->cbgti.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti.val&((1<<dci_pdu_rel15->cbgti.nbits)-1))<<(dci_size-pos);
// CBG flushing out information
pos+=dci_pdu_rel15->cbgfi.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi.val&((1<<dci_pdu_rel15->cbgfi.nbits)-1))<<(dci_size-pos);
// DMRS sequence init
pos+=1;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization&0x1)<<(dci_size-pos);
}
}
}
@@ -1148,6 +1329,11 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
int UE_id;
int i;
NR_UE_list_t *UE_list = &RC.nrmac[mod_idP]->UE_list;
NR_COMMON_channels_t *cc = RC.nrmac[mod_idP]->common_channels;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
int num_slots_ul = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots;
if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols>0)
num_slots_ul++;
LOG_I(MAC, "[gNB %d] Adding UE with rnti %x (next avail %d, num_UEs %d)\n",
mod_idP,
rntiP,
@@ -1166,6 +1352,7 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
memset((void *) &UE_list->UE_sched_ctrl[UE_id],
0,
sizeof(NR_UE_sched_ctrl_t));
UE_list->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch *)malloc(num_slots_ul*sizeof(NR_sched_pucch));
LOG_I(MAC, "gNB %d] Add NR UE_id %d : rnti %x\n",
mod_idP,
UE_id,
@@ -1182,7 +1369,6 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
return -1;
}
void get_pdsch_to_harq_feedback(int Mod_idP,
int UE_id,
NR_SearchSpace__searchSpaceType_PR ss_type,
@@ -1202,48 +1388,51 @@ void get_pdsch_to_harq_feedback(int Mod_idP,
pdsch_to_harq_feedback[i] = i+1;
}
else {
// searching for a ue specific search space
int found=0;
for (int i=0;i<bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) {
ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i];
AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n");
AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n");
if (ss->searchSpaceType->present == ss_type) {
found=1;
break;
found=1;
break;
}
}
AssertFatal(found==1,"Couldn't find a ue specific searchspace\n");
if (ss->searchSpaceType->choice.ue_Specific->dci_Formats == NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0) {
for (int i=0; i<8; i++)
pdsch_to_harq_feedback[i] = i+1;
}
else {
if(ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK != NULL)
pdsch_to_harq_feedback = (uint8_t *)ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK;
if(ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK != NULL) {
for (int i=0; i<8; i++)
pdsch_to_harq_feedback[i] = *ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.array[i];
}
else
AssertFatal(found==1,"There is no allocated dl_DataToUL_ACK for pdsch to harq feedback\n");
AssertFatal(0==1,"There is no allocated dl_DataToUL_ACK for pdsch to harq feedback\n");
}
}
}
// function to update pucch scheduling parameters in UE list when a USS DL is scheduled
void nr_update_pucch_scheduling(int Mod_idP,
int UE_id,
frame_t frameP,
sub_frame_t slotP,
int slots_per_tdd,
NR_sched_pucch *sched_pucch) {
int *pucch_id) {
NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon;
NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
int first_ul_slot_tdd,k;
NR_sched_pucch *curr_pucch;
int first_ul_slot_tdd,k,i;
uint8_t pdsch_to_harq_feedback[8];
int found = 0;
int i = 0;
int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots;
if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0)
nr_ulmix_slots++;
@@ -1252,98 +1441,59 @@ void nr_update_pucch_scheduling(int Mod_idP,
NR_SearchSpace__searchSpaceType_PR ss_type = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
get_pdsch_to_harq_feedback(Mod_idP,UE_id,ss_type,pdsch_to_harq_feedback);
// if the list of pucch to be scheduled is empty
if (UE_list->UE_sched_ctrl[UE_id].sched_pucch == NULL) {
sched_pucch->frame = frameP;
sched_pucch->next_sched_pucch = NULL;
sched_pucch->dai_c = 1;
sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource
if ( nr_ulmix_slots > 0 ) {
// for each possible ul or mixed slot
for (k=0; k<nr_ulmix_slots; k++) {
curr_pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k];
// if there is free room in current pucch structure
if (curr_pucch->dai_c<MAX_ACK_BITS) {
curr_pucch->frame = frameP;
curr_pucch->dai_c++;
curr_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource
// first pucch occasion in first UL or MIXED slot
first_ul_slot_tdd = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots;
for (k=0; k<nr_ulmix_slots; k++) { // for each possible UL or mixed slot
while (i<8 && found == 0) { // look if timing indicator is among allowed values
if (pdsch_to_harq_feedback[i]==(first_ul_slot_tdd+k)-(slotP % slots_per_tdd))
found = 1;
if (found == 0) i++;
}
if (found == 1) break;
}
if (found == 1) {
// computing slot in which pucch is scheduled
sched_pucch->ul_slot = first_ul_slot_tdd + k + (slotP - (slotP % slots_per_tdd));
sched_pucch->timing_indicator = pdsch_to_harq_feedback[i];
}
else
AssertFatal(1==0,"No Uplink slot available in accordance to allowed timing indicator\n");
}
else
AssertFatal(1==0,"No Uplink Slots in this Frame\n");
UE_list->UE_sched_ctrl[UE_id].sched_pucch = sched_pucch;
}
else { // to be tested
curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch;
if (curr_pucch->dai_c<MAX_ACK_BITS) { // we are scheduling at most MAX_UCI_BITS harq-ack in the same pucch
while (i<8 && found == 0) { // look if timing indicator is among allowed values for current pucch
if (pdsch_to_harq_feedback[i]==(curr_pucch->ul_slot % slots_per_tdd)-(slotP % slots_per_tdd))
i = 0;
while (i<8 && found == 0) { // look if timing indicator is among allowed values
if (pdsch_to_harq_feedback[i]==(first_ul_slot_tdd+k)-(slotP % slots_per_tdd))
found = 1;
if (found == 0) i++;
}
if (found == 1) { // scheduling this harq-ack in current pucch
sched_pucch = curr_pucch;
sched_pucch->dai_c = 1 + sched_pucch->dai_c;
sched_pucch->timing_indicator = pdsch_to_harq_feedback[i];
}
}
if (curr_pucch->dai_c==MAX_ACK_BITS || found == 0) { // if current pucch is full or no timing indicator allowed
// look for pucch occasions in other UL of mixed slots
for (k=scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots; k<slots_per_tdd; k++) { // for each possible UL or mixed slot
if (k!=(curr_pucch->ul_slot % slots_per_tdd)) { // skip current scheduled slot (already checked)
i = 0;
while (i<8 && found == 0) { // look if timing indicator is among allowed values
if (pdsch_to_harq_feedback[i]==k-(slotP % slots_per_tdd))
found = 1;
if (found == 0) i++;
}
if (found == 1) {
if (k<(curr_pucch->ul_slot % slots_per_tdd)) { // we need to add a pucch occasion before current pucch
sched_pucch->frame = frameP;
sched_pucch->ul_slot = k + (slotP - (slotP % slots_per_tdd));
sched_pucch->next_sched_pucch = curr_pucch;
sched_pucch->dai_c = 1;
sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource
sched_pucch->timing_indicator = pdsch_to_harq_feedback[i];
UE_list->UE_sched_ctrl[UE_id].sched_pucch = sched_pucch;
}
else {
while (curr_pucch->next_sched_pucch != NULL && k!=(curr_pucch->ul_slot % slots_per_tdd))
curr_pucch = curr_pucch->next_sched_pucch;
if (curr_pucch == NULL) { // creating a new item in the list
sched_pucch->frame = frameP;
sched_pucch->next_sched_pucch = NULL;
sched_pucch->dai_c = 1;
sched_pucch->timing_indicator = pdsch_to_harq_feedback[i];
sched_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource
sched_pucch->ul_slot = k + (slotP - (slotP % slots_per_tdd));
curr_pucch->next_sched_pucch = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch));
curr_pucch->next_sched_pucch = sched_pucch;
}
else {
if (curr_pucch->dai_c==MAX_ACK_BITS)
found = 0; // if pucch at index k is already full we have to find a new one in a following occasion
else { // scheduling this harq-ack in current pucch
sched_pucch = curr_pucch;
sched_pucch->dai_c = 1 + sched_pucch->dai_c;
sched_pucch->timing_indicator = pdsch_to_harq_feedback[i];
}
}
}
}
}
if (found == 1) {
// computing slot in which pucch is scheduled
curr_pucch->ul_slot = first_ul_slot_tdd + k + (slotP - (slotP % slots_per_tdd));
curr_pucch->timing_indicator = i; // index in the list of timing indicators
*pucch_id = k;
return;
}
}
}
AssertFatal(1==0,"No Uplink slot available in accordance to allowed timing indicator\n");
}
void find_aggregation_candidates(uint8_t *aggregation_level,
uint8_t *nr_of_candidates,
NR_SearchSpace_t *ss) {
if (ss->nrofCandidates->aggregationLevel1 != NR_SearchSpace__nrofCandidates__aggregationLevel1_n0) {
*aggregation_level = 1;
*nr_of_candidates = ss->nrofCandidates->aggregationLevel1;
}
if (ss->nrofCandidates->aggregationLevel2 != NR_SearchSpace__nrofCandidates__aggregationLevel2_n0) {
*aggregation_level = 2;
*nr_of_candidates = ss->nrofCandidates->aggregationLevel2;
}
if (ss->nrofCandidates->aggregationLevel4 != NR_SearchSpace__nrofCandidates__aggregationLevel4_n0) {
*aggregation_level = 4;
*nr_of_candidates = ss->nrofCandidates->aggregationLevel4;
}
if (ss->nrofCandidates->aggregationLevel8 != NR_SearchSpace__nrofCandidates__aggregationLevel8_n0) {
*aggregation_level = 8;
*nr_of_candidates = ss->nrofCandidates->aggregationLevel8;
}
if (ss->nrofCandidates->aggregationLevel16 != NR_SearchSpace__nrofCandidates__aggregationLevel16_n0) {
*aggregation_level = 16;
*nr_of_candidates = ss->nrofCandidates->aggregationLevel16;
}
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+15
View File
@@ -306,5 +306,20 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
nr_process_mac_pdu(gnb_mod_idP, CC_idP, frameP, sduP, sdu_lenP);
}
}
else {
// random access pusch with TC-RNTI
if (sduP != NULL) { // if the CRC passed
for (int i = 0; i < MAX_MOBILES_PER_GNB; i++) {
if (UE_list->active[i] == TRUE) {
if (UE_list->tc_rnti[i] == current_rnti) {
// for now the only thing we are doing is set the UE as 5G connected
UE_list->fiveG_connected[i] = true;
LOG_I(MAC, "[gNB %d][RAPROC] PUSCH with TC_RNTI %x received correctly and UE_id %d is now 5G connected\n",
gnb_mod_idP, current_rnti, i);
}
}
}
}
}
}
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+28 -11
View File
@@ -126,7 +126,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
sub_frame_t subframeP);
int configure_fapi_dl_pdu(int Mod_id,
int *CCEIndeces,
nfapi_nr_dl_tti_request_body_t *dl_req,
NR_sched_pucch *pucch_sched,
uint8_t *mcsIndex,
@@ -158,7 +157,7 @@ void nr_update_pucch_scheduling(int Mod_idP,
frame_t frameP,
sub_frame_t slotP,
int slots_per_tdd,
NR_sched_pucch *sched_pucch);
int *pucch_id);
void get_pdsch_to_harq_feedback(int Mod_idP,
int UE_id,
@@ -183,6 +182,7 @@ int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space,
uint16_t slot,
nfapi_nr_config_request_scf_t cfg);
*/
void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu,
NR_ServingCellConfigCommon_t *scc,
NR_BWP_Uplink_t *bwp,
@@ -190,17 +190,35 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu,
uint16_t O_uci,
uint16_t O_ack,
uint8_t SR_flag);
void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
int ss_type,
NR_SearchSpace_t *ss,
NR_ServingCellConfigCommon_t *scc,
NR_BWP_Downlink_t *bwp);
void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
void find_search_space(int ss_type,
NR_BWP_Downlink_t *bwp,
NR_SearchSpace_t *ss);
int nr_configure_pdcch(gNB_MAC_INST *nr_mac,
nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
uint16_t rnti,
int ss_type,
NR_SearchSpace_t *ss,
NR_ServingCellConfigCommon_t *scc,
NR_BWP_Downlink_t *bwp);
void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats,
int *rnti_types,
int N_RB);
int N_RB,
int bwp_id);
void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup,
dci_pdu_rel15_t *dci_pdu_rel15,
nr_dci_format_t format,
int bwp_id);
void find_aggregation_candidates(uint8_t *aggregation_level,
uint8_t *nr_of_candidates,
NR_SearchSpace_t *ss);
int get_spf(nfapi_nr_config_request_scf_t *cfg);
@@ -208,7 +226,7 @@ int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot);
void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
int x_overhead,
uint8_t nodata_dmrs,
uint8_t numdmrscdmgroupnodata,
uint8_t tb_scaling);
/** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */
uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx);
@@ -263,7 +281,6 @@ void nr_generate_Msg2(module_id_t module_idP,
void nr_schedule_reception_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP);
int find_aggregation_level (NR_SearchSpace_t *ss);
void nr_process_mac_pdu(
module_id_t module_idP,
openair2/LAYER2/NR_MAC_gNB/main.c
+5
View File
@@ -113,6 +113,11 @@ void mac_top_init_gNB(void)
UE_list->next[list_el] = list_el + 1;
UE_list->next_ul[list_el] = list_el + 1;
UE_list->active[list_el] = FALSE;
for (int list_harq = 0; list_harq < NR_MAX_NB_HARQ_PROCESSES; list_harq++) {
UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].round = 0;
UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].ndi = 0;
UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].is_waiting = 0;
}
}
UE_list->next[list_el] = -1;
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+16 -62
View File
@@ -251,9 +251,14 @@ typedef struct NR_sched_pucch {
uint8_t dai_c;
uint8_t timing_indicator;
uint8_t resource_indicator;
struct NR_sched_pucch *next_sched_pucch;
} NR_sched_pucch;
typedef struct NR_UE_harq {
uint8_t is_waiting;
uint8_t ndi;
uint8_t round;
uint16_t feedback_slot;
} NR_UE_harq_t;
/*! \brief scheduling control information set through an API */
typedef struct {
@@ -262,10 +267,17 @@ typedef struct {
NR_sched_pucch *sched_pucch;
uint16_t ta_timer;
int16_t ta_update;
uint8_t current_harq_pid;
NR_UE_harq_t harq_processes[NR_MAX_NB_HARQ_PROCESSES];
int dummy;
NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information
} NR_UE_sched_ctrl_t;
typedef struct NR_preamble_ue {
uint8_t num_preambles;
uint8_t *preamble_list;
} NR_preamble_ue;
/*! \brief UE list used by gNB to order UEs/CC for scheduling*/
typedef struct {
DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB];
@@ -278,7 +290,10 @@ typedef struct {
int avail;
int num_UEs;
boolean_t active[MAX_MOBILES_PER_GNB];
boolean_t fiveG_connected[MAX_MOBILES_PER_GNB];
rnti_t rnti[MAX_MOBILES_PER_GNB];
rnti_t tc_rnti[MAX_MOBILES_PER_GNB];
NR_preamble_ue preambles[MAX_MOBILES_PER_GNB];
NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB];
} NR_UE_list_t;
@@ -348,65 +363,4 @@ typedef struct gNB_MAC_INST_s {
int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE];
} gNB_MAC_INST;
typedef struct {
uint8_t format_indicator; //1 bit
uint16_t frequency_domain_assignment; //up to 16 bits
uint8_t time_domain_assignment; // 4 bits
uint8_t frequency_hopping_flag; //1 bit
uint8_t ra_preamble_index; //6 bits
uint8_t ss_pbch_index; //6 bits
uint8_t prach_mask_index; //4 bits
uint8_t vrb_to_prb_mapping; //0 or 1 bit
uint8_t mcs; //5 bits
uint8_t ndi; //1 bit
uint8_t rv; //2 bits
uint8_t harq_pid; //4 bits
uint8_t dai; //0, 2 or 4 bits
uint8_t dai1; //1 or 2 bits
uint8_t dai2; //0 or 2 bits
uint8_t tpc; //2 bits
uint8_t pucch_resource_indicator; //3 bits
uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits
uint8_t short_messages_indicator; //2 bits
uint8_t short_messages; //8 bits
uint8_t tb_scaling; //2 bits
uint8_t carrier_indicator; //0 or 3 bits
uint8_t bwp_indicator; //0, 1 or 2 bits
uint8_t prb_bundling_size_indicator; //0 or 1 bits
uint8_t rate_matching_indicator; //0, 1 or 2 bits
uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits
uint8_t transmission_configuration_indication; //0 or 3 bits
uint8_t srs_request; //2 bits
uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits
uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit
uint8_t dmrs_sequence_initialization; //0 or 1 bit
uint8_t srs_resource_indicator;
uint8_t precoding_information;
uint8_t csi_request;
uint8_t ptrs_dmrs_association;
uint8_t beta_offset_indicator; //0 or 2 bits
uint8_t slot_format_indicator_count;
uint8_t *slot_format_indicators;
uint8_t pre_emption_indication_count;
uint16_t *pre_emption_indications; //14 bit
uint8_t block_number_count;
uint8_t *block_numbers;
uint8_t ul_sul_indicator; //0 or 1 bit
uint8_t antenna_ports;
uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
uint16_t padding;
} dci_pdu_rel15_t;
#endif /*__LAYER2_NR_MAC_GNB_H__ */
openair2/NR_PHY_INTERFACE/NR_IF_Module.c
+49 -66
View File
@@ -38,6 +38,7 @@
#include "LAYER2/MAC/mac_proto.h"
#include "LAYER2/NR_MAC_gNB/mac_proto.h"
#include "common/ran_context.h"
#include "executables/softmodem-common.h"
#define MAX_IF_MODULES 100
@@ -76,76 +77,60 @@ void handle_nr_rach(NR_UL_IND_t *UL_info) {
}
void handle_nr_sr(NR_UL_IND_t *UL_info) {
void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_ctrl) {
// TODO
int max_harq_rounds = 4; // TODO define macro
int num_ucis = UL_info->uci_ind.num_ucis;
nfapi_nr_uci_t *uci_list = UL_info->uci_ind.uci_list;
for (int i = 0; i < num_ucis; i++) {
switch (uci_list[i].pdu_type) {
case NFAPI_NR_UCI_PDCCH_PDU_TYPE: break;
/* if (nfapi_mode == 1) // PNF
{
if (UL_info->sr_ind.sr_indication_body.number_of_srs>0)
{
// oai_nfapi_sr_indication(&UL_info->sr_ind);
case NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE: {
if (get_softmodem_params()->phy_test == 0) {
nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu = &uci_list[i].pucch_pdu_format_0_1;
// handle harq
int harq_idx_s = 0;
// iterate over received harq bits
for (int harq_bit = 0; harq_bit < uci_pdu->harq->num_harq; harq_bit++) {
// search for the right harq process
for (int harq_idx = harq_idx_s; harq_idx < NR_MAX_NB_HARQ_PROCESSES-1; harq_idx++) {
if ((UL_info->slot-1) == sched_ctrl->harq_processes[harq_idx].feedback_slot) {
if (uci_pdu->harq->harq_list[harq_bit].harq_value == 0)
sched_ctrl->harq_processes[harq_idx].round++;
if ((uci_pdu->harq->harq_list[harq_bit].harq_value == 1) ||
(sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds)) {
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
}
sched_ctrl->harq_processes[harq_idx].is_waiting = 0;
harq_idx_s = harq_idx + 1;
break;
}
// if gNB fails to receive a ACK/NACK
else if (((UL_info->slot-1) > sched_ctrl->harq_processes[harq_idx].feedback_slot) &&
(sched_ctrl->harq_processes[harq_idx].is_waiting)) {
sched_ctrl->harq_processes[harq_idx].round++;
if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) {
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
}
sched_ctrl->harq_processes[harq_idx].is_waiting = 0;
}
}
}
}
break;
}
case NFAPI_NR_UCI_FORMAT_2_3_4_PDU_TYPE: break;
}
}
else
{
for (int i=0;i<UL_info->sr_ind.sr_indication_body.number_of_srs;i++)
SR_indication(UL_info->module_id,
UL_info->CC_id,
UL_info->frame,
UL_info->slot,
UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].rx_ue_information.rnti,
UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].ul_cqi_information.ul_cqi);
}
UL_info->sr_ind.sr_indication_body.number_of_srs=0;*/
UL_info->uci_ind.num_ucis = 0;
}
void handle_nr_cqi(NR_UL_IND_t *UL_info) {
/*
for (int i=0;i<UL_info->cqi_ind.number_of_cqis;i++)
cqi_indication(UL_info->module_id,
UL_info->CC_id,
UL_info->frame,
UL_info->slot,
UL_info->cqi_ind.cqi_pdu_list[i].rx_ue_information.rnti,
&UL_info->cqi_ind.cqi_pdu_list[i].cqi_indication_rel9,
UL_info->cqi_ind.cqi_raw_pdu_list[i].pdu,
&UL_info->cqi_ind.cqi_pdu_list[i].ul_cqi_information);
UL_info->cqi_ind.number_of_cqis=0;*/
}
void handle_nr_harq(NR_UL_IND_t *UL_info) {
/* if (nfapi_mode == 1 && UL_info->harq_ind.harq_indication_body.number_of_harqs>0) { // PNF
//LOG_D(PHY, "UL_info->harq_ind.harq_indication_body.number_of_harqs:%d Send to VNF\n", UL_info->harq_ind.harq_indication_body.number_of_harqs);
int retval = oai_nfapi_harq_indication(&UL_info->harq_ind);
if (retval!=0) {
LOG_E(PHY, "Failed to encode NFAPI HARQ_IND retval:%d\n", retval);
}
UL_info->harq_ind.harq_indication_body.number_of_harqs = 0;
}
else
{
for (int i=0;i<UL_info->harq_ind.harq_indication_body.number_of_harqs;i++)
harq_indication(UL_info->module_id,
UL_info->CC_id,
NFAPI_SFNSF2SFN(UL_info->harq_ind.sfn_sf),
NFAPI_SFNSF2SF(UL_info->harq_ind.sfn_sf),
&UL_info->harq_ind.harq_indication_body.harq_pdu_list[i]);
UL_info->harq_ind.harq_indication_body.number_of_harqs=0;
}*/
}
void handle_nr_ulsch(NR_UL_IND_t *UL_info) {
if(nfapi_mode == 1) {
@@ -245,9 +230,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) {
// clear DL/UL info for new scheduling round
clear_nr_nfapi_information(mac,CC_id,UL_info->frame,UL_info->slot);
handle_nr_rach(UL_info);
handle_nr_sr(UL_info);
handle_nr_cqi(UL_info);
handle_nr_harq(UL_info);
handle_nr_uci(UL_info, &mac->UE_list.UE_sched_ctrl[0]);
// clear HI prior to handling ULSCH
mac->UL_dci_req[CC_id].numPdus = 0;
handle_nr_ulsch(UL_info);
openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
+2
View File
@@ -276,6 +276,8 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq) {
dl_config->slot=UE_mac->dl_config_request.slot;
dl_config->number_pdus=0;
//printf(" UE_mac->dl_config_request.slot %d VS dcireq->slot %d \n", UE_mac->dl_config_request.slot, dcireq->slot);
LOG_D(PHY, "Entering UE DCI configuration frame %d slot %d \n", dcireq->frame, dcireq->slot);
ue_dci_configuration(UE_mac, dl_config, dcireq->frame, dcireq->slot);
openair2/RRC/LTE/rrc_defs.h
+1
View File
@@ -271,6 +271,7 @@ typedef enum UE_STATE_e {
RRC_RECONFIGURED,
RRC_HO_EXECUTION,
RRC_NR_NSA,
RRC_NR_NSA_RECONFIGURED
} UE_STATE_t;
typedef enum HO_STATE_e {
openair2/RRC/LTE/rrc_eNB.c
+75 -61
View File
@@ -3251,8 +3251,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t
MeasObj2->measObjectId = 2;
MeasObj2->measObject.present = LTE_MeasObjectToAddMod__measObject_PR_measObjectNR_r15;
MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 =
642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016)
MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 =641272; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016)
MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.present = LTE_MTC_SSB_NR_r15__periodicityAndOffset_r15_PR_sf20_r15;
MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.choice.sf20_r15 = 0;
MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.ssb_Duration_r15 = LTE_MTC_SSB_NR_r15__ssb_Duration_r15_sf4;
@@ -3400,7 +3399,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.present = LTE_ReportConfigInterRAT__triggerType_PR_event;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.present = LTE_ReportConfigInterRAT__triggerType__event__eventId_PR_eventB1_NR_r15;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.present = LTE_ThresholdNR_r15_PR_nr_RSRP_r15;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 46;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 0;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.reportOnLeave_r15 = FALSE;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.hysteresis = 2;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.timeToTrigger = LTE_TimeToTrigger_ms80;
@@ -4614,7 +4613,7 @@ rrc_eNB_process_MeasurementReport(
/* TODO: improve NR triggering */
if (measResults2->measId == 7) {
if (ue_context_pP->ue_context.Status != RRC_NR_NSA) {
if ((ue_context_pP->ue_context.Status != RRC_NR_NSA) && (ue_context_pP->ue_context.Status != RRC_NR_NSA_RECONFIGURED)) {
MessageDef *msg;
ue_context_pP->ue_context.Status = RRC_NR_NSA;
@@ -4637,7 +4636,7 @@ rrc_eNB_process_MeasurementReport(
for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++) {
X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id;
X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid;
X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = 1;
X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = ue_context_pP->ue_context.DRB_configList->list.array[e_rab]->drb_Identity;
memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr,
&ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr,
sizeof(transport_layer_addr_t));
@@ -7774,7 +7773,37 @@ rrc_eNB_decode_dcch(
LOG_I(RRC,
PROTOCOL_RRC_CTXT_UE_FMT" UE State = RRC_HO_EXECUTION (xid %ld)\n",
PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.rrc_TransactionIdentifier);
} else {
}
else if(ue_context_p->ue_context.Status == RRC_NR_NSA){
//Looking for a condition to trigger S1AP E-RAB-Modification-indication, based on the reception of RRCConnectionReconfigurationComplete
//including NR specific elements.
if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension!=NULL) {
if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension!=NULL) {
if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) {
if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) {
if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) {
if (ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) {
if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension
->scg_ConfigResponseNR_r15!=NULL) {
ue_context_p->ue_context.Status = RRC_NR_NSA_RECONFIGURED;
/*Trigger E-RAB Modification Indication */
rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p);
}
}
}
}
}
}
}
}
else {
dedicated_DRB = 0;
ue_context_p->ue_context.Status = RRC_RECONFIGURED;
LOG_I(RRC,
@@ -7784,39 +7813,6 @@ rrc_eNB_decode_dcch(
ue_context_p->ue_context.reestablishment_xid = -1;
//Looking for a condition to trigger S1AP E-RAB-Modification-indication, based on the reception of RRCConnectionReconfigurationComplete
//including NR specific elements. Not sure if this is the correct one and the correct placement
/*if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->
scg_ConfigResponseNR_r15->buf!=NULL){
//Trigger E-RAB Modification Indication
rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p);
}*/
if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension!=NULL) {
if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension!=NULL) {
if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) {
if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) {
if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) {
if (ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) {
if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension
->scg_ConfigResponseNR_r15!=NULL) {
/*Trigger E-RAB Modification Indication */
rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p);
}
}
}
}
}
}
}
} else {
dedicated_DRB = 1;
ue_context_p->ue_context.Status = RRC_RECONFIGURED;
@@ -8371,36 +8367,54 @@ rrc_eNB_decode_dcch(
return 0;
//TTN for D2D
} else if (ul_dcch_msg->message.present == LTE_UL_DCCH_MessageType_PR_messageClassExtension) {
LOG_I(RRC, "THINH [LTE_UL_DCCH_MessageType_PR_messageClassExtension]\n");
LOG_I(RRC, "[LTE_UL_DCCH_MessageType_PR_messageClassExtension]\n");
switch (ul_dcch_msg->message.choice.messageClassExtension.present) {
case LTE_UL_DCCH_MessageType__messageClassExtension_PR_NOTHING: /* No components present */
break;
case LTE_UL_DCCH_MessageType__messageClassExtension_PR_c2: //SidelinkUEInformation
//case UL_DCCH_MessageType__messageClassExtension__c2_PR_sidelinkUEInformation_r12: //SidelinkUEInformation
LOG_I(RRC,"THINH [LTE_UL_DCCH_MessageType__messageClassExtension_PR_c2]\n");
LOG_DUMPMSG(RRC,DEBUG_RRC,(char *)Rx_sdu,sdu_sizeP,
if(ul_dcch_msg->message.choice.messageClassExtension.choice.c2.present ==
LTE_UL_DCCH_MessageType__messageClassExtension__c2_PR_scgFailureInformationNR_r15){
if (ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.
criticalExtensions.present == LTE_SCGFailureInformationNR_r15__criticalExtensions_PR_c1){
if (ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions.
choice.c1.present == LTE_SCGFailureInformationNR_r15__criticalExtensions__c1_PR_scgFailureInformationNR_r15){
if (ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions.
choice.c1.choice.scgFailureInformationNR_r15.failureReportSCG_NR_r15!=NULL) {
LOG_E(RRC, "Received NR scgFailureInformation from UE, failure type: %ld \n",
ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions.
choice.c1.choice.scgFailureInformationNR_r15.failureReportSCG_NR_r15->failureType_r15);
xer_fprint(stdout, &asn_DEF_LTE_UL_DCCH_Message, (void *)ul_dcch_msg);
}
}
}
}
else if(ul_dcch_msg->message.choice.messageClassExtension.choice.c2.present == LTE_UL_DCCH_MessageType__messageClassExtension__c2_PR_sidelinkUEInformation_r12){
//case UL_DCCH_MessageType__messageClassExtension__c2_PR_sidelinkUEInformation_r12: //SidelinkUEInformation
LOG_I(RRC,"THINH [LTE_UL_DCCH_MessageType__messageClassExtension_PR_c2]\n");
LOG_DUMPMSG(RRC,DEBUG_RRC,(char *)Rx_sdu,sdu_sizeP,
"[MSG] RRC SidelinkUEInformation \n");
MSC_LOG_RX_MESSAGE(
MSC_RRC_ENB,
MSC_RRC_UE,
Rx_sdu,
sdu_sizeP,
MSC_AS_TIME_FMT" SidelinkUEInformation UE %x size %u",
MSC_AS_TIME_ARGS(ctxt_pP),
ue_context_p->ue_context.rnti,
sdu_sizeP);
LOG_I(RRC,
PROTOCOL_RRC_CTXT_UE_FMT" RLC RB %02d --- RLC_DATA_IND %d bytes "
"(SidelinkUEInformation) ---> RRC_eNB\n",
PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),
DCCH,
MSC_LOG_RX_MESSAGE(
MSC_RRC_ENB,
MSC_RRC_UE,
Rx_sdu,
sdu_sizeP,
MSC_AS_TIME_FMT" SidelinkUEInformation UE %x size %u",
MSC_AS_TIME_ARGS(ctxt_pP),
ue_context_p->ue_context.rnti,
sdu_sizeP);
rrc_eNB_process_SidelinkUEInformation(
ctxt_pP,
ue_context_p,
&ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.sidelinkUEInformation_r12);
LOG_I(RRC,
PROTOCOL_RRC_CTXT_UE_FMT" RLC RB %02d --- RLC_DATA_IND %d bytes "
"(SidelinkUEInformation) ---> RRC_eNB\n",
PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),
DCCH,
sdu_sizeP);
rrc_eNB_process_SidelinkUEInformation(
ctxt_pP,
ue_context_p,
&ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.sidelinkUEInformation_r12);
}
break;
default:
openair2/RRC/NR/rrc_gNB_nsa.c
+5 -3
View File
@@ -42,10 +42,12 @@
void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t *cg_config_info) {
struct rrc_gNB_ue_context_s *ue_context_p = NULL;
OCTET_STRING_t *ueCapabilityRAT_Container_nr = NULL;
OCTET_STRING_t *ueCapabilityRAT_Container_MRDC = NULL;
int list_size;
OCTET_STRING_t *ueCapabilityRAT_Container_nr=NULL;
OCTET_STRING_t *ueCapabilityRAT_Container_MRDC=NULL;
asn_dec_rval_t dec_rval;
int list_size=0;
AssertFatal(UE_CapabilityRAT_ContainerList!=NULL,"UE_CapabilityRAT_ContainerList is null\n");
AssertFatal((list_size=UE_CapabilityRAT_ContainerList->list.count) >= 2, "UE_CapabilityRAT_ContainerList->list.size %d < 2\n",UE_CapabilityRAT_ContainerList->list.count);
openair2/RRC/NR/rrc_gNB_reconfig.c
+1784 -1677
View File
File diff suppressed because it is too large Load Diff
openair2/X2AP/x2ap_eNB_decoder.c
+2 -2
View File
@@ -144,9 +144,9 @@ int x2ap_eNB_decode_pdu(X2AP_X2AP_PDU_t *pdu, const uint8_t *const buffer, uint3
length,
0,
0);
//if (asn1_xer_print) {
if (asn1_xer_print) {
xer_fprint(stdout, &asn_DEF_X2AP_X2AP_PDU, pdu);
//}
}
if (dec_ret.code != RC_OK) {
X2AP_ERROR("Failed to decode pdu\n");
openair2/X2AP/x2ap_eNB_handler.c
+1 -2
View File
@@ -1768,8 +1768,7 @@ LOG_I(RRC,"x2u tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\
X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequest_IEs_t, ie, x2SgNBAdditionRequest,
X2AP_ProtocolIE_ID_id_MeNBtoSgNBContainer, true);
if (ie->value.choice.MeNBtoSgNBContainer.size > 8192 )
if (ie->value.choice.MeNBtoSgNBContainer.size > 8192 ) // TODO: this is the size of rrc_buffer in struct x2ap_handover_req_s
{ printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); }
memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size);