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Fix hardcoded coreset and assignment from wrong array position

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This commit is contained in:
luis_pereira87
2022-05-12 13:12:45 +01:00
parent 9aa7d1c88f
commit af377945c3
10 changed files with 28 additions and 19 deletions
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openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
+11 -6
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@@ -2598,6 +2598,7 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
nr_rnti_type_t rnti_type, nr_rnti_type_t rnti_type,
uint16_t N_RB, uint16_t N_RB,
int bwp_id, int bwp_id,
NR_ControlResourceSetId_t coreset_id,
uint16_t cset0_bwp_size) { uint16_t cset0_bwp_size) {
uint16_t size = 0; uint16_t size = 0;
@@ -2648,7 +2649,7 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
/// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20 /// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20
size += 20; size += 20;
size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated
int dci_10_size = nr_dci_size(initialDownlinkBWP,initialUplinkBWP,cg,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, bwp_id, cset0_bwp_size); int dci_10_size = nr_dci_size(initialDownlinkBWP,initialUplinkBWP,cg,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, bwp_id, coreset_id, cset0_bwp_size);
AssertFatal(dci_10_size >= size, "NR_UL_DCI_FORMAT_0_0 size is bigger than NR_DL_DCI_FORMAT_1_0! 3GPP TS 38.212 Section 7.3.1.0: DCI size alignment is not fully implemented"); AssertFatal(dci_10_size >= size, "NR_UL_DCI_FORMAT_0_0 size is bigger than NR_DL_DCI_FORMAT_1_0! 3GPP TS 38.212 Section 7.3.1.0: DCI size alignment is not fully implemented");
size += dci_10_size - size; // Padding to match 1_0 size size += dci_10_size - size; // Padding to match 1_0 size
// UL/SUL indicator assumed to be 0 // UL/SUL indicator assumed to be 0
@@ -2992,11 +2993,15 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
size += dci_pdu->antenna_ports.nbits; size += dci_pdu->antenna_ports.nbits;
LOG_D(NR_MAC,"dci_pdu->antenna_ports.nbits %d\n",dci_pdu->antenna_ports.nbits); LOG_D(NR_MAC,"dci_pdu->antenna_ports.nbits %d\n",dci_pdu->antenna_ports.nbits);
// Tx Config Indication // Tx Config Indication
int corset_id = 1 ; for (int i = 0; i < pdcch_Config->controlResourceSetToAddModList->list.count; i++) {
long *isTciEnable = pdcch_Config->controlResourceSetToAddModList->list.array[corset_id-1]->tci_PresentInDCI; if (pdcch_Config->controlResourceSetToAddModList->list.array[i]->controlResourceSetId == coreset_id) {
if (isTciEnable != NULL) { long *isTciEnable = pdcch_Config->controlResourceSetToAddModList->list.array[i]->tci_PresentInDCI;
dci_pdu->transmission_configuration_indication.nbits = 3; if (isTciEnable != NULL) {
size += dci_pdu->transmission_configuration_indication.nbits; dci_pdu->transmission_configuration_indication.nbits = 3;
size += dci_pdu->transmission_configuration_indication.nbits;
}
break;
}
} }
// SRS request // SRS request
if (cg->spCellConfig->spCellConfigDedicated->supplementaryUplink==NULL) if (cg->spCellConfig->spCellConfigDedicated->supplementaryUplink==NULL)
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h
+1
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@@ -55,6 +55,7 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDLBWP,
nr_rnti_type_t rnti_type, nr_rnti_type_t rnti_type,
uint16_t N_RB, uint16_t N_RB,
int bwp_id, int bwp_id,
NR_ControlResourceSetId_t coreset_id,
uint16_t cset0_bwp_size); uint16_t cset0_bwp_size);
void find_aggregation_candidates(uint8_t *aggregation_level, void find_aggregation_candidates(uint8_t *aggregation_level,
openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
+4 -4
View File
@@ -169,7 +169,7 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t
rel15->SubcarrierSpacing = bwp_Common->genericParameters.subcarrierSpacing; rel15->SubcarrierSpacing = bwp_Common->genericParameters.subcarrierSpacing;
} }
for (int i = 0; i < rel15->num_dci_options; i++) { for (int i = 0; i < rel15->num_dci_options; i++) {
rel15->dci_length_options[i] = nr_dci_size(initialDownlinkBWP,initialUplinkBWP, mac->cg, &mac->def_dci_pdu_rel15[rel15->dci_format_options[i]], rel15->dci_format_options[i], NR_RNTI_C, rel15->BWPSize, dl_bwp_id, mac->type0_PDCCH_CSS_config.num_rbs); rel15->dci_length_options[i] = nr_dci_size(initialDownlinkBWP,initialUplinkBWP, mac->cg, &mac->def_dci_pdu_rel15[rel15->dci_format_options[i]], rel15->dci_format_options[i], NR_RNTI_C, rel15->BWPSize, dl_bwp_id, coreset_id, mac->type0_PDCCH_CSS_config.num_rbs);
} }
break; break;
case NR_RNTI_RA: case NR_RNTI_RA:
@@ -185,7 +185,7 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t
rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
} }
rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing; rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing;
rel15->dci_length_options[0] = nr_dci_size(initialDownlinkBWP,initialUplinkBWP, mac->cg, &mac->def_dci_pdu_rel15[rel15->dci_format_options[0]], rel15->dci_format_options[0], NR_RNTI_RA, rel15->BWPSize, dl_bwp_id, mac->type0_PDCCH_CSS_config.num_rbs); rel15->dci_length_options[0] = nr_dci_size(initialDownlinkBWP,initialUplinkBWP, mac->cg, &mac->def_dci_pdu_rel15[rel15->dci_format_options[0]], rel15->dci_format_options[0], NR_RNTI_RA, rel15->BWPSize, dl_bwp_id, coreset_id, mac->type0_PDCCH_CSS_config.num_rbs);
break; break;
case NR_RNTI_P: case NR_RNTI_P:
break; break;
@@ -200,7 +200,7 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t
rel15->BWPStart = mac->type0_PDCCH_CSS_config.cset_start_rb; rel15->BWPStart = mac->type0_PDCCH_CSS_config.cset_start_rb;
rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing; rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing;
for (int i = 0; i < rel15->num_dci_options; i++) { for (int i = 0; i < rel15->num_dci_options; i++) {
rel15->dci_length_options[i] = nr_dci_size(initialDownlinkBWP,initialUplinkBWP, mac->cg, &mac->def_dci_pdu_rel15[rel15->dci_format_options[i]], rel15->dci_format_options[i], NR_RNTI_TC, rel15->BWPSize, dl_bwp_id, mac->type0_PDCCH_CSS_config.num_rbs); rel15->dci_length_options[i] = nr_dci_size(initialDownlinkBWP,initialUplinkBWP, mac->cg, &mac->def_dci_pdu_rel15[rel15->dci_format_options[i]], rel15->dci_format_options[i], NR_RNTI_TC, rel15->BWPSize, dl_bwp_id, coreset_id, mac->type0_PDCCH_CSS_config.num_rbs);
} }
break; break;
case NR_RNTI_SP_CSI: case NR_RNTI_SP_CSI:
@@ -223,7 +223,7 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t
rel15->SubcarrierSpacing = mac->mib->subCarrierSpacingCommon + 2; rel15->SubcarrierSpacing = mac->mib->subCarrierSpacingCommon + 2;
for (int i = 0; i < rel15->num_dci_options; i++) { for (int i = 0; i < rel15->num_dci_options; i++) {
rel15->dci_length_options[i] = nr_dci_size(initialDownlinkBWP,initialUplinkBWP, mac->cg, &mac->def_dci_pdu_rel15[rel15->dci_format_options[i]], rel15->dci_format_options[i], NR_RNTI_SI, rel15->BWPSize, 0, mac->type0_PDCCH_CSS_config.num_rbs); rel15->dci_length_options[i] = nr_dci_size(initialDownlinkBWP,initialUplinkBWP, mac->cg, &mac->def_dci_pdu_rel15[rel15->dci_format_options[i]], rel15->dci_format_options[i], NR_RNTI_SI, rel15->BWPSize, 0, coreset_id, mac->type0_PDCCH_CSS_config.num_rbs);
} }
break; break;
case NR_RNTI_SFI: case NR_RNTI_SFI:
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+3
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@@ -904,6 +904,7 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
NR_RNTI_TC, NR_RNTI_TC,
pusch_pdu->bwp_size, pusch_pdu->bwp_size,
ra->ul_bwp_id, ra->ul_bwp_id,
coresetid,
nr_mac->cset0_bwp_size); nr_mac->cset0_bwp_size);
// Mark the corresponding RBs as used // Mark the corresponding RBs as used
@@ -1484,6 +1485,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
NR_RNTI_RA, NR_RNTI_RA,
BWPSize, BWPSize,
bwpid, bwpid,
coresetid,
nr_mac->cset0_bwp_size); nr_mac->cset0_bwp_size);
// DL TX request // DL TX request
@@ -1893,6 +1895,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
NR_RNTI_TC, NR_RNTI_TC,
pdsch_pdu_rel15->BWPSize, pdsch_pdu_rel15->BWPSize,
bwpid, bwpid,
coresetid,
nr_mac->cset0_bwp_size); nr_mac->cset0_bwp_size);
// Add padding header and zero rest out if there is space left // Add padding header and zero rest out if there is space left
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
+1
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@@ -552,6 +552,7 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
rnti_type, rnti_type,
pdsch_pdu_rel15->BWPSize, pdsch_pdu_rel15->BWPSize,
0, 0,
0,
gNB_mac->cset0_bwp_size); gNB_mac->cset0_bwp_size);
LOG_D(MAC,"BWPSize: %i\n", pdcch_pdu_rel15->BWPSize); LOG_D(MAC,"BWPSize: %i\n", pdcch_pdu_rel15->BWPSize);
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+1
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@@ -1374,6 +1374,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
rnti_type, rnti_type,
pdsch_pdu->BWPSize, pdsch_pdu->BWPSize,
bwp ? bwp->bwp_Id : 0, bwp ? bwp->bwp_Id : 0,
coresetid,
gNB_mac->cset0_bwp_size); gNB_mac->cset0_bwp_size);
LOG_D(NR_MAC, LOG_D(NR_MAC,
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+2 -1
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@@ -1486,12 +1486,13 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
int rnti_type, int rnti_type,
int N_RB, int N_RB,
int bwp_id, int bwp_id,
NR_ControlResourceSetId_t coreset_id,
uint16_t cset0_bwp_size) { uint16_t cset0_bwp_size) {
uint8_t fsize = 0, pos = 0; uint8_t fsize = 0, pos = 0;
uint64_t *dci_pdu = (uint64_t *)pdcch_dci_pdu->Payload; uint64_t *dci_pdu = (uint64_t *)pdcch_dci_pdu->Payload;
*dci_pdu=0; *dci_pdu=0;
int dci_size = nr_dci_size(scc->downlinkConfigCommon->initialDownlinkBWP,scc->uplinkConfigCommon->initialUplinkBWP, CellGroup, dci_pdu_rel15, dci_format, rnti_type, N_RB, bwp_id, cset0_bwp_size); int dci_size = nr_dci_size(scc->downlinkConfigCommon->initialDownlinkBWP,scc->uplinkConfigCommon->initialUplinkBWP, CellGroup, dci_pdu_rel15, dci_format, rnti_type, N_RB, bwp_id, coreset_id, cset0_bwp_size);
pdcch_dci_pdu->PayloadSizeBits = dci_size; pdcch_dci_pdu->PayloadSizeBits = dci_size;
AssertFatal(dci_size <= 64, "DCI sizes above 64 bits not yet supported"); AssertFatal(dci_size <= 64, "DCI sizes above 64 bits not yet supported");
if (dci_format == NR_DL_DCI_FORMAT_1_1 || dci_format == NR_UL_DCI_FORMAT_0_1) if (dci_format == NR_DL_DCI_FORMAT_1_1 || dci_format == NR_UL_DCI_FORMAT_0_1)
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c
+3 -8
View File
@@ -876,9 +876,7 @@ int checkTargetSSBInTCIStates_pdcchConfig(int ssb_index_t, int Mod_idP, int UE_i
NR_TCI_State_t *tci =NULL; NR_TCI_State_t *tci =NULL;
NR_TCI_StateId_t *tci_id = NULL; NR_TCI_StateId_t *tci_id = NULL;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int bwp_id = sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0; NR_ControlResourceSet_t *coreset = sched_ctrl->coreset;
NR_BWP_Downlink_t *bwp = CellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
NR_ControlResourceSet_t *coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[bwp_id-1];
int i; int i;
int flag = 0; int flag = 0;
int tci_stateID = -1; int tci_stateID = -1;
@@ -948,7 +946,6 @@ void tci_handling(module_id_t Mod_idP, int UE_id, frame_t frame, slot_t slot) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int bwp_id = sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0; const int bwp_id = sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0;
NR_CellGroupConfig_t *CellGroup = UE_info->CellGroup[UE_id]; NR_CellGroupConfig_t *CellGroup = UE_info->CellGroup[UE_id];
NR_BWP_Downlink_t *bwp = bwp_id > 0 ? sched_ctrl->active_bwp : NULL;
//bwp indicator //bwp indicator
int n_dl_bwp=0; int n_dl_bwp=0;
@@ -1078,10 +1075,8 @@ void tci_handling(module_id_t Mod_idP, int UE_id, frame_t frame, slot_t slot) {
} }
} }
sched_ctrl->UE_mac_ce_ctrl.pdcch_state_ind.tci_present_inDCI = bwp ? sched_ctrl->UE_mac_ce_ctrl.pdcch_state_ind.tci_present_inDCI = sched_ctrl->coreset ?
bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[bwp_id-1]->tci_PresentInDCI : sched_ctrl->coreset->tci_PresentInDCI : NULL;
CellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]->tci_PresentInDCI;
//filling pdsch tci state activation deactivation mac ce structure fields //filling pdsch tci state activation deactivation mac ce structure fields
if(sched_ctrl->UE_mac_ce_ctrl.pdcch_state_ind.tci_present_inDCI) { if(sched_ctrl->UE_mac_ce_ctrl.pdcch_state_ind.tci_present_inDCI) {
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+1
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@@ -1938,6 +1938,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
rnti_types[0], rnti_types[0],
pusch_pdu->bwp_size, pusch_pdu->bwp_size,
bwp_id, bwp_id,
coresetid,
nr_mac->cset0_bwp_size); nr_mac->cset0_bwp_size);
memset(sched_pusch, 0, sizeof(*sched_pusch)); memset(sched_pusch, 0, sizeof(*sched_pusch));
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+1
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@@ -307,6 +307,7 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
int rnti_types, int rnti_types,
int N_RB, int N_RB,
int bwp_id, int bwp_id,
NR_ControlResourceSetId_t coreset_id,
uint16_t cset0_bwp_size); uint16_t cset0_bwp_size);
void prepare_dci(const NR_CellGroupConfig_t *CellGroup, void prepare_dci(const NR_CellGroupConfig_t *CellGroup,