added CQI request timer. CQI only requested periodically. MCS20 on UL works now.
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@@ -742,6 +742,7 @@ typedef struct {
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uint16_t ta_timer;
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uint16_t ta_timer;
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int16_t ta_update;
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int16_t ta_update;
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int32_t context_active_timer;
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int32_t context_active_timer;
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int32_t cqi_req_timer;
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int32_t ul_inactivity_timer;
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int32_t ul_inactivity_timer;
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int32_t ul_failure_timer;
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int32_t ul_failure_timer;
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int32_t ra_pdcch_order_sent;
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int32_t ra_pdcch_order_sent;
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@@ -127,6 +127,8 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
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// increment this, it is cleared when we receive an sdu
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// increment this, it is cleared when we receive an sdu
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eNB_mac_inst[module_idP].UE_list.UE_sched_ctrl[i].ul_inactivity_timer++;
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eNB_mac_inst[module_idP].UE_list.UE_sched_ctrl[i].ul_inactivity_timer++;
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eNB_mac_inst[module_idP].UE_list.UE_sched_ctrl[i].cqi_req_timer++;
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if (mac_xface->get_eNB_UE_stats(module_idP, CC_id, rnti)==NULL) {
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if (mac_xface->get_eNB_UE_stats(module_idP, CC_id, rnti)==NULL) {
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// mac_remove_ue(module_idP, i, frameP, subframeP);
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// mac_remove_ue(module_idP, i, frameP, subframeP);
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@@ -873,7 +873,14 @@ void schedule_ulsch_rnti(module_id_t module_idP,
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UE_template->ul_SR = 0;
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UE_template->ul_SR = 0;
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aggregation = process_ue_cqi(module_idP,UE_id); // =2 by default!!
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aggregation = process_ue_cqi(module_idP,UE_id); // =2 by default!!
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status = mac_eNB_get_rrc_status(module_idP,rnti);
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status = mac_eNB_get_rrc_status(module_idP,rnti);
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cqi_req = (status < RRC_CONNECTED)? 0:1;
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if (status < RRC_CONNECTED)
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cqi_req = 0;
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else if (UE_list->UE_sched_ctrl[UE_id].cqi_req_timer>30) {
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cqi_req = 1;
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UE_list->UE_sched_ctrl[UE_id].cqi_req_timer=0;
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}
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else
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cqi_req = 0;
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//power control
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//power control
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//compute the expected ULSCH RX power (for the stats)
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//compute the expected ULSCH RX power (for the stats)
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@@ -918,7 +925,9 @@ void schedule_ulsch_rnti(module_id_t module_idP,
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UE_list->eNB_UE_stats[CC_id][UE_id].target_rx_power=target_rx_power;
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UE_list->eNB_UE_stats[CC_id][UE_id].target_rx_power=target_rx_power;
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UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1=UE_template->pre_assigned_mcs_ul;
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UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1=UE_template->pre_assigned_mcs_ul;
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mcs = cmin (UE_template->pre_assigned_mcs_ul, openair_daq_vars.target_ue_ul_mcs); // adjust, based on user-defined MCS
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mcs = cmin (UE_template->pre_assigned_mcs_ul, openair_daq_vars.target_ue_ul_mcs); // adjust, based on user-defined MCS
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if ((cqi_req==1) && (mcs==20)) {
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mcs=19;
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}
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if (UE_template->pre_allocated_rb_table_index_ul >=0) {
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if (UE_template->pre_allocated_rb_table_index_ul >=0) {
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rb_table_index=UE_template->pre_allocated_rb_table_index_ul;
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rb_table_index=UE_template->pre_allocated_rb_table_index_ul;
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} else {
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} else {
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@@ -318,7 +318,7 @@ static LTE_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs];
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int multi_thread=1;
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int multi_thread=1;
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uint32_t target_dl_mcs = 28; //maximum allowed mcs
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uint32_t target_dl_mcs = 28; //maximum allowed mcs
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uint32_t target_ul_mcs = 19;
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uint32_t target_ul_mcs = 20;
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uint32_t timing_advance = 0;
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uint32_t timing_advance = 0;
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uint8_t exit_missed_slots=1;
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uint8_t exit_missed_slots=1;
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uint64_t num_missed_slots=0; // counter for the number of missed slots
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uint64_t num_missed_slots=0; // counter for the number of missed slots
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