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Nfapi struct corrections/ DCI interface/ Phytest scheduler type 1

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This commit is contained in:
Guy De Souza
2018-07-27 15:25:51 +02:00
parent 45db11de94
commit b387b2034e
16 changed files with 295 additions and 211 deletions
Download Patch File Download Diff File Expand all files Collapse all files
openair1/PHY/INIT/nr_init.c
-1
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@@ -20,7 +20,6 @@
*/
#include "PHY/defs_gNB.h"
#include "SCHED/sched_eNB.h"
#include "PHY/phy_extern.h"
#include "PHY/NR_REFSIG/nr_refsig.h"
#include "PHY/INIT/phy_init.h"
openair1/PHY/NR_TRANSPORT/nr_dci.c
+3 -3
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@@ -173,7 +173,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
/// DMRS QPSK modulation
/*There is a need to shift from which index the pregenerated DMRS sequence is used
* see 38211 r15.2.0 section 7.4.1.3.2: assumption is the reference point for k refers to the DMRS sequence*/
if (pdcch_params.config_type == nr_cset_config_pdcch_config)
if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG)
gold_pdcch_dmrs += ((int)floor(frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_params.rb_offset)*3/32;
for (int i=0; i<NR_MAX_PDCCH_DMRS_LENGTH>>1; i++) {
@@ -219,7 +219,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
if (cset_start_sc >= frame_parms.ofdm_symbol_size)
cset_start_sc -= frame_parms.ofdm_symbol_size;
if (pdcch_params.precoder_granularity == nr_cset_same_as_reg_bundle) {
if (pdcch_params.precoder_granularity == NFAPI_NR_CSET_SAME_AS_REG_BUNDLE) {
for (int cce_idx=0; cce_idx<dci_alloc.L; cce_idx++){
cce = dci_alloc.cce_list[cce_idx];
@@ -247,7 +247,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
}
}
else { //nr_cset_all_contiguous_rbs
else { //NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS
}
}
openair1/PHY/NR_TRANSPORT/nr_dci.h
-47
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@@ -25,53 +25,6 @@
#include "PHY/defs_gNB.h"
#include "PHY/NR_REFSIG/nr_refsig.h"
typedef enum {
nr_dci_format_0_0=0,
nr_dci_format_0_1,
nr_dci_format_2_0,
nr_dci_format_2_1,
nr_dci_format_2_2,
nr_dci_format_2_3,
nr_dci_format_1_0,
nr_dci_format_1_1,
} nr_dci_format_e;
typedef enum {
nr_rnti_type_SI_RNTI=0,
nr_rnti_type_RA_RNTI,
nr_rnti_type_C_RNTI,
nr_rnti_type_TC_RNTI,
nr_rnti_type_CS_RNTI,
nr_rnti_type_P_RNTI
} nr_rnti_type_e;
typedef struct {
uint8_t param_O;
uint8_t param_M;
uint8_t nb_ss_sets_per_slot;
uint8_t first_symbol_idx;
} nr_pdcch_ss_params_t;
typedef struct {
uint8_t n_rb;
uint8_t n_symb;
uint8_t rb_offset;
nr_cce_reg_mapping_type_e cr_mapping_type;
nr_ssb_and_cset_mux_pattern_type_e mux_pattern;
nr_coreset_precoder_granularity_type_e precoder_granularity;
nr_coreset_config_type_e config_type;
} nr_pdcch_coreset_params_t;
typedef struct {
uint8_t first_slot;
uint8_t nb_slots;
uint8_t sfn_mod2;
uint32_t dmrs_scrambling_id;
nr_cce_t cce_list[NR_MAX_PDCCH_AGG_LEVEL];
nr_pdcch_ss_params_t ss_params;
nr_pdcch_coreset_params_t coreset_params;
} nr_pdcch_vars_t;
typedef unsigned __int128 uint128_t;
uint8_t nr_get_dci_size(nfapi_nr_dci_format_e format,
openair1/PHY/defs_gNB.h
+1
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@@ -292,6 +292,7 @@ typedef struct PHY_VARS_gNB_s {
Sched_Rsp_t Sched_INFO;
NR_gNB_PDCCH pdcch_vars;
nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_type0_params;
LTE_eNB_PHICH phich_vars[2];
NR_gNB_COMMON common_vars;
openair1/PHY/defs_nr_common.h
-21
View File
@@ -112,27 +112,6 @@ typedef struct NR_BWP_PARMS {
uint16_t ofdm_symbol_size;
} NR_BWP_PARMS;
typedef enum {
nr_ssb_and_cset_mux_pattern_type_1=0,
nr_ssb_and_cset_mux_pattern_type_2,
nr_ssb_and_cset_mux_pattern_type_3
} nr_ssb_and_cset_mux_pattern_type_e;
typedef enum {
nr_cce_reg_mapping_interleaved=0,
nr_cce_reg_mapping_non_interleaved
} nr_cce_reg_mapping_type_e;
typedef enum {
nr_cset_config_mib_sib1=0,
nr_cset_config_pdcch_config
} nr_coreset_config_type_e;
typedef enum {
nr_cset_same_as_reg_bundle=0,
nr_cset_all_contiguous_rbs
} nr_coreset_precoder_granularity_type_e;
typedef struct {
uint8_t reg_idx;
uint8_t start_sc_idx;
openair1/SCHED_NR/fapi_nr_l1.c
+1 -1
View File
@@ -61,7 +61,7 @@ void handle_nfapi_nr_dci_dl_pdu(PHY_VARS_gNB *gNB,
{
int idx = subframe&1;
NR_gNB_PDCCH *pdcch_vars = &gNB->pdcch_vars;
nfapi_nr_dl_config_dci_pdu_rel15_t *pdu = &dl_config_pdu->dci_dl_pdu_rel15;
nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu = &dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel15;
LOG_D(PHY,"Frame %d, Subframe %d: DCI processing - populating pdcch_vars->dci_alloc[%d] proc:subframe_tx:%d idx:%d pdcch_vars->num_dci:%d\n",frame,subframe, pdcch_vars->num_dci, proc->subframe_tx, idx, pdcch_vars->num_dci);
openair1/SCHED_NR/phy_procedures_nr_common.c
+44 -52
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@@ -60,25 +60,29 @@ nr_subframe_t nr_subframe_select(nfapi_nr_config_request_t *cfg,unsigned char su
}
void nr_get_pdcch_vars_from_mib(nr_pdcch_vars_t *pdcch_vars,
nr_scs_e scs_common,
nr_scs_e pdcch_scs,
nr_frequency_range_e freq_range,
uint8_t rmsi_pdcch_config,
uint16_t N_RB)
void nr_configure_css_dci_from_mib(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
nr_scs_e scs_common,
nr_scs_e pdcch_scs,
nr_frequency_range_e freq_range,
uint8_t rmsi_pdcch_config,
uint8_t ssb_idx,
uint16_t nb_slots_per_frame,
uint16_t N_RB)
{
nr_pdcch_coreset_params_t *coreset_params = &pdcch_vars->coreset_params;
nr_pdcch_ss_params_t *ss_params = &pdcch_vars->ss_params;
uint8_t O, M;
uint8_t ss_idx = rmsi_pdcch_config&0xf;
uint8_t cset_idx = (rmsi_pdcch_config>>4)&0xf;
uint8_t mu;
/// Coreset params
switch(scs_common) {
case kHz15:
mu = 0;
break;
case kHz30:
mu = 1;
if (N_RB < 106) { // Minimum 40Mhz bandwidth not satisfied
switch(pdcch_scs) {
@@ -86,10 +90,10 @@ void nr_get_pdcch_vars_from_mib(nr_pdcch_vars_t *pdcch_vars,
break;
case kHz30:
coreset_params->mux_pattern = nr_ssb_and_cset_mux_pattern_type_1;
coreset_params->n_rb = (cset_idx < 10)? 24 : 48;
coreset_params->n_symb = nr_coreset_nsymb_pdcch_type_0_b40Mhz[cset_idx];
coreset_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_b40Mhz[cset_idx];
pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
pdcch_params->n_rb = (cset_idx < 10)? 24 : 48;
pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_b40Mhz[cset_idx];
pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_b40Mhz[cset_idx];
break;
default:
@@ -104,10 +108,10 @@ void nr_get_pdcch_vars_from_mib(nr_pdcch_vars_t *pdcch_vars,
break;
case kHz30:
coreset_params->mux_pattern = nr_ssb_and_cset_mux_pattern_type_1;
coreset_params->n_rb = (cset_idx < 4)? 24 : 48;
coreset_params->n_symb = nr_coreset_nsymb_pdcch_type_0_b40Mhz[cset_idx];
coreset_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_b40Mhz[cset_idx];
pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1;
pdcch_params->n_rb = (cset_idx < 4)? 24 : 48;
pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_b40Mhz[cset_idx];
pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_b40Mhz[cset_idx];
break;
default:
@@ -116,9 +120,11 @@ void nr_get_pdcch_vars_from_mib(nr_pdcch_vars_t *pdcch_vars,
}
case kHz60:
mu = 2;
break;
case kHz120:
mu = 3;
break;
default:
@@ -127,60 +133,46 @@ void nr_get_pdcch_vars_from_mib(nr_pdcch_vars_t *pdcch_vars,
}
/// Search space params
switch(coreset_params->mux_pattern) {
switch(pdcch_params->mux_pattern) {
case nr_ssb_and_cset_mux_pattern_type_1:
case NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1:
if (freq_range == nr_FR1) {
ss_params->param_O = nr_ss_param_O_type_0_mux1_FR1[ss_idx];
ss_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR1[ss_idx];
ss_params->param_M = nr_ss_param_M_type_0_mux1_FR1[ss_idx];
ss_params->first_symbol_idx = (ss_idx < 8)? ( (ss_idx&1)? coreset_params->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ss_idx - 8];
O = nr_ss_param_O_type_0_mux1_FR1[ss_idx];
pdcch_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR1[ss_idx];
M = nr_ss_param_M_type_0_mux1_FR1[ss_idx];
pdcch_params->first_symbol = (ss_idx < 8)? ( (ss_idx&1)? pdcch_params->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ss_idx - 8];
}
else {
AssertFatal(ss_idx<14 ,"Invalid search space index for multiplexing type 1 and FR2 %d\n", ss_idx);
ss_params->param_O = nr_ss_param_O_type_0_mux1_FR2[ss_idx];
ss_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR2[ss_idx];
ss_params->param_M = nr_ss_param_M_type_0_mux1_FR2[ss_idx];
ss_params->first_symbol_idx = (ss_idx < 12)? ( (ss_idx&1)? 7 : 0 ) : 0;
O = nr_ss_param_O_type_0_mux1_FR2[ss_idx];
pdcch_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR2[ss_idx];
M = nr_ss_param_M_type_0_mux1_FR2[ss_idx];
pdcch_params->first_symbol = (ss_idx < 12)? ( (ss_idx&1)? 7 : 0 ) : 0;
}
pdcch_params->nb_slots = 2;
pdcch_params->sfn_mod2 = ((uint8_t)(floor( (O*pow(2, mu) + floor(ssb_idx*M)) / nb_slots_per_frame )) & 1)? 1 : 0;
pdcch_params->first_slot = (uint8_t)(O*pow(2, mu) + floor(ssb_idx*M)) % nb_slots_per_frame;
break;
case nr_ssb_and_cset_mux_pattern_type_2:
case NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2:
break;
case nr_ssb_and_cset_mux_pattern_type_3:
case NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE3:
break;
default:
AssertFatal(1==0, "Invalid SSB and coreset multiplexing pattern %d\n", coreset_params->mux_pattern);
AssertFatal(1==0, "Invalid SSB and coreset multiplexing pattern %d\n", pdcch_params->mux_pattern);
}
pdcch_params->config_type = NFAPI_NR_CSET_CONFIG_MIB_SIB1;
pdcch_params->cr_mapping_type = NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED;
pdcch_params->precoder_granularity = NFAPI_NR_CSET_SAME_AS_REG_BUNDLE;
}
void nr_get_pdcch_type_0_monitoring_period(nr_pdcch_vars_t *pdcch_vars,
uint8_t mu,
uint8_t nb_slots_per_frame,
uint8_t ssb_idx)
{
uint8_t O = pdcch_vars->ss_params.param_O, M = pdcch_vars->ss_params.param_M;
void nr_configure_css_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
nfapi_nr_coreset_t* coreset,
nfapi_nr_search_space_t* search_space) {
if (pdcch_vars->coreset_params.mux_pattern == nr_ssb_and_cset_mux_pattern_type_1) {
pdcch_vars->nb_slots = 2;
pdcch_vars->sfn_mod2 = ((uint8_t)(floor( (O*pow(2, mu) + floor(ssb_idx*M)) / nb_slots_per_frame )) & 1)? 1 : 0;
pdcch_vars->first_slot = (uint8_t)(O*pow(2, mu) + floor(ssb_idx*M)) % nb_slots_per_frame;
}
else { //nr_ssb_and_cset_mux_pattern_type_2, nr_ssb_and_cset_mux_pattern_type_3
pdcch_vars->nb_slots = 1;
}
}
void nr_get_pdcch_vars_from_config(nr_pdcch_vars_t* pdcch_vars,
nfapi_nr_coreset_t* coreset,
nfapi_nr_search_space_t* search_space) {
nr_pdcch_coreset_params_t cset_params = pdcch_vars->coreset_params;
nr_pdcch_ss_params_t ss_params = pdcch_vars->ss_params;
}
openair1/SCHED_NR/sched_nr.h
+8 -10
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@@ -42,15 +42,13 @@ void nr_feptx_ofdm(RU_t *ru);
void nr_feptx_ofdm_2thread(RU_t *ru);
void nr_feptx0(RU_t *ru,int slot);
void nr_get_pdcch_vars_from_mib(nr_pdcch_vars_t *pdcch_vars,
nr_scs_e scs_common,
nr_scs_e pdcch_scs,
nr_frequency_range_e freq_range,
uint8_t rmsi_pdcch_config,
uint16_t N_RB);
void nr_get_pdcch_type_0_monitoring_period(nr_pdcch_vars_t *pdcch_vars,
uint8_t mu,
uint8_t nb_slots_per_frame,
uint8_t ssb_idx);
void nr_configure_css_dci_from_mib(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
nr_scs_e scs_common,
nr_scs_e pdcch_scs,
nr_frequency_range_e freq_range,
uint8_t rmsi_pdcch_config,
uint8_t ssb_idx,
uint16_t nb_slots_per_frame,
uint16_t N_RB);
#endif