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added Timing advance tracing to .vcd output. Increase maximum UL RB count to 45. Measured UL throughput @ 15 Mbit/s (40 PRBs).

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This commit is contained in:
Raymond Knopp
2016-03-18 08:00:51 +01:00
parent 84a1c7377b
commit b441c37b40
6 changed files with 19 additions and 183 deletions
Download Patch File Download Diff File Expand all files Collapse all files
openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
+3 -125
View File
@@ -525,54 +525,6 @@ uint32_t bytes_to_bsr_index(int32_t nbytes)
return(i-1); return(i-1);
} }
/*
void adjust_bsr_info(int buffer_occupancy,
uint16_t TBS,
UE_TEMPLATE *UE_template)
{
uint32_t tmp_bsr;
// could not serve all the uplink traffic
if (buffer_occupancy > 0 ) {
if (BSR_TABLE[UE_template->bsr_info[LCGID0]] <= TBS ) {
tmp_bsr = BSR_TABLE[UE_template->bsr_info[LCGID0]]; // serving this amout of bytes
UE_template->bsr_info[LCGID0] = 0;
if (BSR_TABLE[UE_template->bsr_info[LCGID1]] <= (TBS-tmp_bsr)) {
tmp_bsr += BSR_TABLE[UE_template->bsr_info[LCGID1]];
UE_template->bsr_info[LCGID1] = 0;
if (BSR_TABLE[UE_template->bsr_info[LCGID2]] <= (TBS-tmp_bsr)) {
tmp_bsr += BSR_TABLE[UE_template->bsr_info[LCGID2]];
UE_template->bsr_info[LCGID2] = 0;
if (BSR_TABLE[UE_template->bsr_info[LCGID3]] <= (TBS-tmp_bsr)) {
tmp_bsr += BSR_TABLE[UE_template->bsr_info[LCGID3]];
UE_template->bsr_info[LCGID3] = 0;
} else {
UE_template->bsr_info[LCGID3] = bytes_to_bsr_index((int32_t)BSR_TABLE[UE_template->bsr_info[LCGID3]] - ((int32_t) TBS - (int32_t)tmp_bsr));
}
} else {
UE_template->bsr_info[LCGID2] = bytes_to_bsr_index((int32_t)BSR_TABLE[UE_template->bsr_info[LCGID2]] - ((int32_t)TBS - (int32_t)tmp_bsr));
}
} else {
UE_template->bsr_info[LCGID1] = bytes_to_bsr_index((int32_t)BSR_TABLE[UE_template->bsr_info[LCGID1]] - ((int32_t)TBS - (int32_t)tmp_bsr));
}
} else {
UE_template->bsr_info[LCGID0] = bytes_to_bsr_index((int32_t)BSR_TABLE[UE_template->bsr_info[LCGID0]] - (int32_t)TBS);
}
} else { // we have flushed all buffers so clear bsr
UE_template->bsr_info[LCGID0] = 0;
UE_template->bsr_info[LCGID1] = 0;
UE_template->bsr_info[LCGID2] = 0;
UE_template->bsr_info[LCGID3] = 0;
}
}
*/
void add_ue_ulsch_info(module_id_t module_idP, int CC_id, int UE_id, sub_frame_t subframeP, UE_ULSCH_STATUS status) void add_ue_ulsch_info(module_id_t module_idP, int CC_id, int UE_id, sub_frame_t subframeP, UE_ULSCH_STATUS status)
{ {
@@ -584,66 +536,6 @@ void add_ue_ulsch_info(module_id_t module_idP, int CC_id, int UE_id, sub_frame_t
} }
// This seems not to be used anymore
/*
int schedule_next_ulue(module_id_t module_idP, int UE_id, sub_frame_t subframeP){
int next_ue;
// first phase: scheduling for ACK
switch (subframeP) {
// scheduling for subframeP 2: for scheduled user during subframeP 5 and 6
case 8:
if ((eNB_dlsch_info[module_idP][UE_id].status == S_DL_SCHEDULED) &&
(eNB_dlsch_info[module_idP][UE_id].subframe == 5 || eNB_dlsch_info[module_idP][UE_id].subframe == 6)){
// set the downlink status
eNB_dlsch_info[module_idP][UE_id].status = S_DL_BUFFERED;
return UE_id;
}
break;
// scheduling for subframeP 3: for scheduled user during subframeP 7 and 8
case 9:
if ((eNB_dlsch_info[module_idP][UE_id].status == S_DL_SCHEDULED) &&
(eNB_dlsch_info[module_idP][UE_id].subframe == 7 || eNB_dlsch_info[module_idP][UE_id].subframe == 8)){
eNB_dlsch_info[module_idP][UE_id].status = S_DL_BUFFERED;
return UE_id;
}
break;
// scheduling UL subframeP 4: for scheduled user during subframeP 9 and 0
case 0 :
if ((eNB_dlsch_info[module_idP][UE_id].status == S_DL_SCHEDULED) &&
(eNB_dlsch_info[module_idP][UE_id].subframe == 9 || eNB_dlsch_info[module_idP][UE_id].subframe == 0)){
eNB_dlsch_info[module_idP][UE_id].status = S_DL_BUFFERED;
return UE_id;
}
break;
default:
break;
}
// second phase
for (next_ue=0; next_ue <NUMBER_OF_UE_MAX; next_ue++ ){
if (eNB_ulsch_info[module_idP][next_ue].status == S_UL_WAITING )
return next_ue;
else if (eNB_ulsch_info[module_idP][next_ue].status == S_UL_SCHEDULED){
eNB_ulsch_info[module_idP][next_ue].status = S_UL_BUFFERED;
}
}
for (next_ue=0; next_ue <NUMBER_OF_UE_MAX; next_ue++ ){
if (eNB_ulsch_info[module_idP][next_ue].status != S_UL_NONE )// do this just for active UEs
eNB_ulsch_info[module_idP][next_ue].status = S_UL_WAITING;
}
next_ue = 0;
return next_ue;
}
*/
unsigned char *parse_ulsch_header(unsigned char *mac_header, unsigned char *parse_ulsch_header(unsigned char *mac_header,
unsigned char *num_ce, unsigned char *num_ce,
unsigned char *num_sdu, unsigned char *num_sdu,
@@ -957,7 +849,7 @@ void schedule_ulsch_rnti(module_id_t module_idP,
// buffer_occupancy = UE_template->ul_total_buffer; // buffer_occupancy = UE_template->ul_total_buffer;
while (((rb_table[rb_table_index]>(frame_parms->N_RB_UL-1-first_rb[CC_id])) || while (((rb_table[rb_table_index]>(frame_parms->N_RB_UL-1-first_rb[CC_id])) ||
(rb_table[rb_table_index]>39)) && (rb_table[rb_table_index]>45)) &&
(rb_table_index>0)) { (rb_table_index>0)) {
rb_table_index--; rb_table_index--;
} }
@@ -984,12 +876,6 @@ void schedule_ulsch_rnti(module_id_t module_idP,
first_rb[CC_id],rb_table[rb_table_index], first_rb[CC_id],rb_table[rb_table_index],
rb_table_index,TBS,harq_pid); rb_table_index,TBS,harq_pid);
/*
// Adjust BSR entries for LCGIDs
adjust_bsr_info(buffer_occupancy,
TBS,
UE_template);
*/
// adjust total UL buffer status by TBS, wait for UL sdus to do final update // adjust total UL buffer status by TBS, wait for UL sdus to do final update
LOG_D(MAC,"[eNB %d] CC_id %d UE %d/%x : adjusting ul_total_buffer, old %d, TBS %d\n", module_idP,CC_id,UE_id,rnti,UE_template->ul_total_buffer,TBS); LOG_D(MAC,"[eNB %d] CC_id %d UE %d/%x : adjusting ul_total_buffer, old %d, TBS %d\n", module_idP,CC_id,UE_id,rnti,UE_template->ul_total_buffer,TBS);
if (UE_template->ul_total_buffer > TBS) if (UE_template->ul_total_buffer > TBS)
@@ -998,16 +884,8 @@ void schedule_ulsch_rnti(module_id_t module_idP,
UE_template->ul_total_buffer = 0; UE_template->ul_total_buffer = 0;
LOG_D(MAC,"ul_total_buffer, new %d\n", UE_template->ul_total_buffer); LOG_D(MAC,"ul_total_buffer, new %d\n", UE_template->ul_total_buffer);
// Cyclic shift for DM RS // Cyclic shift for DM RS
if(cooperation_flag == 2) { cshift = 0;// values from 0 to 7 can be used for mapping the cyclic shift (36.211 , Table 5.5.2.1.1-1)
if(UE_id == 1) { // For Distriibuted Alamouti, cyclic shift applied to 2nd UE
cshift = 1;
} else {
cshift = 0;
}
} else {
cshift = 0;// values from 0 to 7 can be used for mapping the cyclic shift (36.211 , Table 5.5.2.1.1-1)
}
if (frame_parms->frame_type == TDD) { if (frame_parms->frame_type == TDD) {
switch (frame_parms->N_RB_UL) { switch (frame_parms->N_RB_UL) {
case 6: case 6:
openair2/LAYER2/MAC/pre_processor.c
+4 -48
View File
@@ -47,6 +47,7 @@
#include "LAYER2/MAC/proto.h" #include "LAYER2/MAC/proto.h"
#include "LAYER2/MAC/extern.h" #include "LAYER2/MAC/extern.h"
#include "UTIL/LOG/log.h" #include "UTIL/LOG/log.h"
#include "UTIL/LOG/vcd_signal_dumper.h"
#include "UTIL/OPT/opt.h" #include "UTIL/OPT/opt.h"
#include "OCG.h" #include "OCG.h"
#include "OCG_extern.h" #include "OCG_extern.h"
@@ -807,6 +808,9 @@ void dlsch_scheduler_pre_processor_reset (int module_idP,
ue_sched_ctl->ta_timer--; ue_sched_ctl->ta_timer--;
ue_sched_ctl->ta_update =0; // don't trigger a timing advance command ue_sched_ctl->ta_update =0; // don't trigger a timing advance command
} }
if (UE_id==0) {
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_TIMING_ADVANCE,ue_sched_ctl->ta_update);
}
nb_rbs_required[CC_id][UE_id]=0; nb_rbs_required[CC_id][UE_id]=0;
ue_sched_ctl->pre_nb_available_rbs[CC_id] = 0; ue_sched_ctl->pre_nb_available_rbs[CC_id] = 0;
ue_sched_ctl->dl_pow_off[CC_id] = 2; ue_sched_ctl->dl_pow_off[CC_id] = 2;
@@ -937,9 +941,6 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
UE_TEMPLATE *UE_template = 0; UE_TEMPLATE *UE_template = 0;
LTE_DL_FRAME_PARMS *frame_parms = 0; LTE_DL_FRAME_PARMS *frame_parms = 0;
// LOG_I(MAC,"store ulsch buffers\n");
// convert BSR to bytes for comparison with tbs
// store_ulsch_buffer(module_idP,frameP, subframeP);
//LOG_I(MAC,"assign max mcs min rb\n"); //LOG_I(MAC,"assign max mcs min rb\n");
// maximize MCS and then allocate required RB according to the buffer occupancy with the limit of max available UL RB // maximize MCS and then allocate required RB according to the buffer occupancy with the limit of max available UL RB
@@ -1097,51 +1098,6 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
} }
} }
/*
void store_ulsch_buffer(module_id_t module_idP, int frameP, sub_frame_t subframeP)
{
int UE_id,pCC_id,lcgid;
UE_list_t *UE_list = &eNB_mac_inst[module_idP].UE_list;
UE_TEMPLATE *UE_template;
for (UE_id=UE_list->head_ul; UE_id>=0; UE_id=UE_list->next_ul[UE_id]) {
if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1)
continue;
UE_template = &UE_list->UE_template[UE_PCCID(module_idP,UE_id)][UE_id];
//LOG_I(MAC,"[UE %d next %d] SR is %d\n",UE_id, UE_list->next_ul[UE_id], UE_template->ul_SR);
UE_template->ul_total_buffer=0;
for (lcgid=0; lcgid<MAX_NUM_LCGID; lcgid++) {
UE_template->ul_buffer_info[lcgid]=BSR_TABLE[UE_template->bsr_info[lcgid]];
UE_template->ul_total_buffer+= UE_template->ul_buffer_info[lcgid]; // apply traffic aggregtaion if packets are small
// UE_template->ul_buffer_creation_time_max=cmax(UE_template->ul_buffer_creation_time_max, frame_cycle*1024 + frameP-UE_template->ul_buffer_creation_time[lcgid]));
}
if ( UE_template->ul_total_buffer >0)
LOG_D(MAC,"[eNB %d] Frame %d subframe %d UE %d CC id %d: LCGID0 %d, LCGID1 %d, LCGID2 %d LCGID3 %d, BO %d\n",
module_idP, frameP,subframeP, UE_id, UE_PCCID(module_idP,UE_id),
UE_template->ul_buffer_info[LCGID0],
UE_template->ul_buffer_info[LCGID1],
UE_template->ul_buffer_info[LCGID2],
UE_template->ul_buffer_info[LCGID3],
UE_template->ul_total_buffer);
else if (UE_is_to_be_scheduled(module_idP,UE_PCCID(module_idP,UE_id),UE_id) > 0 ) {
if (UE_template->ul_total_buffer == 0 ) {
UE_template->ul_total_buffer = BSR_TABLE[11];
}
LOG_D(MAC,"[eNB %d] Frame %d subframe %d UE %d CC id %d: SR active, set BO to %d \n",
module_idP, frameP,subframeP, UE_id, UE_PCCID(module_idP,UE_id),
UE_template->ul_total_buffer);
}
}
}
*/
void assign_max_mcs_min_rb(module_id_t module_idP,int frameP, sub_frame_t subframeP, uint16_t *first_rb) void assign_max_mcs_min_rb(module_id_t module_idP,int frameP, sub_frame_t subframeP, uint16_t *first_rb)
openair2/UTIL/LOG/vcd_signal_dumper.c
+1
View File
@@ -122,6 +122,7 @@ const char* eurecomVariablesNames[] = {
"ue0_BSR", "ue0_BSR",
"ue0_BO", "ue0_BO",
"ue0_scheduled", "ue0_scheduled",
"ue0_timing_advance",
"ue0_SR_ENERGY", "ue0_SR_ENERGY",
"ue0_SR_THRES", "ue0_SR_THRES",
"ue0_rssi0", "ue0_rssi0",
openair2/UTIL/LOG/vcd_signal_dumper.h
+1
View File
@@ -94,6 +94,7 @@ typedef enum {
VCD_SIGNAL_DUMPER_VARIABLES_UE0_BSR, VCD_SIGNAL_DUMPER_VARIABLES_UE0_BSR,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_BO, VCD_SIGNAL_DUMPER_VARIABLES_UE0_BO,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_SCHEDULED, VCD_SIGNAL_DUMPER_VARIABLES_UE0_SCHEDULED,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_TIMING_ADVANCE,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_SR_ENERGY, VCD_SIGNAL_DUMPER_VARIABLES_UE0_SR_ENERGY,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_SR_THRES, VCD_SIGNAL_DUMPER_VARIABLES_UE0_SR_THRES,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_RSSI0, VCD_SIGNAL_DUMPER_VARIABLES_UE0_RSSI0,
targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf
+2 -2
View File
@@ -140,10 +140,10 @@ eNBs =
NETWORK_INTERFACES : NETWORK_INTERFACES :
{ {
ENB_INTERFACE_NAME_FOR_S1_MME = "eth0"; ENB_INTERFACE_NAME_FOR_S1_MME = "eth0";
ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.213/24"; ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.215/24";
ENB_INTERFACE_NAME_FOR_S1U = "eth0"; ENB_INTERFACE_NAME_FOR_S1U = "eth0";
ENB_IPV4_ADDRESS_FOR_S1U = "192.168.12.213/24"; ENB_IPV4_ADDRESS_FOR_S1U = "192.168.12.215/24";
ENB_PORT_FOR_S1U = 2152; # Spec 2152 ENB_PORT_FOR_S1U = 2152; # Spec 2152
}; };
targets/RT/USER/eNB_usrp.gtkw
+8 -8
View File
@@ -1,15 +1,15 @@
[*] [*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Mon Mar 14 12:40:13 2016 [*] Thu Mar 17 23:50:10 2016
[*] [*]
[dumpfile] "/tmp/openair_dump_eNB.vcd" [dumpfile] "/tmp/openair_dump_eNB.vcd"
[dumpfile_mtime] "Mon Mar 14 11:08:33 2016" [dumpfile_mtime] "Thu Mar 17 23:49:36 2016"
[dumpfile_size] 54022345 [dumpfile_size] 236045612
[savefile] "/home/abeille/openairinterface5g/targets/RT/USER/eNB_usrp.gtkw" [savefile] "/home/papillon/openairinterface5g/targets/RT/USER/eNB_usrp.gtkw"
[timestart] 12592600000 [timestart] 10372000000
[size] 1535 876 [size] 1535 876
[pos] -1 -1 [pos] -1 -1
*-25.793451 12619679774 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-29.793451 12619679774 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 284 [sst_width] 284
[signals_width] 238 [signals_width] 238
[sst_expanded] 1 [sst_expanded] 1
@@ -54,11 +54,11 @@ functions.phy_procedures_eNb_rx
variables.ue0_BO[63:0] variables.ue0_BO[63:0]
@420 @420
variables.ue0_BSR[63:0] variables.ue0_BSR[63:0]
@421
variables.ue0_timing_advance[63:0]
@28 @28
functions.macxface_initiate_ra_proc functions.macxface_initiate_ra_proc
@29
functions.macxface_terminate_ra_proc functions.macxface_terminate_ra_proc
@28
functions.macxface_SR_indication functions.macxface_SR_indication
@420 @420
variables.ue0_SR_ENERGY[63:0] variables.ue0_SR_ENERGY[63:0]