Merge remote-tracking branch 'origin/NR_UE_SA' into bandwidth-testing

Conflicts:
	executables/nr-ru.c
	openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c
	openair1/SCHED_NR/phy_procedures_nr_gNB.c
	openair2/LAYER2/NR_MAC_gNB/config.c
	openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
	openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
	openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
	openair2/RRC/NR/MESSAGES/asn1_msg.c
	openair2/RRC/NR/nr_rrc_proto.h
	openair2/RRC/NR/rrc_gNB.c
	openair2/RRC/NR/rrc_gNB_reconfig.c
This commit is contained in:
Eurecom
2021-08-21 07:48:04 +02:00
200 changed files with 20133 additions and 20652 deletions
+4
View File
@@ -38,6 +38,8 @@
#include <string.h>
#include <stdbool.h>
#include "NR_SubcarrierSpacing.h"
#define TABLE_38213_13_1_NUM_INDEXES 15
#define TABLE_38213_13_2_NUM_INDEXES 14
#define TABLE_38213_13_3_NUM_INDEXES 9
@@ -452,9 +454,11 @@ typedef struct Type0_PDCCH_CSS_config_s {
uint32_t number_of_search_space_per_slot;
uint32_t first_symbol_index;
uint32_t search_space_duration;
uint32_t search_space_frame_period; // in slots
uint32_t ssb_length;
uint32_t ssb_index;
uint32_t cset_start_rb;
NR_SubcarrierSpacing_t scs_pdcch;
bool active;
} NR_Type0_PDCCH_CSS_config_t;
+691 -137
View File
@@ -36,6 +36,19 @@
#define reserved 0xffff
void reverse_n_bits(uint8_t *value, uint16_t bitlen) {
uint16_t j;
uint8_t i;
for(j = bitlen - 1,i = 0; j > i; j--, i++) {
if(((*value>>j)&1) != ((*value>>i)&1)) {
*value ^= (1<<j);
*value ^= (1<<i);
}
}
}
// start symbols for SSB types A,B,C,D,E
uint16_t symbol_ssb_AC[8]={2,8,16,22,30,36,44,50};
uint16_t symbol_ssb_BD[64]={4,8,16,20,32,36,44,48,60,64,72,76,88,92,100,104,144,148,156,160,172,176,184,188,200,204,212,216,228,232,240,244,284,288,
@@ -126,151 +139,225 @@ const float table_38213_13_12_c3[16] = { 1, 0.5f, 1, 0.5f, 1, 0.5f, 0.5f, 0.5f
const int32_t table_38213_10_1_1_c2[5] = { 0, 0, 4, 2, 1 };
// for PDSCH from TS 38.214 subclause 5.1.2.1.1
const uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2[16][3]={
{0,2,12}, // row index 1
{0,2,10}, // row index 2
{0,2,9}, // row index 3
{0,2,7}, // row index 4
{0,2,5}, // row index 5
{0,9,4}, // row index 6
{0,4,4}, // row index 7
{0,5,7}, // row index 8
{0,5,2}, // row index 9
{0,9,2}, // row index 10
{0,12,2}, // row index 11
{0,1,13}, // row index 12
{0,1,6}, // row index 13
{0,2,4}, // row index 14
{0,4,7}, // row index 15
{0,8,4} // row index 16
const uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2[16][4]={
{1,0,2,12}, // row index 1
{1,0,2,10}, // row index 2
{1,0,2,9}, // row index 3
{1,0,2,7}, // row index 4
{1,0,2,5}, // row index 5
{0,0,9,4}, // row index 6
{0,0,4,4}, // row index 7
{0,0,5,7}, // row index 8
{0,0,5,2}, // row index 9
{0,0,9,2}, // row index 10
{0,0,12,2}, // row index 11
{1,0,1,13}, // row index 12
{1,0,1,6}, // row index 13
{1,0,2,4}, // row index 14
{0,0,4,7}, // row index 15
{0,0,8,4} // row index 16
};
const uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3[16][3]={
{0,3,11}, // row index 1
{0,3,9}, // row index 2
{0,3,8}, // row index 3
{0,3,6}, // row index 4
{0,3,4}, // row index 5
{0,10,4}, // row index 6
{0,6,4}, // row index 7
{0,5,7}, // row index 8
{0,5,2}, // row index 9
{0,9,2}, // row index 10
{0,12,2}, // row index 11
{0,1,13}, // row index 12
{0,1,6}, // row index 13
{0,2,4}, // row index 14
{0,4,7}, // row index 15
{0,8,4} // row index 16
const uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3[16][4]={
{1,0,3,11}, // row index 1
{1,0,3,9}, // row index 2
{1,0,3,8}, // row index 3
{1,0,3,6}, // row index 4
{1,0,3,4}, // row index 5
{0,0,10,4}, // row index 6
{0,0,6,4}, // row index 7
{0,0,5,7}, // row index 8
{0,0,5,2}, // row index 9
{0,0,9,2}, // row index 10
{0,0,12,2}, // row index 11
{1,0,1,13}, // row index 12
{1,0,1,6}, // row index 13
{1,0,2,4}, // row index 14
{0,0,4,7}, // row index 15
{0,0,8,4} // row index 16
};
const uint8_t table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos2[16][3]={
{0,2,6}, // row index 1
{0,2,10}, // row index 2
{0,2,9}, // row index 3
{0,2,7}, // row index 4
{0,2,5}, // row index 5
{0,6,4}, // row index 6
{0,4,4}, // row index 7
{0,5,6}, // row index 8
{0,5,2}, // row index 9
{0,9,2}, // row index 10
{0,10,2}, // row index 11
{0,1,11}, // row index 12
{0,1,6}, // row index 13
{0,2,4}, // row index 14
{0,4,6}, // row index 15
{0,8,4} // row index 16
const uint8_t table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos2[16][4]={
{1,0,2,6}, // row index 1
{1,0,2,10}, // row index 2
{1,0,2,9}, // row index 3
{1,0,2,7}, // row index 4
{1,0,2,5}, // row index 5
{0,0,6,4}, // row index 6
{0,0,4,4}, // row index 7
{0,0,5,6}, // row index 8
{0,0,5,2}, // row index 9
{0,0,9,2}, // row index 10
{0,0,10,2}, // row index 11
{1,0,1,11}, // row index 12
{1,0,1,6}, // row index 13
{1,0,2,4}, // row index 14
{0,0,4,6}, // row index 15
{0,0,8,4} // row index 16
};
const uint8_t table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos3[16][3]={
{0,3,5}, // row index 1
{0,3,9}, // row index 2
{0,3,8}, // row index 3
{0,3,6}, // row index 4
{0,3,4}, // row index 5
{0,8,2}, // row index 6
{0,6,4}, // row index 7
{0,5,6}, // row index 8
{0,5,2}, // row index 9
{0,9,2}, // row index 10
{0,10,2}, // row index 11
{0,1,11}, // row index 12
{0,1,6}, // row index 13
{0,2,4}, // row index 14
{0,4,6}, // row index 15
{0,8,4} // row index 16
const uint8_t table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos3[16][4]={
{1,0,3,5}, // row index 1
{1,0,3,9}, // row index 2
{1,0,3,8}, // row index 3
{1,0,3,6}, // row index 4
{1,0,3,4}, // row index 5
{0,0,8,2}, // row index 6
{0,0,6,4}, // row index 7
{0,0,5,6}, // row index 8
{0,0,5,2}, // row index 9
{0,0,9,2}, // row index 10
{0,0,10,2}, // row index 11
{1,0,1,11}, // row index 12
{1,0,1,6}, // row index 13
{1,0,2,4}, // row index 14
{0,0,4,6}, // row index 15
{0,0,8,4} // row index 16
};
const uint8_t table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos2[16][3]={
{0,2,2}, // row index 1
{0,4,2}, // row index 2
{0,6,2}, // row index 3
{0,8,2}, // row index 4
{0,10,2}, // row index 5
{1,2,2}, // row index 6
{1,4,2}, // row index 7
{0,2,4}, // row index 8
{0,4,4}, // row index 9
{0,6,4}, // row index 10
{0,8,4}, // row index 11
{0,10,4}, // row index 12
{0,2,7}, // row index 13
{0,2,12}, // row index 14
{1,2,4}, // row index 15
{0,0,0} // row index 16
const uint8_t table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos2[16][4]={
{0,0,2,2}, // row index 1
{0,0,4,2}, // row index 2
{0,0,6,2}, // row index 3
{0,0,8,2}, // row index 4
{0,0,10,2}, // row index 5
{0,1,2,2}, // row index 6
{0,1,4,2}, // row index 7
{0,0,2,4}, // row index 8
{0,0,4,4}, // row index 9
{0,0,6,4}, // row index 10
{0,0,8,4}, // row index 11
{0,0,10,4}, // row index 12
{0,0,2,7}, // row index 13
{1,0,2,12}, // row index 14
{0,1,2,4}, // row index 15
{0,0,0,0} // row index 16
};
const uint8_t table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos3[16][3]={
{0,2,2}, // row index 1
{0,4,2}, // row index 2
{0,6,2}, // row index 3
{0,8,2}, // row index 4
{0,10,2}, // row index 5
{1,2,2}, // row index 6
{1,4,2}, // row index 7
{0,2,4}, // row index 8
{0,4,4}, // row index 9
{0,6,4}, // row index 10
{0,8,4}, // row index 11
{0,10,4}, // row index 12
{0,2,7}, // row index 13
{0,3,11}, // row index 14
{1,2,4}, // row index 15
{0,0,0} // row index 16
const uint8_t table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos3[16][4]={
{0,0,2,2}, // row index 1
{0,0,4,2}, // row index 2
{0,0,6,2}, // row index 3
{0,0,8,2}, // row index 4
{0,0,10,2}, // row index 5
{0,1,2,2}, // row index 6
{0,1,4,2}, // row index 7
{0,0,2,4}, // row index 8
{0,0,4,4}, // row index 9
{0,0,6,4}, // row index 10
{0,0,8,4}, // row index 11
{0,0,10,4}, // row index 12
{0,0,2,7}, // row index 13
{1,0,3,11}, // row index 14
{0,1,2,4}, // row index 15
{0,0,0,0} // row index 16
};
const uint8_t table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos2[16][3]={
{0,2,2}, // row index 1
{0,4,2}, // row index 2
{0,6,2}, // row index 3
{0,8,2}, // row index 4
{0,10,2}, // row index 5
{0,0,0}, // row index 6
{0,0,0}, // row index 7
{0,2,4}, // row index 8
{0,4,4}, // row index 9
{0,6,4}, // row index 10
{0,8,4}, // row index 11
{0,10,4}, // row index 12
{0,2,7}, // row index 13
{0,2,12}, // row index 14
{0,0,6}, // row index 15
{0,2,6} // row index 16
const uint8_t table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos2[16][4]={
{0,0,2,2}, // row index 1
{0,0,4,2}, // row index 2
{0,0,6,2}, // row index 3
{0,0,8,2}, // row index 4
{0,0,10,2}, // row index 5
{0,0,0,0}, // row index 6
{0,0,0,0}, // row index 7
{0,0,2,4}, // row index 8
{0,0,4,4}, // row index 9
{0,0,6,4}, // row index 10
{0,0,8,4}, // row index 11
{0,0,10,4}, // row index 12
{0,0,2,7}, // row index 13
{1,0,2,12}, // row index 14
{1,0,0,6}, // row index 15
{1,0,2,6} // row index 16
};
const uint8_t table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos3[16][3]={
{0,2,2}, // row index 1
{0,4,2}, // row index 2
{0,6,2}, // row index 3
{0,8,2}, // row index 4
{0,10,2}, // row index 5
{0,0,0}, // row index 6
{0,0,0}, // row index 7
{0,2,4}, // row index 8
{0,4,4}, // row index 9
{0,6,4}, // row index 10
{0,8,4}, // row index 11
{0,10,4}, // row index 12
{0,2,7}, // row index 13
{0,3,11}, // row index 14
{0,0,6}, // row index 15
{0,2,6} // row index 16
const uint8_t table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos3[16][4]={
{0,0,2,2}, // row index 1
{0,0,4,2}, // row index 2
{0,0,6,2}, // row index 3
{0,0,8,2}, // row index 4
{0,0,10,2}, // row index 5
{0,0,0,0}, // row index 6
{0,0,0,0}, // row index 7
{0,0,2,4}, // row index 8
{0,0,4,4}, // row index 9
{0,0,6,4}, // row index 10
{0,0,8,4}, // row index 11
{0,0,10,4}, // row index 12
{0,0,2,7}, // row index 13
{1,0,3,11}, // row index 14
{1,0,0,6}, // row index 15
{1,0,2,6} // row index 16
};
void get_info_from_tda_tables(int default_abc,
int tda,
int dmrs_TypeA_Position,
int normal_CP,
int *startSymbolIndex,
int *nrOfSymbols) {
int k0 = 0;
int is_mapping_typeA = 1;
switch(default_abc){
case 1:
if (normal_CP){
if (dmrs_TypeA_Position){
is_mapping_typeA = table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3[tda][0];
k0 = table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3[tda][1];
*startSymbolIndex = table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3[tda][2];
*nrOfSymbols = table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3[tda][3];
}
else{
is_mapping_typeA = table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2[tda][0];
k0 = table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2[tda][1];
*startSymbolIndex = table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2[tda][2];
*nrOfSymbols = table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2[tda][3];
}
}
else{
if (dmrs_TypeA_Position){
is_mapping_typeA = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos3[tda][0];
k0 = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos3[tda][1];
*startSymbolIndex = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos3[tda][2];
*nrOfSymbols = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos3[tda][3];
}
else{
is_mapping_typeA = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos2[tda][0];
k0 = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos2[tda][1];
*startSymbolIndex = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos2[tda][2];
*nrOfSymbols = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos2[tda][3];
}
}
break;
case 2:
if (dmrs_TypeA_Position){
is_mapping_typeA = table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos3[tda][0];
k0 = table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos3[tda][1];
*startSymbolIndex = table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos3[tda][2];
*nrOfSymbols = table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos3[tda][3];
}
else{
is_mapping_typeA = table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos2[tda][0];
k0 = table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos2[tda][1];
*startSymbolIndex = table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos2[tda][2];
*nrOfSymbols = table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos2[tda][3];
}
break;
case 3:
if (dmrs_TypeA_Position){
is_mapping_typeA = table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos3[tda][0];
k0 = table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos3[tda][1];
*startSymbolIndex = table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos3[tda][2];
*nrOfSymbols = table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos3[tda][3];
}
else{
is_mapping_typeA = table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos2[tda][0];
k0 = table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos2[tda][1];
*startSymbolIndex = table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos2[tda][2];
*nrOfSymbols = table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos2[tda][3];
}
break;
default:
AssertFatal(1==0,"Invalid default time domaing allocation type\n");
}
AssertFatal(k0==0,"Only k0 = 0 is supported\n");
AssertFatal(is_mapping_typeA==1,"Only mapping type A is currently supported\n");
}
const char *prachfmt[]={"0","1","2","3", "A1","A2","A3","B1","B4","C0","C2","A1/B1","A2/B2","A3/B3"};
const char *duplex_mode[]={"FDD","TDD"};
@@ -1221,6 +1308,79 @@ void find_aggregation_candidates(uint8_t *aggregation_level,
*aggregation_level = 16;
*nr_of_candidates = ss->nrofCandidates->aggregationLevel16;
}
// n8 does not correspont to a value of 8 but 7, the following corrects this
if(*nr_of_candidates == 7)
*nr_of_candidates = 8;
}
void set_monitoring_periodicity_offset(NR_SearchSpace_t *ss,
uint16_t period,
uint16_t offset) {
switch(period) {
case 1:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1;
break;
case 2:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2;
ss->monitoringSlotPeriodicityAndOffset->choice.sl2 = offset;
break;
case 4:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl4;
ss->monitoringSlotPeriodicityAndOffset->choice.sl4 = offset;
break;
case 5:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl5;
ss->monitoringSlotPeriodicityAndOffset->choice.sl5 = offset;
break;
case 8:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl8;
ss->monitoringSlotPeriodicityAndOffset->choice.sl8 = offset;
break;
case 10:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl10;
ss->monitoringSlotPeriodicityAndOffset->choice.sl10 = offset;
break;
case 16:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl16;
ss->monitoringSlotPeriodicityAndOffset->choice.sl16 = offset;
break;
case 20:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl20;
ss->monitoringSlotPeriodicityAndOffset->choice.sl20 = offset;
break;
case 40:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl40;
ss->monitoringSlotPeriodicityAndOffset->choice.sl40 = offset;
break;
case 80:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl80;
ss->monitoringSlotPeriodicityAndOffset->choice.sl80 = offset;
break;
case 160:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl160;
ss->monitoringSlotPeriodicityAndOffset->choice.sl160 = offset;
break;
case 320:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl320;
ss->monitoringSlotPeriodicityAndOffset->choice.sl320 = offset;
break;
case 640:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl640;
ss->monitoringSlotPeriodicityAndOffset->choice.sl640 = offset;
break;
case 1280:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1280;
ss->monitoringSlotPeriodicityAndOffset->choice.sl1280 = offset;
break;
case 2560:
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2560;
ss->monitoringSlotPeriodicityAndOffset->choice.sl2560 = offset; break;
default:
AssertFatal(1==0,"Invalid monitoring slot periodicity value\n");
break;
}
}
@@ -3307,6 +3467,126 @@ uint16_t get_ssb_start_symbol(const long band, NR_SubcarrierSpacing_t scs, int i
}
}
void csi_period_offset(NR_CSI_ReportConfig_t *csirep,
NR_NZP_CSI_RS_Resource_t *nzpcsi,
int *period, int *offset) {
if(nzpcsi != NULL) {
NR_CSI_ResourcePeriodicityAndOffset_PR p_and_o = nzpcsi->periodicityAndOffset->present;
switch(p_and_o){
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots4:
*period = 4;
*offset = nzpcsi->periodicityAndOffset->choice.slots4;
break;
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots5:
*period = 5;
*offset = nzpcsi->periodicityAndOffset->choice.slots5;
break;
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots8:
*period = 8;
*offset = nzpcsi->periodicityAndOffset->choice.slots8;
break;
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots10:
*period = 10;
*offset = nzpcsi->periodicityAndOffset->choice.slots10;
break;
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots16:
*period = 16;
*offset = nzpcsi->periodicityAndOffset->choice.slots16;
break;
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots20:
*period = 20;
*offset = nzpcsi->periodicityAndOffset->choice.slots20;
break;
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots32:
*period = 32;
*offset = nzpcsi->periodicityAndOffset->choice.slots32;
break;
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots40:
*period = 40;
*offset = nzpcsi->periodicityAndOffset->choice.slots40;
break;
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots64:
*period = 64;
*offset = nzpcsi->periodicityAndOffset->choice.slots64;
break;
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots80:
*period = 80;
*offset = nzpcsi->periodicityAndOffset->choice.slots80;
break;
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots160:
*period = 160;
*offset = nzpcsi->periodicityAndOffset->choice.slots160;
break;
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots320:
*period = 320;
*offset = nzpcsi->periodicityAndOffset->choice.slots320;
break;
case NR_CSI_ResourcePeriodicityAndOffset_PR_slots640:
*period = 640;
*offset = nzpcsi->periodicityAndOffset->choice.slots640;
break;
default:
AssertFatal(1==0,"No periodicity and offset found in CSI resource");
}
}
if(csirep != NULL) {
NR_CSI_ReportPeriodicityAndOffset_PR p_and_o = csirep->reportConfigType.choice.periodic->reportSlotConfig.present;
switch(p_and_o){
case NR_CSI_ReportPeriodicityAndOffset_PR_slots4:
*period = 4;
*offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots4;
break;
case NR_CSI_ReportPeriodicityAndOffset_PR_slots5:
*period = 5;
*offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots5;
break;
case NR_CSI_ReportPeriodicityAndOffset_PR_slots8:
*period = 8;
*offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots8;
break;
case NR_CSI_ReportPeriodicityAndOffset_PR_slots10:
*period = 10;
*offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots10;
break;
case NR_CSI_ReportPeriodicityAndOffset_PR_slots16:
*period = 16;
*offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots16;
break;
case NR_CSI_ReportPeriodicityAndOffset_PR_slots20:
*period = 20;
*offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots20;
break;
case NR_CSI_ReportPeriodicityAndOffset_PR_slots40:
*period = 40;
*offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots40;
break;
case NR_CSI_ReportPeriodicityAndOffset_PR_slots80:
*period = 80;
*offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots80;
break;
case NR_CSI_ReportPeriodicityAndOffset_PR_slots160:
*period = 160;
*offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots160;
break;
case NR_CSI_ReportPeriodicityAndOffset_PR_slots320:
*period = 320;
*offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320;
break;
default:
AssertFatal(1==0,"No periodicity and offset resource found in CSI report");
}
}
}
void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config,
frame_t frameP,
NR_MIB_t *mib,
@@ -3316,6 +3596,7 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
NR_SubcarrierSpacing_t scs_ssb,
frequency_range_t frequency_range,
uint32_t ssb_index,
uint32_t ssb_period,
uint32_t ssb_offset_point_a) {
NR_SubcarrierSpacing_t scs_pdcch;
@@ -3335,7 +3616,7 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
else
scs_pdcch = NR_SubcarrierSpacing_kHz30;
}
type0_PDCCH_CSS_config->scs_pdcch = scs_pdcch;
type0_PDCCH_CSS_config->ssb_index = ssb_index;
type0_PDCCH_CSS_config->frame = frameP;
@@ -3530,6 +3811,8 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
}
// 38.213 chapter 13: over two consecutive slots
type0_PDCCH_CSS_config->search_space_duration = 2;
// two frames
type0_PDCCH_CSS_config->search_space_frame_period = nr_slots_per_frame[scs_ssb]<<1;
}
if(type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern == 1 && frequency_range == FR2){
@@ -3546,6 +3829,8 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
}
// 38.213 chapter 13: over two consecutive slots
type0_PDCCH_CSS_config->search_space_duration = 2;
// two frames
type0_PDCCH_CSS_config->search_space_frame_period = nr_slots_per_frame[scs_ssb]<<1;
}
/// MUX PATTERN 2
@@ -3611,6 +3896,8 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
}else{ ; }
// 38.213 chapter 13: over one slot
type0_PDCCH_CSS_config->search_space_duration = 1;
// SSB periodicity in slots
type0_PDCCH_CSS_config->search_space_frame_period = ssb_period*nr_slots_per_frame[scs_ssb];
}
/// MUX PATTERN 3
@@ -3639,6 +3926,8 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
}else{ ; }
// 38.213 chapter 13: over one slot
type0_PDCCH_CSS_config->search_space_duration = 1;
// SSB periodicity in slots
type0_PDCCH_CSS_config->search_space_frame_period = ssb_period*nr_slots_per_frame[scs_ssb];
}
AssertFatal(type0_PDCCH_CSS_config->number_of_search_space_per_slot!=UINT_MAX,"");
@@ -3662,6 +3951,271 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
}
void fill_coresetZero(NR_ControlResourceSet_t *coreset0, NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config) {
int32_t duration;
if (coreset0 == NULL)
coreset0 = calloc(1,sizeof(*coreset0));
coreset0->controlResourceSetId = 0;
AssertFatal(type0_PDCCH_CSS_config!=NULL,"No type0 CSS configuration\n");
duration = type0_PDCCH_CSS_config->num_symbols;
if(coreset0->frequencyDomainResources.buf == NULL) coreset0->frequencyDomainResources.buf = calloc(1,6);
switch(type0_PDCCH_CSS_config->num_rbs){
case 24:
coreset0->frequencyDomainResources.buf[0] = 0xf0;
coreset0->frequencyDomainResources.buf[1] = 0;
break;
case 48:
coreset0->frequencyDomainResources.buf[0] = 0xff;
coreset0->frequencyDomainResources.buf[1] = 0;
break;
case 96:
coreset0->frequencyDomainResources.buf[0] = 0xff;
coreset0->frequencyDomainResources.buf[1] = 0xff;
break;
default:
AssertFatal(1==0,"Invalid number of PRBs %d for Coreset0\n",type0_PDCCH_CSS_config->num_rbs);
}
coreset0->frequencyDomainResources.buf[2] = 0;
coreset0->frequencyDomainResources.buf[3] = 0;
coreset0->frequencyDomainResources.buf[4] = 0;
coreset0->frequencyDomainResources.buf[5] = 0;
coreset0->frequencyDomainResources.size = 6;
coreset0->frequencyDomainResources.bits_unused = 3;
coreset0->duration = duration;
coreset0->cce_REG_MappingType.present=NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved;
coreset0->cce_REG_MappingType.choice.interleaved=calloc(1,sizeof(*coreset0->cce_REG_MappingType.choice.interleaved));
coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize = NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6;
coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize = NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n2;
coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex = NULL; // -> use cell_id
coreset0->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle;
coreset0->tci_StatesPDCCH_ToAddList = NULL;
coreset0->tci_StatesPDCCH_ToReleaseList = NULL;
coreset0->tci_PresentInDCI = NULL;
coreset0->pdcch_DMRS_ScramblingID = NULL;
}
uint8_t fill_searchSpaceZero(NR_SearchSpace_t *ss0, NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config, int L) {
if(ss0 == NULL) ss0=calloc(1,sizeof(*ss0));
if(ss0->controlResourceSetId == NULL) ss0->controlResourceSetId=calloc(1,sizeof(*ss0->controlResourceSetId));
if(ss0->monitoringSymbolsWithinSlot == NULL) ss0->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss0->monitoringSymbolsWithinSlot));
if(ss0->monitoringSymbolsWithinSlot->buf == NULL) ss0->monitoringSymbolsWithinSlot->buf = calloc(1,2);
if(ss0->nrofCandidates == NULL) ss0->nrofCandidates = calloc(1,sizeof(*ss0->nrofCandidates));
if(ss0->searchSpaceType == NULL) ss0->searchSpaceType = calloc(1,sizeof(*ss0->searchSpaceType));
if(ss0->searchSpaceType->choice.common == NULL) ss0->searchSpaceType->choice.common=calloc(1,sizeof(*ss0->searchSpaceType->choice.common));
if(ss0->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0 == NULL)
ss0->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0 = calloc(1,sizeof(*ss0->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0));
uint32_t duration,periodicity,offset;
uint16_t symbols,max_agg;
AssertFatal(type0_PDCCH_CSS_config!=NULL,"No type0 CSS configuration\n");
max_agg = (type0_PDCCH_CSS_config->num_symbols*type0_PDCCH_CSS_config->num_rbs)/6;
if (L>max_agg) return 0;
symbols = (1-(1<<type0_PDCCH_CSS_config->num_symbols))<<type0_PDCCH_CSS_config->first_symbol_index;
duration = type0_PDCCH_CSS_config->search_space_duration;
periodicity = type0_PDCCH_CSS_config->search_space_frame_period;
if (type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern == 1)
offset = type0_PDCCH_CSS_config->n_0;
else
offset = type0_PDCCH_CSS_config->n_c;
ss0->searchSpaceId = 0;
*ss0->controlResourceSetId = 0;
ss0->monitoringSlotPeriodicityAndOffset = calloc(1,sizeof(*ss0->monitoringSlotPeriodicityAndOffset));
set_monitoring_periodicity_offset(ss0,periodicity,offset);
if (duration==1)
ss0->duration = NULL;
else{
ss0->duration = calloc(1,sizeof(*ss0->duration));
*ss0->duration = duration;
}
ss0->monitoringSymbolsWithinSlot->size = 2;
ss0->monitoringSymbolsWithinSlot->bits_unused = 2;
ss0->monitoringSymbolsWithinSlot->buf[1] = 0;
ss0->monitoringSymbolsWithinSlot->buf[0] = 0;
for (int i=0; i<8; i++) {
ss0->monitoringSymbolsWithinSlot->buf[1] |= ((symbols>>(i+8))&0x01)<<(7-i);
ss0->monitoringSymbolsWithinSlot->buf[0] |= ((symbols>>i)&0x01)<<(7-i);
}
// max values are set according to TS38.213 Section 10.1 Table 10.1-1
ss0->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0;
ss0->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0;
switch(L){
case 4:
ss0->nrofCandidates->aggregationLevel4 = (((max_agg>>2) > 4)? 4 : max_agg>>2);
ss0->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0;
ss0->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0;
break;
case 8:
ss0->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n0;
ss0->nrofCandidates->aggregationLevel8 = (((max_agg>>3) > 2)? 2 : max_agg>>3);
ss0->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0;
break;
case 16:
ss0->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n0;
ss0->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0;
ss0->nrofCandidates->aggregationLevel16 = (((max_agg>>4) > 1)? 1 : max_agg>>4);
break;
default:
AssertFatal(1==0,"Invalid aggregation level %d for SS0\n",L);
}
ss0->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_common;
return 1;
}
void find_period_offest_SR (NR_SchedulingRequestResourceConfig_t *SchedulingReqRec, int *period, int *offset) {
NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR P_O = SchedulingReqRec->periodicityAndOffset->present;
switch (P_O){
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl1:
*period = 1;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl1;
break;
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl2:
*period = 2;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl2;
break;
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl4:
*period = 4;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl4;
break;
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl5:
*period = 5;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl5;
break;
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl8:
*period = 8;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl8;
break;
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl10:
*period = 10;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl10;
break;
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl16:
*period = 16;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl16;
break;
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl20:
*period = 20;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl20;
break;
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl40:
*period = 40;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl40;
break;
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl80:
*period = 80;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl80;
break;
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl160:
*period = 160;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl160;
break;
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl320:
*period = 320;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl320;
break;
case NR_SchedulingRequestResourceConfig__periodicityAndOffset_PR_sl640:
*period = 640;
*offset = SchedulingReqRec->periodicityAndOffset->choice.sl640;
break;
default:
AssertFatal(1==0,"No periodicityAndOffset resources found in schedulingrequestresourceconfig");
}
}
uint16_t compute_pucch_prb_size(uint8_t format,
uint8_t nr_prbs,
uint16_t O_tot,
uint16_t O_csi,
NR_PUCCH_MaxCodeRate_t *maxCodeRate,
uint8_t Qm,
uint8_t n_symb,
uint8_t n_re_ctrl) {
uint16_t O_crc;
if (O_tot<12)
O_crc = 0;
else{
if (O_tot<20)
O_crc = 6;
else {
if (O_tot<360)
O_crc = 11;
else
AssertFatal(1==0,"Case for segmented PUCCH not yet implemented");
}
}
int rtimes100;
switch(*maxCodeRate){
case NR_PUCCH_MaxCodeRate_zeroDot08 :
rtimes100 = 8;
break;
case NR_PUCCH_MaxCodeRate_zeroDot15 :
rtimes100 = 15;
break;
case NR_PUCCH_MaxCodeRate_zeroDot25 :
rtimes100 = 25;
break;
case NR_PUCCH_MaxCodeRate_zeroDot35 :
rtimes100 = 35;
break;
case NR_PUCCH_MaxCodeRate_zeroDot45 :
rtimes100 = 45;
break;
case NR_PUCCH_MaxCodeRate_zeroDot60 :
rtimes100 = 60;
break;
case NR_PUCCH_MaxCodeRate_zeroDot80 :
rtimes100 = 80;
break;
default :
AssertFatal(1==0,"Invalid MaxCodeRate");
}
float r = (float)rtimes100/100;
if (O_csi == O_tot) {
if ((O_tot+O_csi)>(nr_prbs*n_re_ctrl*n_symb*Qm*r))
AssertFatal(1==0,"MaxCodeRate %.2f can't support %d UCI bits and %d CRC bits with %d PRBs",
r,O_tot,O_crc,nr_prbs);
else
return nr_prbs;
}
if (format==2){
// TODO fix this for multiple CSI reports
for (int i=1; i<=nr_prbs; i++){
if((O_tot+O_crc)<=(i*n_symb*Qm*n_re_ctrl*r) &&
(O_tot+O_crc)>((i-1)*n_symb*Qm*n_re_ctrl*r))
return i;
}
AssertFatal(1==0,"MaxCodeRate %.2f can't support %d UCI bits and %d CRC bits with at most %d PRBs",
r,O_tot,O_crc,nr_prbs);
}
else{
AssertFatal(1==0,"Not yet implemented");
}
}
/* extract UL PTRS values from RRC and validate it based upon 38.214 6.2.3 */
bool set_ul_ptrs_values(NR_PTRS_UplinkConfig_t *ul_ptrs_config,
uint16_t rbSize,uint8_t mcsIndex, uint8_t mcsTable,
@@ -136,12 +136,40 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
NR_SubcarrierSpacing_t scs_ssb,
frequency_range_t frequency_range,
uint32_t ssb_index,
uint32_t ssb_period,
uint32_t ssb_offset_point_a);
uint16_t get_ssb_start_symbol(const long band, NR_SubcarrierSpacing_t scs, int i_ssb);
void get_info_from_tda_tables(int default_abc,
int tda,
int dmrs_TypeA_Position,
int normal_CP,
int *startSymbolIndex,
int *nrOfSymbols);
void fill_coresetZero(NR_ControlResourceSet_t *coreset0, NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config);
uint8_t fill_searchSpaceZero(NR_SearchSpace_t *ss0, NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config, int L);
uint16_t compute_pucch_prb_size(uint8_t format,
uint8_t nr_prbs,
uint16_t O_tot,
uint16_t O_csi,
NR_PUCCH_MaxCodeRate_t *maxCodeRate,
uint8_t Qm,
uint8_t n_symb,
uint8_t n_re_ctrl);
int16_t get_N_RA_RB (int delta_f_RA_PRACH,int delta_f_PUSCH);
void find_period_offest_SR (NR_SchedulingRequestResourceConfig_t *SchedulingReqRec, int *period, int *offset);
void csi_period_offset(NR_CSI_ReportConfig_t *csirep,
NR_NZP_CSI_RS_Resource_t *nzpcsi,
int *period, int *offset);
void reverse_n_bits(uint8_t *value, uint16_t bitlen);
bool set_dl_ptrs_values(NR_PTRS_DownlinkConfig_t *ptrs_config,
uint16_t rbSize, uint8_t mcsIndex, uint8_t mcsTable,
uint8_t *K_ptrs, uint8_t *L_ptrs,uint8_t *portIndex,
@@ -56,7 +56,6 @@ extern unsigned char NB_UE_INST;*/
extern unsigned char NB_INST;
extern unsigned char NB_eNB_INST;
extern unsigned char NB_RN_INST;
extern unsigned short NODE_ID[1];
/* Scheduler */
extern RAN_CONTEXT_t RC;
@@ -139,13 +138,4 @@ extern const float table_38213_13_12_c3[16];
extern const int32_t table_38213_10_1_1_c2[5];
extern const uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos2[16][3];
extern const uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A_dmrs_typeA_pos3[16][3];
extern const uint8_t table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos2[16][3];
extern const uint8_t table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP_dmrs_typeA_pos3[16][3];
extern const uint8_t table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos2[16][3];
extern const uint8_t table_5_1_2_1_1_4_time_dom_res_alloc_B_dmrs_typeA_pos3[16][3];
extern const uint8_t table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos2[16][3];
extern const uint8_t table_5_1_2_1_1_5_time_dom_res_alloc_C_dmrs_typeA_pos3[16][3];
#endif //DEF_H