making phy-test slot bitmap tdd period based to minimize the chance to need it larger than 64 slots
This commit is contained in:
@@ -45,7 +45,7 @@
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<testCase id="090101">
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<testCase id="090101">
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<class>Initialize_eNB</class>
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<class>Initialize_eNB</class>
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<desc>Initialize gNB USRP</desc>
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<desc>Initialize gNB USRP</desc>
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<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.106prb.usrpn300.phytest-dora.conf --phy-test -q -U 787200 -T 106 -t 23 -D 130175 -m 28 -M 106 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args>
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<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.106prb.usrpn300.phytest-dora.conf --phy-test -q -U 768 -T 106 -t 23 -D 127 -m 28 -M 106 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args>
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<rt_stats_cfg>datalog_rt_stats.default.yaml</rt_stats_cfg>
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<rt_stats_cfg>datalog_rt_stats.default.yaml</rt_stats_cfg>
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<air_interface>NR</air_interface>
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<air_interface>NR</air_interface>
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<USRP_IPAddress>192.168.20.2</USRP_IPAddress>
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<USRP_IPAddress>192.168.20.2</USRP_IPAddress>
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@@ -45,7 +45,7 @@
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<testCase id="390101">
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<testCase id="390101">
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<class>Initialize_eNB</class>
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<class>Initialize_eNB</class>
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<desc>Initialize gNB USRP</desc>
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<desc>Initialize gNB USRP</desc>
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<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.273prb.usrpn300.phytest-dora.conf --phy-test -q -U 787200 -T 273 -t 23 -D 130175 -m 23 -M 273 -l 2 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args>
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<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.273prb.usrpn300.phytest-dora.conf --phy-test -q -U 768 -T 273 -t 23 -D 127 -m 23 -M 273 -l 2 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args>
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<rt_stats_cfg>datalog_rt_stats.100.2x2.yaml</rt_stats_cfg>
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<rt_stats_cfg>datalog_rt_stats.100.2x2.yaml</rt_stats_cfg>
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<air_interface>NR</air_interface>
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<air_interface>NR</air_interface>
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<USRP_IPAddress>192.168.20.2</USRP_IPAddress>
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<USRP_IPAddress>192.168.20.2</USRP_IPAddress>
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@@ -45,7 +45,7 @@
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<testCase id="190101">
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<testCase id="190101">
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<class>Initialize_eNB</class>
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<class>Initialize_eNB</class>
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<desc>Initialize gNB USRP</desc>
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<desc>Initialize gNB USRP</desc>
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<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.162prb.usrpn300.phytest-dora.conf --phy-test -q -U 787200 -T 162 -t 23 -D 130175 -m 23 -M 162 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args>
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<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.162prb.usrpn300.phytest-dora.conf --phy-test -q -U 768 -T 162 -t 23 -D 127 -m 23 -M 162 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args>
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<rt_stats_cfg>datalog_rt_stats.1x1.60.yaml</rt_stats_cfg>
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<rt_stats_cfg>datalog_rt_stats.1x1.60.yaml</rt_stats_cfg>
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<air_interface>NR</air_interface>
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<air_interface>NR</air_interface>
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<USRP_IPAddress>192.168.20.2</USRP_IPAddress>
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<USRP_IPAddress>192.168.20.2</USRP_IPAddress>
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@@ -45,7 +45,7 @@
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<testCase id="290101">
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<testCase id="290101">
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<class>Initialize_eNB</class>
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<class>Initialize_eNB</class>
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<desc>Initialize gNB USRP</desc>
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<desc>Initialize gNB USRP</desc>
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<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.162prb.usrpn300.phytest-dora.conf --phy-test --gNBs.[0].pdsch_AntennaPorts_XP 2 --RUs.[0].nb_tx 2 --RUs.[0].nb_rx 2 -q -U 787200 -T 162 -t 23 -D 130175 -m 23 -M 162 -l 2 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args>
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<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.162prb.usrpn300.phytest-dora.conf --phy-test --gNBs.[0].pdsch_AntennaPorts_XP 2 --RUs.[0].nb_tx 2 --RUs.[0].nb_rx 2 -q -U 768 -T 162 -t 23 -D 127 -m 23 -M 162 -l 2 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args>
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<rt_stats_cfg>datalog_rt_stats.60.2x2.yaml</rt_stats_cfg>
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<rt_stats_cfg>datalog_rt_stats.60.2x2.yaml</rt_stats_cfg>
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<air_interface>NR</air_interface>
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<air_interface>NR</air_interface>
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<USRP_IPAddress>192.168.20.2</USRP_IPAddress>
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<USRP_IPAddress>192.168.20.2</USRP_IPAddress>
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@@ -64,8 +64,8 @@
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#define CONFIG_HLP_DLBW_PHYTEST "Set the number of PRBs used for DLSCH in PHYTEST mode\n"
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#define CONFIG_HLP_DLBW_PHYTEST "Set the number of PRBs used for DLSCH in PHYTEST mode\n"
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#define CONFIG_HLP_ULBW_PHYTEST "Set the number of PRBs used for ULSCH in PHYTEST mode\n"
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#define CONFIG_HLP_ULBW_PHYTEST "Set the number of PRBs used for ULSCH in PHYTEST mode\n"
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#define CONFIG_HLP_PRB_SA "Set the number of PRBs for SA\n"
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#define CONFIG_HLP_PRB_SA "Set the number of PRBs for SA\n"
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#define CONFIG_HLP_DLBM_PHYTEST "Bitmap for DLSCH slots (slot 0 starts at LSB)\n"
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#define CONFIG_HLP_DLBM_PHYTEST "Bitmap for DLSCH slots in period (slot 0 starts at LSB)\n"
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#define CONFIG_HLP_ULBM_PHYTEST "Bitmap for ULSCH slots (slot 0 starts at LSB)\n"
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#define CONFIG_HLP_ULBM_PHYTEST "Bitmap for ULSCH slots in period (slot 0 starts at LSB)\n"
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#define CONFIG_HLP_SSC "Set the start subcarrier \n"
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#define CONFIG_HLP_SSC "Set the start subcarrier \n"
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#define CONFIG_HLP_TDD "Set hardware to TDD mode (default: FDD). Used only with -U (otherwise set in config file).\n"
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#define CONFIG_HLP_TDD "Set hardware to TDD mode (default: FDD). Used only with -U (otherwise set in config file).\n"
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#define CONFIG_HLP_UE "Set the lte softmodem as a UE\n"
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#define CONFIG_HLP_UE "Set the lte softmodem as a UE\n"
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@@ -41,27 +41,29 @@
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// #define ENABLE_MAC_PAYLOAD_DEBUG 1
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// #define ENABLE_MAC_PAYLOAD_DEBUG 1
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/* This function checks whether the given Dl/UL slot is set
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/* This function checks whether the given Dl/UL slot is set
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in the input bitmap, which is a mask indicating in which
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in the input bitmap (per period), which is a mask indicating in which
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slot to transmit (among those available in the TDD configuration) */
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slot to transmit (among those available in the TDD configuration) */
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static bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot)
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static bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot)
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{
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{
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return (bitmap >> (slot % 64)) & 0x01;
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AssertFatal(slot < 64, "Unable to handle periods with length larger than 64 slots in phy-test mode\n");
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return (bitmap >> slot) & 0x01;
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}
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}
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uint32_t target_dl_mcs = 9;
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uint32_t target_dl_mcs = 9;
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uint32_t target_dl_Nl = 1;
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uint32_t target_dl_Nl = 1;
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uint32_t target_dl_bw = 50;
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uint32_t target_dl_bw = 50;
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uint64_t dlsch_slot_bitmap = (1<<1);
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uint64_t dlsch_slot_bitmap = (1<<1);
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/* schedules whole bandwidth for first user, all the time */
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/* schedules whole bandwidth for first user, all the time */
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void nr_preprocessor_phytest(module_id_t module_id,
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void nr_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_t slot)
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frame_t frame,
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sub_frame_t slot)
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{
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{
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gNB_MAC_INST *mac = RC.nrmac[module_id];
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/* already mutex protected: held in gNB_dlsch_ulsch_scheduler() */
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/* already mutex protected: held in gNB_dlsch_ulsch_scheduler() */
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if (!is_xlsch_in_slot(dlsch_slot_bitmap, slot))
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int slot_period = slot % mac->frame_structure.numb_slots_period;
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if (!is_xlsch_in_slot(dlsch_slot_bitmap, slot_period))
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return;
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return;
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NR_UE_info_t *UE = RC.nrmac[module_id]->UE_info.list[0];
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NR_UE_info_t *UE = mac->UE_info.list[0];
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NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon;
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NR_ServingCellConfigCommon_t *scc = mac->common_channels[0].ServingCellConfigCommon;
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NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
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NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
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NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP;
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NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP;
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const int CC_id = 0;
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const int CC_id = 0;
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@@ -72,7 +74,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
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return;
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return;
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}
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}
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const int tda = get_dl_tda(RC.nrmac[module_id], slot);
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const int tda = get_dl_tda(mac, slot);
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NR_tda_info_t tda_info = get_dl_tda_info(dl_bwp,
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NR_tda_info_t tda_info = get_dl_tda_info(dl_bwp,
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sched_ctrl->search_space->searchSpaceType->present,
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sched_ctrl->search_space->searchSpaceType->present,
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tda,
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tda,
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@@ -98,7 +100,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
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int rbSize = 0;
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int rbSize = 0;
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if (target_dl_bw>bwpSize)
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if (target_dl_bw>bwpSize)
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target_dl_bw = bwpSize;
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target_dl_bw = bwpSize;
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uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map[beam];
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uint16_t *vrb_map = mac->common_channels[CC_id].vrb_map[beam];
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/* loop ensures that we allocate exactly target_dl_bw, or return */
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/* loop ensures that we allocate exactly target_dl_bw, or return */
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while (true) {
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while (true) {
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/* advance to first free RB */
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/* advance to first free RB */
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@@ -139,7 +141,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
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0);
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0);
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sched_ctrl->num_total_bytes += sched_ctrl->rlc_status[lcid].bytes_in_buffer;
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sched_ctrl->num_total_bytes += sched_ctrl->rlc_status[lcid].bytes_in_buffer;
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int CCEIndex = get_cce_index(RC.nrmac[module_id],
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int CCEIndex = get_cce_index(mac,
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CC_id, slot, UE->rnti,
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CC_id, slot, UE->rnti,
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&sched_ctrl->aggregation_level,
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&sched_ctrl->aggregation_level,
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beam,
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beam,
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@@ -147,10 +149,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
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sched_ctrl->coreset,
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sched_ctrl->coreset,
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&sched_ctrl->sched_pdcch,
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&sched_ctrl->sched_pdcch,
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false);
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false);
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AssertFatal(CCEIndex >= 0,
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AssertFatal(CCEIndex >= 0, "Could not find CCE for UE %04x\n", UE->rnti);
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"%s(): could not find CCE for UE %04x\n",
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__func__,
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UE->rnti);
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NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
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NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
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if (sched_pdsch->dl_harq_pid == -1)
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if (sched_pdsch->dl_harq_pid == -1)
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@@ -159,20 +158,16 @@ void nr_preprocessor_phytest(module_id_t module_id,
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int alloc = -1;
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int alloc = -1;
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if (!get_FeedbackDisabled(UE->sc_info.downlinkHARQ_FeedbackDisabled_r17, sched_pdsch->dl_harq_pid)) {
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if (!get_FeedbackDisabled(UE->sc_info.downlinkHARQ_FeedbackDisabled_r17, sched_pdsch->dl_harq_pid)) {
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int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, UE->current_UL_BWP.pucch_Config, CCEIndex);
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int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, UE->current_UL_BWP.pucch_Config, CCEIndex);
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alloc = nr_acknack_scheduling(RC.nrmac[module_id], UE, frame, slot, 0, r_pucch, 0);
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alloc = nr_acknack_scheduling(mac, UE, frame, slot, 0, r_pucch, 0);
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if (alloc < 0) {
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if (alloc < 0) {
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LOG_D(MAC,
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LOG_D(NR_MAC, "Could not find PUCCH for UE %04x@%d.%d\n", rnti, frame, slot);
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"Could not find PUCCH for UE %04x@%d.%d\n",
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rnti,
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frame,
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slot);
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return;
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return;
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}
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}
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}
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}
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sched_ctrl->cce_index = CCEIndex;
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sched_ctrl->cce_index = CCEIndex;
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fill_pdcch_vrb_map(RC.nrmac[module_id],
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fill_pdcch_vrb_map(mac,
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CC_id,
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CC_id,
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&sched_ctrl->sched_pdcch,
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&sched_ctrl->sched_pdcch,
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CCEIndex,
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CCEIndex,
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@@ -270,7 +265,8 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
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/* check if slot is UL, and that slot is 8 (assuming K2=6 because of UE
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/* check if slot is UL, and that slot is 8 (assuming K2=6 because of UE
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* limitations). Note that if K2 or the TDD configuration is changed, below
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* limitations). Note that if K2 or the TDD configuration is changed, below
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* conditions might exclude each other and never be true */
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* conditions might exclude each other and never be true */
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if (!is_xlsch_in_slot(ulsch_slot_bitmap, sched_slot))
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int slot_period = sched_slot % nr_mac->frame_structure.numb_slots_period;
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if (!is_xlsch_in_slot(ulsch_slot_bitmap, slot_period))
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return false;
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return false;
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uint16_t rbStart = 0;
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uint16_t rbStart = 0;
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@@ -150,9 +150,7 @@ uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs);
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/* \brief preprocessor for phytest: schedules UE_id 0 with fixed MCS on all
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/* \brief preprocessor for phytest: schedules UE_id 0 with fixed MCS on all
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* freq resources */
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* freq resources */
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void nr_preprocessor_phytest(module_id_t module_id,
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void nr_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_t slot);
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frame_t frame,
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sub_frame_t slot);
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/* \brief UL preprocessor for phytest: schedules UE_id 0 with fixed MCS on a
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/* \brief UL preprocessor for phytest: schedules UE_id 0 with fixed MCS on a
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* fixed set of resources */
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* fixed set of resources */
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bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_t slot);
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bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_t slot);
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