[OAI-UE] fix pucch format2 regression
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@@ -523,8 +523,29 @@ void generate_pucch2x(int32_t **txdataF,
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pucch2x_modulation(btilde,d,amp);
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pucch2x_modulation(btilde,d,amp);
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// add extra symbol for 2a/2b
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// add extra symbol for 2a/2b
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d[20]=0;
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d[21]=0;
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if (fmt==pucch_format2a)
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d[20] = (B2 == 0) ? amp : -amp;
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else if (fmt==pucch_format2b) {
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switch (B2) {
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case 0:
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d[20] = amp;
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break;
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case 1:
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d[21] = -amp;
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break;
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case 2:
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d[21] = amp;
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break;
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case 3:
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d[20] = -amp;
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break;
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default:
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AssertFatal(1==0,"Illegal modulation symbol %d for PUCCH %s\n",B2,pucch_format_string[fmt]);
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break;
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}
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}
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#ifdef DEBUG_PUCCH_TX
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#ifdef DEBUG_PUCCH_TX
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@@ -552,7 +573,8 @@ void generate_pucch2x(int32_t **txdataF,
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n_cs = (ncs_cell[ns][l]+nprime)%12;
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n_cs = (ncs_cell[ns][l]+nprime)%12;
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alpha_ind = 0;
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alpha_ind = 0;
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for (n=0; n<12; n++) {
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for (n=0; n<12; n++)
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{
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// this is r_uv^alpha(n)
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// this is r_uv^alpha(n)
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ref_re = (int16_t)(((int32_t)alpha_re[alpha_ind] * ul_ref_sigs[u][v][0][n<<1] - (int32_t)alpha_im[alpha_ind] * ul_ref_sigs[u][v][0][1+(n<<1)])>>15);
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ref_re = (int16_t)(((int32_t)alpha_re[alpha_ind] * ul_ref_sigs[u][v][0][n<<1] - (int32_t)alpha_im[alpha_ind] * ul_ref_sigs[u][v][0][1+(n<<1)])>>15);
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ref_im = (int16_t)(((int32_t)alpha_re[alpha_ind] * ul_ref_sigs[u][v][0][1+(n<<1)] + (int32_t)alpha_im[alpha_ind] * ul_ref_sigs[u][v][0][n<<1])>>15);
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ref_im = (int16_t)(((int32_t)alpha_re[alpha_ind] * ul_ref_sigs[u][v][0][1+(n<<1)] + (int32_t)alpha_im[alpha_ind] * ul_ref_sigs[u][v][0][n<<1])>>15);
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@@ -563,48 +585,25 @@ void generate_pucch2x(int32_t **txdataF,
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//LOG_I(PHY,"slot %d ofdm# %d ==> d[%d,%d] \n",ns,l,data_ind,n);
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//LOG_I(PHY,"slot %d ofdm# %d ==> d[%d,%d] \n",ns,l,data_ind,n);
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}
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}
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else {
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else {
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if (l==1){
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if ((l==1) || ( (l==5) && (fmt==pucch_format2) ))
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((int16_t *)&zptr[n])[0] = ((int32_t)amp*ref_re>>15);
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{
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((int16_t *)&zptr[n])[1] = ((int32_t)amp*ref_im>>15);
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((int16_t *)&zptr[n])[0] = ((int32_t)amp*ref_re>>15);
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}
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((int16_t *)&zptr[n])[1] = ((int32_t)amp*ref_im>>15);
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else if (fmt==pucch_format2a) {
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}
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d[20]=amp;
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// l == 5 && pucch format 2a
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d[21]=amp;
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else if (fmt==pucch_format2a)
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if (B2 == 0) {
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{
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((int16_t *)&zptr[n])[0] = ((int32_t)amp*ref_re>>15);
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((int16_t *)&zptr[n])[0] = ((int32_t)d[20]*ref_re>>15);
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((int16_t *)&zptr[n])[1] = ((int32_t)amp*ref_im>>15);
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((int16_t *)&zptr[n])[1] = ((int32_t)d[21]*ref_im>>15);
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}
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}
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else {
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// l == 5 && pucch format 2b
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((int16_t *)&zptr[n])[0] = -((int32_t)amp*ref_re>>15);
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else if (fmt==pucch_format2b)
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((int16_t *)&zptr[n])[1] = -((int32_t)amp*ref_im>>15);
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{
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}
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((int16_t *)&zptr[n])[0] = ((int32_t)d[20]*ref_re>>15);
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//LOG_I(PHY,"slot %d ofdm# %d ==> dmrs[%d] \n",ns,l,n);
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((int16_t *)&zptr[n])[1] = ((int32_t)d[21]*ref_im>>15);
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}
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}
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else if (fmt==pucch_format2b) {
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} // l==1 || l==5
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switch (B2) {
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alpha_ind = (alpha_ind + n_cs)%12;
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case 0: // 1
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((int16_t *)&zptr[n])[0] = ((int32_t)amp*ref_re>>15);
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((int16_t *)&zptr[n])[1] = ((int32_t)amp*ref_im>>15);
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break;
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case 1: // -j
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((int16_t *)&zptr[n])[1] = ((int32_t)amp*ref_re>>15);
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((int16_t *)&zptr[n])[0] = -((int32_t)amp*ref_im>>15);
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break;
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case 2: // -1
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((int16_t *)&zptr[n])[0] = -((int32_t)amp*ref_re>>15);
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((int16_t *)&zptr[n])[1] = -((int32_t)amp*ref_im>>15);
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break;
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case 3: // j
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((int16_t *)&zptr[n])[1] = -((int32_t)amp*ref_re>>15);
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((int16_t *)&zptr[n])[0] = ((int32_t)amp*ref_im>>15);
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break;
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default:
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AssertFatal(1==0,"Illegal modulation symbol %d for PUCCH %s\n",B2,pucch_format_string[fmt]);
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break;
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}
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}// fmt==pucch_format2b
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}// l==1 || l==5
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alpha_ind = (alpha_ind + n_cs)%12;
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} // n
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} // n
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zptr+=12;
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zptr+=12;
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