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fix for empty mib at beginning of execution

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This commit is contained in:
francescomani
2021-06-24 12:22:03 +02:00
parent fcecd0dfdb
commit c249ca0bd8
3 changed files with 8 additions and 1 deletions
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openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
+5 -1
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@@ -158,10 +158,14 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
dl_req = &dl_tti_request->dl_tti_request_body; dl_req = &dl_tti_request->dl_tti_request_body;
// get MIB every 8 frames // get MIB every 8 frames
if((slotP == 0) && (frameP & 7) == 0) { if(((slotP == 0) && (frameP & 7) == 0) ||
gNB->first_MIB) {
mib_sdu_length = mac_rrc_nr_data_req(module_idP, CC_id, frameP, MIBCH, 0, 1, &cc->MIB_pdu.payload[0]); mib_sdu_length = mac_rrc_nr_data_req(module_idP, CC_id, frameP, MIBCH, 0, 1, &cc->MIB_pdu.payload[0]);
// flag to avoid sending an empty MIB in the first frames of execution since gNB doesn't get at the beginning in frame 0 slot 0
gNB->first_MIB = false;
LOG_D(MAC, LOG_D(MAC,
"[gNB %d] Frame %d : MIB->BCH CC_id %d, Received %d bytes\n", "[gNB %d] Frame %d : MIB->BCH CC_id %d, Received %d bytes\n",
module_idP, module_idP,
openair2/LAYER2/NR_MAC_gNB/main.c
+2
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@@ -81,6 +81,8 @@ void mac_top_init_gNB(void)
RC.nrmac[i]->ul_handle = 0; RC.nrmac[i]->ul_handle = 0;
RC.nrmac[i]->first_MIB = true;
if (get_softmodem_params()->phy_test) { if (get_softmodem_params()->phy_test) {
RC.nrmac[i]->pre_processor_dl = nr_preprocessor_phytest; RC.nrmac[i]->pre_processor_dl = nr_preprocessor_phytest;
RC.nrmac[i]->pre_processor_ul = nr_ul_preprocessor_phytest; RC.nrmac[i]->pre_processor_ul = nr_ul_preprocessor_phytest;
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+1
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@@ -736,6 +736,7 @@ typedef struct gNB_MAC_INST_s {
NR_CellGroupConfig_t *secondaryCellGroupCommon; NR_CellGroupConfig_t *secondaryCellGroupCommon;
NR_Type0_PDCCH_CSS_config_t type0_PDCCH_CSS_config[64]; NR_Type0_PDCCH_CSS_config_t type0_PDCCH_CSS_config[64];
bool first_MIB;
} gNB_MAC_INST; } gNB_MAC_INST;
#endif /*__LAYER2_NR_MAC_GNB_H__ */ #endif /*__LAYER2_NR_MAC_GNB_H__ */