Check for CCE allocation in DL PP
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@@ -90,12 +90,18 @@ int round_robin_dl(module_id_t Mod_id,
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const uint8_t round = ue_ctrl->round[CC_id][harq_pid];
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const uint8_t round = ue_ctrl->round[CC_id][harq_pid];
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if (round != 8) { // retransmission: allocate
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if (round != 8) { // retransmission: allocate
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int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid];
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int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid];
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if (nb_rb % RBGsize != 0) {
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if (nb_rb == 0)
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continue;
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if (nb_rb % RBGsize != 0)
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nb_rb += nb_rb % RBGsize; // should now divide evenly
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nb_rb += nb_rb % RBGsize; // should now divide evenly
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}
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int nb_rbg = nb_rb / RBGsize;
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int nb_rbg = nb_rb / RBGsize;
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if (nb_rbg > n_rbg_sched) // needs more RBGs than we can allocate
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if (nb_rbg > n_rbg_sched) // needs more RBGs than we can allocate
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continue;
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continue;
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const uint8_t cqi = ue_ctrl->dl_cqi[CC_id];
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const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi);
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if (idx < 0)
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continue; // cannot allocate CCE
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ue_ctrl->pre_dci_dl_pdu_idx = idx;
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// retransmissions: directly allocate
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// retransmissions: directly allocate
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n_rbg_sched -= nb_rbg;
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n_rbg_sched -= nb_rbg;
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ue_ctrl->pre_nb_available_rbs[CC_id] += nb_rb;
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ue_ctrl->pre_nb_available_rbs[CC_id] += nb_rb;
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@@ -155,8 +161,16 @@ int round_robin_dl(module_id_t Mod_id,
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while (num_ue_sched < max_num_ue) {
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while (num_ue_sched < max_num_ue) {
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while (rb_required[UE_id] == 0)
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while (rb_required[UE_id] == 0)
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UE_id = next_ue_list_looped(UE_list, UE_id);
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UE_id = next_ue_list_looped(UE_list, UE_id);
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/* TODO: check that CCE allocation is feasible. If it is not, reduce
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const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id];
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* num_ue_req anyway because this would have been one opportunity */
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const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi);
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if (idx < 0) {
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LOG_D(MAC, "cannot allocate CCE for UE %d, skipping\n", UE_id);
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num_ue_req--;
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max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched);
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UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate
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continue;
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}
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UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx;
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*cur_UE = UE_id;
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*cur_UE = UE_id;
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cur_UE = &UE_sched.next[UE_id];
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cur_UE = &UE_sched.next[UE_id];
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rb_required_total += rb_required[UE_id];
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rb_required_total += rb_required[UE_id];
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@@ -347,7 +361,7 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
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frameP,
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frameP,
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subframeP,
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subframeP,
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&UE_to_sched,
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&UE_to_sched,
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3, // max_num_ue
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4, // max_num_ue
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n_rbg_sched,
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n_rbg_sched,
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rbgalloc_mask);
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rbgalloc_mask);
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