diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c index aa09f84028..9a2e8c91cb 100644 --- a/openair1/PHY/INIT/nr_init.c +++ b/openair1/PHY/INIT/nr_init.c @@ -118,12 +118,15 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, gNB->bad_pucch = 0; + // ceil(((NB_RB<<1)*3)/32) // 3 RE *2(QPSK) + int pdcch_dmrs_init_length = (((fp->N_RB_DL<<1)*3)>>5)+1; + for (int slot=0; slotslots_per_frame; slot++) { pdcch_dmrs[slot] = (uint32_t **)malloc16(fp->symbols_per_slot*sizeof(uint32_t *)); AssertFatal(pdcch_dmrs[slot]!=NULL, "NR init: pdcch_dmrs for slot %d - malloc failed\n", slot); for (int symb=0; symbsymbols_per_slot; symb++) { - pdcch_dmrs[slot][symb] = (uint32_t *)malloc16(NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD*sizeof(uint32_t)); + pdcch_dmrs[slot][symb] = (uint32_t *)malloc16(pdcch_dmrs_init_length*sizeof(uint32_t)); LOG_D(PHY,"pdcch_dmrs[%d][%d] %p\n",slot,symb,pdcch_dmrs[slot][symb]); AssertFatal(pdcch_dmrs[slot][symb]!=NULL, "NR init: pdcch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb); } @@ -137,6 +140,8 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, gNB->nr_gold_pdsch_dmrs = (uint32_t ****)malloc16(fp->slots_per_frame*sizeof(uint32_t ***)); uint32_t ****pdsch_dmrs = gNB->nr_gold_pdsch_dmrs; + // ceil(((NB_RB*6(k)*2(QPSK)/32) // 3 RE *2(QPSK) + int pdsch_dmrs_init_length = ((fp->N_RB_DL*12)>>5)+1; for (int slot=0; slotslots_per_frame; slot++) { pdsch_dmrs[slot] = (uint32_t ***)malloc16(fp->symbols_per_slot*sizeof(uint32_t **)); AssertFatal(pdsch_dmrs[slot]!=NULL, "NR init: pdsch_dmrs for slot %d - malloc failed\n", slot); @@ -146,7 +151,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, AssertFatal(pdsch_dmrs[slot][symb]!=NULL, "NR init: pdsch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb); for (int q=0; qnr_gold_pusch_dmrs; + // ceil(((NB_RB*6(k)*2(QPSK)/32) // 3 RE *2(QPSK) + int pusch_dmrs_init_length = ((fp->N_RB_UL*12)>>5)+1; for(int nscid=0; nscid<2; nscid++) { pusch_dmrs[nscid] = (uint32_t ***)malloc16(fp->slots_per_frame*sizeof(uint32_t **)); AssertFatal(pusch_dmrs[nscid]!=NULL, "NR init: pusch_dmrs for nscid %d - malloc failed\n", nscid); @@ -168,7 +175,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, AssertFatal(pusch_dmrs[nscid][slot]!=NULL, "NR init: pusch_dmrs for slot %d - malloc failed\n", slot); for (int symb=0; symbsymbols_per_slot; symb++) { - pusch_dmrs[nscid][slot][symb] = (uint32_t *)malloc16(NR_MAX_PUSCH_DMRS_INIT_LENGTH_DWORD*sizeof(uint32_t)); + pusch_dmrs[nscid][slot][symb] = (uint32_t *)malloc16(pusch_dmrs_init_length*sizeof(uint32_t)); AssertFatal(pusch_dmrs[nscid][slot][symb]!=NULL, "NR init: pusch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb); } } @@ -183,12 +190,15 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, uint32_t ***csi_rs = gNB->nr_gold_csi_rs; AssertFatal(csi_rs!=NULL, "NR init: csi reference signal malloc failed\n"); + // ceil((NB_RB*8(max allocation per RB)*2(QPSK))/32) + int csi_dmrs_init_length = ((fp->N_RB_DL<<4)>>5)+1; + for (int slot=0; slotslots_per_frame; slot++) { csi_rs[slot] = (uint32_t **)malloc16(fp->symbols_per_slot*sizeof(uint32_t *)); AssertFatal(csi_rs[slot]!=NULL, "NR init: csi reference signal for slot %d - malloc failed\n", slot); for (int symb=0; symbsymbols_per_slot; symb++) { - csi_rs[slot][symb] = (uint32_t *)malloc16(NR_MAX_CSI_RS_INIT_LENGTH_DWORD*sizeof(uint32_t)); + csi_rs[slot][symb] = (uint32_t *)malloc16(csi_dmrs_init_length*sizeof(uint32_t)); AssertFatal(csi_rs[slot][symb]!=NULL, "NR init: csi reference signal for slot %d symbol %d - malloc failed\n", slot, symb); } } diff --git a/openair1/PHY/INIT/nr_init_ue.c b/openair1/PHY/INIT/nr_init_ue.c index 99f869c9b7..a38cb1d93f 100644 --- a/openair1/PHY/INIT/nr_init_ue.c +++ b/openair1/PHY/INIT/nr_init_ue.c @@ -137,10 +137,9 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, NR_UE_COMMON *const common_vars = &ue->common_vars; NR_UE_PBCH **const pbch_vars = ue->pbch_vars; NR_UE_PRACH **const prach_vars = ue->prach_vars; - int i,j,k,l,slot,symb,q; + int i,j,k,l,slot,symb; int gNB_id; int th_id; - uint32_t ****pusch_dmrs; uint16_t N_n_scid[2] = {0,1}; // [HOTFIX] This is a temporary implementation of scramblingID0 and scramblingID1 which are given by DMRS-UplinkConfig int n_scid; abstraction_flag = 0; @@ -197,22 +196,22 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, /////////////////////////PUSCH DMRS init///////////////////////// /////////// - ue->nr_gold_pusch_dmrs = (uint32_t ****)malloc16(fp->slots_per_frame*sizeof(uint32_t ***)); - pusch_dmrs = ue->nr_gold_pusch_dmrs; + + // ceil(((NB_RB*6(k)*2(QPSK)/32) // 3 RE *2(QPSK) + int pusch_dmrs_init_length = ((fp->N_RB_UL*12)>>5)+1; + + ue->nr_gold_pusch_dmrs = (uint32_t ***)malloc16(fp->slots_per_frame*sizeof(uint32_t **)); + uint32_t ***pusch_dmrs = ue->nr_gold_pusch_dmrs; n_scid = 0; // This quantity is indicated by higher layer parameter dmrs-SeqInitialization for (slot=0; slotslots_per_frame; slot++) { - pusch_dmrs[slot] = (uint32_t ***)malloc16(fp->symbols_per_slot*sizeof(uint32_t **)); + pusch_dmrs[slot] = (uint32_t **)malloc16(fp->symbols_per_slot*sizeof(uint32_t *)); AssertFatal(pusch_dmrs[slot]!=NULL, "init_nr_ue_signal: pusch_dmrs for slot %d - malloc failed\n", slot); for (symb=0; symbsymbols_per_slot; symb++) { - pusch_dmrs[slot][symb] = (uint32_t **)malloc16(NR_MAX_NB_CODEWORDS*sizeof(uint32_t *)); + pusch_dmrs[slot][symb] = (uint32_t *)malloc16(pusch_dmrs_init_length*sizeof(uint32_t)); AssertFatal(pusch_dmrs[slot][symb]!=NULL, "init_nr_ue_signal: pusch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb); - for (q=0; qN_RB_DL<<1)*3)>>5)+1; //PDCCH DMRS init (gNB offset = 0) ue->nr_gold_pdcch[0] = (uint32_t ***)malloc16(fp->slots_per_frame*sizeof(uint32_t **)); uint32_t ***pdcch_dmrs = ue->nr_gold_pdcch[0]; @@ -274,7 +275,7 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, AssertFatal(pdcch_dmrs[slot]!=NULL, "NR init: pdcch_dmrs for slot %d - malloc failed\n", slot); for (int symb=0; symbsymbols_per_slot; symb++) { - pdcch_dmrs[slot][symb] = (uint32_t *)malloc16(NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD*sizeof(uint32_t)); + pdcch_dmrs[slot][symb] = (uint32_t *)malloc16(pdcch_dmrs_init_length*sizeof(uint32_t)); AssertFatal(pdcch_dmrs[slot][symb]!=NULL, "NR init: pdcch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb); } } @@ -282,6 +283,9 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, ue->scramblingID_pdcch = fp->Nid_cell; nr_gold_pdcch(ue,fp->Nid_cell); + // ceil(((NB_RB*6(k)*2(QPSK)/32) // 3 RE *2(QPSK) + int pdsch_dmrs_init_length = ((fp->N_RB_DL*12)>>5)+1; + //PDSCH DMRS init (eNB offset = 0) ue->nr_gold_pdsch[0] = (uint32_t ****)malloc16(fp->slots_per_frame*sizeof(uint32_t ***)); uint32_t ****pdsch_dmrs = ue->nr_gold_pdsch[0]; @@ -295,7 +299,7 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, AssertFatal(pdsch_dmrs[slot][symb]!=NULL, "NR init: pdsch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb); for (int q=0; qN_RB_DL, Ncp); - if (Ncp == NFAPI_CP_EXTENDED) AssertFatal(mu == NR_MU_2,"Invalid cyclic prefix %d for numerology index %d\n", Ncp, mu); diff --git a/openair1/PHY/NR_REFSIG/nr_gold.c b/openair1/PHY/NR_REFSIG/nr_gold.c index 7930839832..7f81529964 100644 --- a/openair1/PHY/NR_REFSIG/nr_gold.c +++ b/openair1/PHY/NR_REFSIG/nr_gold.c @@ -60,6 +60,7 @@ void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid) uint8_t reset; NR_DL_FRAME_PARMS *fp = &gNB->frame_parms; uint32_t ***pdcch_dmrs = gNB->nr_gold_pdcch_dmrs; + int pdcch_dmrs_init_length = (((fp->N_RB_DL<<1)*3)>>5)+1; for (uint8_t slot=0; slotslots_per_frame; slot++) { for (uint8_t symb=0; symbsymbols_per_slot; symb++) { @@ -67,7 +68,7 @@ void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid) reset = 1; x2 = ((1<<17) * (fp->symbols_per_slot*slot+symb+1) * ((Nid<<1)+1) + (Nid<<1)); LOG_D(PHY,"PDCCH DMRS slot %d, symb %d, Nid %d, x2 %x\n",slot,symb,Nid,x2); - for (uint32_t n=0; nframe_parms; uint32_t ****pdsch_dmrs = gNB->nr_gold_pdsch_dmrs; - + int pdsch_dmrs_init_length = ((fp->N_RB_DL*12)>>5)+1; uint16_t N_n_scid[NR_MAX_NB_CODEWORDS]={Nid, Nid}; // Not correct, appropriate scrambling IDs have to be updated to support DCI 1_1 uint8_t n_scid=0; // again works only for 1_0 for (uint8_t slot=0; slotslots_per_frame; slot++) { @@ -93,13 +94,13 @@ void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid) reset = 1; x2 = ((1<<17) * (fp->symbols_per_slot*slot+symb+1) * ((N_n_scid[n_scid]<<1)+1) +((N_n_scid[n_scid]<<1)+n_scid)); LOG_D(PHY,"PDSCH DMRS slot %d, symb %d x2 %x, N_n_scid %d,n_scid %d\n",slot,symb,x2,N_n_scid[n_scid],n_scid); - for (uint32_t n=0; nframe_parms; unsigned short l; + int pusch_dmrs_init_length = ((fp->N_RB_UL*12)>>5)+1; for (nscid=0; nscid<2; nscid++) { nid = Nid[nscid]; @@ -122,7 +124,7 @@ void nr_gold_pusch(PHY_VARS_gNB* gNB, uint32_t *Nid) { x2 = ((1<<17) * (fp->symbols_per_slot*ns+l+1) * ((nid<<1)+1) +((nid<<1)+nscid)); LOG_D(PHY,"DMRS slot %d, symb %d x2 %x\n",ns,l,x2); - for (n=0; nnr_gold_pusch_dmrs[nscid][ns][l][n] = lte_gold_generic(&x1, &x2, reset); reset = 0; } @@ -138,6 +140,7 @@ void nr_init_csi_rs(PHY_VARS_gNB* gNB, uint32_t Nid) uint32_t ***csi_rs = gNB->nr_gold_csi_rs; uint32_t x1, x2; uint8_t reset; + int csi_dmrs_init_length = ((fp->N_RB_DL<<4)>>5)+1; for (uint8_t slot=0; slotslots_per_frame; slot++) { for (uint8_t symb=0; symbsymbols_per_slot; symb++) { @@ -145,7 +148,7 @@ void nr_init_csi_rs(PHY_VARS_gNB* gNB, uint32_t Nid) reset = 1; x2 = ((1<<10) * (fp->symbols_per_slot*slot+symb+1) * ((Nid<<1)+1) + (Nid)); - for (uint32_t n=0; nframe_parms.N_RB_DL<<1)*3)>>5)+1; for (ns=0; nsframe_parms.slots_per_frame; ns++) { @@ -66,7 +67,7 @@ void nr_gold_pdcch(PHY_VARS_NR_UE* ue, x2tmp0 = ((ue->frame_parms.symbols_per_slot*ns+l+1)*((nid<<1)+1))<<17; x2 = (x2tmp0+(nid<<1))%(1<<31); //cinit - for (n=0; nnr_gold_pdcch[0][ns][l][n] = lte_gold_generic(&x1, &x2, reset); reset = 0; } @@ -82,6 +83,7 @@ void nr_gold_pdsch(PHY_VARS_NR_UE* ue, int nscid; unsigned int nid; uint8_t reset; + int pdsch_dmrs_init_length = ((ue->frame_parms.N_RB_DL*12)>>5)+1; /// to be updated from higher layer //unsigned short lbar = 0; @@ -98,7 +100,7 @@ void nr_gold_pdsch(PHY_VARS_NR_UE* ue, x2 = (x2tmp0+(nid<<1)+nscid)%(1<<31); //cinit LOG_D(PHY,"UE DMRS slot %d, symb %d, x2 %x, nscid %d\n",ns,l,x2,nscid); - for (n=0; nnr_gold_pdsch[0][ns][l][nscid][n] = lte_gold_generic(&x1, &x2, reset); reset = 0; } @@ -112,9 +114,10 @@ void nr_init_pusch_dmrs(PHY_VARS_NR_UE* ue, uint8_t n_scid) { uint32_t x1, x2, n; - uint8_t reset, slot, symb, q; + uint8_t reset, slot, symb; NR_DL_FRAME_PARMS *fp = &ue->frame_parms; - uint32_t ****pusch_dmrs = ue->nr_gold_pusch_dmrs; + uint32_t ***pusch_dmrs = ue->nr_gold_pusch_dmrs; + int pusch_dmrs_init_length = ((fp->N_RB_UL*12)>>5)+1; for (slot=0; slotslots_per_frame; slot++) { @@ -123,13 +126,10 @@ void nr_init_pusch_dmrs(PHY_VARS_NR_UE* ue, reset = 1; x2 = ((1<<17) * (fp->symbols_per_slot*slot+symb+1) * ((N_n_scid[n_scid]<<1)+1) +((N_n_scid[n_scid]<<1)+n_scid)); - for (n=0; ncommon_vars.txdataF; int txdataF_offset = (slot%2)*frame_parms.samples_per_slot_wCP; uint32_t **gold_csi_rs = gNB->nr_gold_csi_rs[slot]; - int16_t mod_csi[frame_parms.symbols_per_slot][NR_MAX_CSI_RS_LENGTH>>1] __attribute__((aligned(16)));; + //*8(max allocation per RB)*2(QPSK)) + int csi_rs_length = frame_parms.N_RB_DL<<4; + int16_t mod_csi[frame_parms.symbols_per_slot][csi_rs_length>>1] __attribute__((aligned(16)));; uint16_t b = csi_params.freq_domain; uint16_t n, csi_bw, csi_start, p, k, l, mprime, na, kpn, csi_length; uint8_t size, ports, kprime, lprime, i, gs; @@ -59,7 +61,7 @@ void nr_generate_csi_rs(PHY_VARS_gNB *gNB, for (uint8_t symb=0; symb>5)+1; n++) { gold_csi_rs[symb][n] = lte_gold_generic(&x1, &x2, reset); reset = 0; } diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c index 13ca3bde6b..c1de1648ef 100644 --- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c +++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c @@ -207,7 +207,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, /////////////////////////DMRS Modulation///////////////////////// /////////// - uint32_t ***pusch_dmrs = UE->nr_gold_pusch_dmrs[slot]; + uint32_t **pusch_dmrs = UE->nr_gold_pusch_dmrs[slot]; uint16_t n_dmrs = (pusch_pdu->bwp_start + start_rb + nb_rb)*((dmrs_type == pusch_dmrs_type1) ? 6:4); int16_t mod_dmrs[n_dmrs<<1] __attribute((aligned(16))); /////////// @@ -369,7 +369,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, // TODO: performance improvement, we can skip the modulation of DMRS symbols outside the bandwidth part // Perform this on gold sequence, not required when SC FDMA operation is done, LOG_D(PHY,"DMRS in symbol %d\n",l); - nr_modulation(pusch_dmrs[l][0], n_dmrs*2, DMRS_MOD_ORDER, mod_dmrs); // currently only codeword 0 is modulated. Qm = 2 as DMRS is QPSK modulated + nr_modulation(pusch_dmrs[l], n_dmrs*2, DMRS_MOD_ORDER, mod_dmrs); // Qm = 2 as DMRS is QPSK modulated } else { dmrs_idx = 0; } @@ -379,7 +379,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, if(is_ptrs_symbol(l, ulsch_ue->ptrs_symbols)) { is_ptrs_sym = 1; - nr_modulation(pusch_dmrs[l][0], nb_rb, DMRS_MOD_ORDER, mod_ptrs); + nr_modulation(pusch_dmrs[l], nb_rb, DMRS_MOD_ORDER, mod_ptrs); } } diff --git a/openair1/PHY/defs_nr_UE.h b/openair1/PHY/defs_nr_UE.h index 7aca95cb1e..65a9fea786 100644 --- a/openair1/PHY/defs_nr_UE.h +++ b/openair1/PHY/defs_nr_UE.h @@ -862,7 +862,7 @@ typedef struct { uint16_t scramblingID_pdcch; /// PUSCH DMRS sequence - uint32_t ****nr_gold_pusch_dmrs; + uint32_t ***nr_gold_pusch_dmrs; uint32_t X_u[64][839]; diff --git a/openair1/PHY/defs_nr_common.h b/openair1/PHY/defs_nr_common.h index 8245da9737..1b99160a23 100644 --- a/openair1/PHY/defs_nr_common.h +++ b/openair1/PHY/defs_nr_common.h @@ -67,22 +67,9 @@ #define NR_PBCH_DMRS_LENGTH 144 // in mod symbols #define NR_PBCH_DMRS_LENGTH_DWORD 10 // ceil(2(QPSK)*NR_PBCH_DMRS_LENGTH/32) -/*These max values are for the gold sequences which are generated at init for the - * full carrier bandwidth*/ -#define NR_MAX_PDCCH_DMRS_INIT_LENGTH ((NR_MAX_NB_RB<<1)*3) // 3 symbols *2(QPSK) -#define NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD 52 // ceil(NR_MAX_PDCCH_DMRS_LENGTH/32) /*used for the resource mapping*/ #define NR_MAX_PDCCH_DMRS_LENGTH 576 // 16(L)*2(QPSK)*3(3 DMRS symbs per REG)*6(REG per CCE) -#define NR_MAX_PDSCH_DMRS_LENGTH 3300 //275*6(k)*2(QPSK real+imag) -#define NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD 104 // ceil(NR_MAX_PDSCH_DMRS_LENGTH/32) - -#define NR_MAX_CSI_RS_LENGTH 4400 //275*8(max allocation per RB)*2(QPSK) -#define NR_MAX_CSI_RS_INIT_LENGTH_DWORD 138 // ceil(NR_MAX_CSI_RS_LENGTH/32) - -#define NR_MAX_PUSCH_DMRS_LENGTH NR_MAX_PDSCH_DMRS_LENGTH -#define NR_MAX_PUSCH_DMRS_INIT_LENGTH_DWORD NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD - #define NR_MAX_DCI_PAYLOAD_SIZE 64 #define NR_MAX_DCI_SIZE 1728 //16(L)*2(QPSK)*9(12 RE per REG - 3(DMRS))*6(REG per CCE) #define NR_MAX_DCI_SIZE_DWORD 54 // ceil(NR_MAX_DCI_SIZE/32)