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UHD interfacing (master clock 30.72, bandwidths on 5/10/20 @ 20 MHz), RX gain calibration back to normal.

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gauthier
2016-04-18 20:44:30 +02:00
parent ccc6faf578
commit cac9ac4041
1 changed files with 7 additions and 7 deletions
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targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
+7 -7
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@@ -617,19 +617,19 @@ extern "C" {
openair0_cfg[0].tx_scheduling_advance = 8*openair0_cfg[0].samples_per_packet; openair0_cfg[0].tx_scheduling_advance = 8*openair0_cfg[0].samples_per_packet;
break; break;
case 15360000: case 15360000:
s->usrp->set_master_clock_rate(15.36e06); s->usrp->set_master_clock_rate(30.72e06);
openair0_cfg[0].samples_per_packet = 2048; openair0_cfg[0].samples_per_packet = 2048;
openair0_cfg[0].tx_sample_advance = 153; openair0_cfg[0].tx_sample_advance = 153;
openair0_cfg[0].tx_bw = 10e6; openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 10e6; openair0_cfg[0].rx_bw = 20e6;
openair0_cfg[0].tx_scheduling_advance = 10240; openair0_cfg[0].tx_scheduling_advance = 10240;
break; break;
case 7680000: case 7680000:
s->usrp->set_master_clock_rate(7.68e6); s->usrp->set_master_clock_rate(30.72e6);
openair0_cfg[0].samples_per_packet = 1024; openair0_cfg[0].samples_per_packet = 1024;
openair0_cfg[0].tx_sample_advance = 103; openair0_cfg[0].tx_sample_advance = 153;
openair0_cfg[0].tx_bw = 5e6; openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 5e6; openair0_cfg[0].rx_bw = 20e6;
openair0_cfg[0].tx_scheduling_advance = 5*openair0_cfg[0].samples_per_packet; openair0_cfg[0].tx_scheduling_advance = 5*openair0_cfg[0].samples_per_packet;
break; break;
case 1920000: case 1920000: