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This commit is contained in:
Louis Adrien Dufrene
2018-11-20 16:39:05 +01:00
parent d082b50896
commit cf07c4d394
3 changed files with 71 additions and 71 deletions
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openair2/COMMON/rrc_messages_types.h
+65 -65
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@@ -33,9 +33,9 @@
#include "rrc_types.h"
#include "s1ap_messages_types.h"
#ifdef CMAKER
#include "LTE_SystemInformationBlockType2.h"
#include "LTE_SystemInformationBlockType2.h"
#else
#include "RRC/LTE/MESSAGES/LTE_SystemInformationBlockType2.h"
#include "RRC/LTE/MESSAGES/LTE_SystemInformationBlockType2.h"
#endif
#include "LTE_SL-OffsetIndicator-r12.h"
#include "LTE_SubframeBitmapSL-r12.h"
@@ -47,19 +47,19 @@
//-------------------------------------------------------------------------------------------//
// Messages for RRC logging
#if defined(DISABLE_ITTI_XER_PRINT)
#include "LTE_BCCH-DL-SCH-Message.h"
#include "LTE_DL-CCCH-Message.h"
#include "LTE_DL-DCCH-Message.h"
#include "LTE_UE-EUTRA-Capability.h"
#include "LTE_UL-CCCH-Message.h"
#include "LTE_UL-DCCH-Message.h"
#include "LTE_BCCH-DL-SCH-Message.h"
#include "LTE_DL-CCCH-Message.h"
#include "LTE_DL-DCCH-Message.h"
#include "LTE_UE-EUTRA-Capability.h"
#include "LTE_UL-CCCH-Message.h"
#include "LTE_UL-DCCH-Message.h"
typedef BCCH_DL_SCH_Message_t RrcDlBcchMessage;
typedef DL_CCCH_Message_t RrcDlCcchMessage;
typedef DL_DCCH_Message_t RrcDlDcchMessage;
typedef UE_EUTRA_Capability_t RrcUeEutraCapability;
typedef UL_CCCH_Message_t RrcUlCcchMessage;
typedef UL_DCCH_Message_t RrcUlDcchMessage;
typedef BCCH_DL_SCH_Message_t RrcDlBcchMessage;
typedef DL_CCCH_Message_t RrcDlCcchMessage;
typedef DL_DCCH_Message_t RrcDlDcchMessage;
typedef UE_EUTRA_Capability_t RrcUeEutraCapability;
typedef UL_CCCH_Message_t RrcUlCcchMessage;
typedef UL_DCCH_Message_t RrcUlDcchMessage;
#endif
//-------------------------------------------------------------------------------------------//
@@ -103,7 +103,7 @@ typedef struct RrcConfigurationReq_s {
uint8_t num_plmn;
uint32_t rrc_inactivity_timer_thres; // for testing, maybe change later
paging_drx_t default_drx;
int16_t nb_cc;
lte_frame_type_t frame_type[MAX_NUM_CCs];
@@ -125,9 +125,9 @@ typedef struct RrcConfigurationReq_s {
long pucch_delta_shift[MAX_NUM_CCs];
long pucch_nRB_CQI[MAX_NUM_CCs];
long pucch_nCS_AN[MAX_NUM_CCs];
//#if (LTE_RRC_VERSION < MAKE_VERSION(10, 0, 0))
//#if (LTE_RRC_VERSION < MAKE_VERSION(10, 0, 0))
long pucch_n1_AN[MAX_NUM_CCs];
//#endif
//#endif
long pdsch_referenceSignalPower[MAX_NUM_CCs];
long pdsch_p_b[MAX_NUM_CCs];
long pusch_n_SB[MAX_NUM_CCs];
@@ -189,7 +189,7 @@ typedef struct RrcConfigurationReq_s {
LTE_SL_OffsetIndicator_r12_PR rxPool_ResourceConfig_offsetIndicator_present[MAX_NUM_CCs];
long rxPool_ResourceConfig_offsetIndicator_choice[MAX_NUM_CCs];
LTE_SubframeBitmapSL_r12_PR rxPool_ResourceConfig_subframeBitmap_present[MAX_NUM_CCs];
char* rxPool_ResourceConfig_subframeBitmap_choice_bs_buf[MAX_NUM_CCs];
char *rxPool_ResourceConfig_subframeBitmap_choice_bs_buf[MAX_NUM_CCs];
long rxPool_ResourceConfig_subframeBitmap_choice_bs_size[MAX_NUM_CCs];
long rxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused[MAX_NUM_CCs];
@@ -205,7 +205,7 @@ typedef struct RrcConfigurationReq_s {
LTE_SL_OffsetIndicator_r12_PR discRxPool_ResourceConfig_offsetIndicator_present[MAX_NUM_CCs];
long discRxPool_ResourceConfig_offsetIndicator_choice[MAX_NUM_CCs];
LTE_SubframeBitmapSL_r12_PR discRxPool_ResourceConfig_subframeBitmap_present[MAX_NUM_CCs];
char* discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf[MAX_NUM_CCs];
char *discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf[MAX_NUM_CCs];
long discRxPool_ResourceConfig_subframeBitmap_choice_bs_size[MAX_NUM_CCs];
long discRxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused[MAX_NUM_CCs];
//for discRxPoolPS
@@ -219,7 +219,7 @@ typedef struct RrcConfigurationReq_s {
LTE_SL_OffsetIndicator_r12_PR discRxPoolPS_ResourceConfig_offsetIndicator_present[MAX_NUM_CCs];
long discRxPoolPS_ResourceConfig_offsetIndicator_choice[MAX_NUM_CCs];
LTE_SubframeBitmapSL_r12_PR discRxPoolPS_ResourceConfig_subframeBitmap_present[MAX_NUM_CCs];
char* discRxPoolPS_ResourceConfig_subframeBitmap_choice_bs_buf[MAX_NUM_CCs];
char *discRxPoolPS_ResourceConfig_subframeBitmap_choice_bs_buf[MAX_NUM_CCs];
long discRxPoolPS_ResourceConfig_subframeBitmap_choice_bs_size[MAX_NUM_CCs];
long discRxPoolPS_ResourceConfig_subframeBitmap_choice_bs_bits_unused[MAX_NUM_CCs];
} RrcConfigurationReq;
@@ -231,69 +231,69 @@ typedef struct NbIoTRrcConfigurationReq_s {
uint16_t tac;
uint16_t mcc;
uint16_t mnc;
uint8_t mnc_digit_length;
lte_frame_type_t frame_type;
uint16_t mcc;
uint16_t mnc;
uint8_t mnc_digit_length;
lte_frame_type_t frame_type;
uint8_t tdd_config;
uint8_t tdd_config_s;
lte_prefix_type_t prefix_type;
lte_prefix_type_t prefix_type_UL;
lte_prefix_type_t prefix_type_UL;
int16_t eutra_band;
uint32_t downlink_frequency;
int32_t uplink_frequency_offset;
int16_t Nid_cell;// for testing, change later
int16_t N_RB_DL;// for testing, change later
//RACH
long rach_raResponseWindowSize_NB;
long rach_macContentionResolutionTimer_NB;
long rach_powerRampingStep_NB;
long rach_preambleInitialReceivedTargetPower_NB;
long rach_preambleTransMax_CE_NB;
long rach_raResponseWindowSize_NB;
long rach_macContentionResolutionTimer_NB;
long rach_powerRampingStep_NB;
long rach_preambleInitialReceivedTargetPower_NB;
long rach_preambleTransMax_CE_NB;
//BCCH
long bcch_modificationPeriodCoeff_NB;
long bcch_modificationPeriodCoeff_NB;
//PCCH
long pcch_defaultPagingCycle_NB;
long pcch_nB_NB;
long pcch_npdcch_NumRepetitionPaging_NB;
long pcch_defaultPagingCycle_NB;
long pcch_nB_NB;
long pcch_npdcch_NumRepetitionPaging_NB;
//NPRACH
long nprach_CP_Length;
long nprach_rsrp_range;
long nprach_Periodicity[MAX_NUM_NBIOT_CELEVELS];
long nprach_StartTime[MAX_NUM_NBIOT_CELEVELS];
long nprach_SubcarrierOffset[MAX_NUM_NBIOT_CELEVELS];
long nprach_NumSubcarriers[MAX_NUM_NBIOT_CELEVELS];
long numRepetitionsPerPreambleAttempt_NB[MAX_NUM_NBIOT_CELEVELS];
long nprach_SubcarrierMSG3_RangeStart;
long maxNumPreambleAttemptCE_NB;
long npdcch_NumRepetitions_RA[MAX_NUM_NBIOT_CELEVELS];
long npdcch_StartSF_CSS_RA[MAX_NUM_NBIOT_CELEVELS];
long npdcch_Offset_RA[MAX_NUM_NBIOT_CELEVELS];
long nprach_CP_Length;
long nprach_rsrp_range;
long nprach_Periodicity[MAX_NUM_NBIOT_CELEVELS];
long nprach_StartTime[MAX_NUM_NBIOT_CELEVELS];
long nprach_SubcarrierOffset[MAX_NUM_NBIOT_CELEVELS];
long nprach_NumSubcarriers[MAX_NUM_NBIOT_CELEVELS];
long numRepetitionsPerPreambleAttempt_NB[MAX_NUM_NBIOT_CELEVELS];
long nprach_SubcarrierMSG3_RangeStart;
long maxNumPreambleAttemptCE_NB;
long npdcch_NumRepetitions_RA[MAX_NUM_NBIOT_CELEVELS];
long npdcch_StartSF_CSS_RA[MAX_NUM_NBIOT_CELEVELS];
long npdcch_Offset_RA[MAX_NUM_NBIOT_CELEVELS];
//NPDSCH
long npdsch_nrs_Power;
long npdsch_nrs_Power;
//NPUSCH
long npusch_ack_nack_numRepetitions_NB;
long npusch_srs_SubframeConfig_NB;
long npusch_threeTone_CyclicShift_r13;
long npusch_sixTone_CyclicShift_r13;
BOOLEAN_t npusch_groupHoppingEnabled;
long npusch_groupAssignmentNPUSCH_r13;
long npusch_ack_nack_numRepetitions_NB;
long npusch_srs_SubframeConfig_NB;
long npusch_threeTone_CyclicShift_r13;
long npusch_sixTone_CyclicShift_r13;
BOOLEAN_t npusch_groupHoppingEnabled;
long npusch_groupAssignmentNPUSCH_r13;
//DL_GapConfig
long dl_GapThreshold_NB;
long dl_GapPeriodicity_NB;
long dl_GapDurationCoeff_NB;
long dl_GapThreshold_NB;
long dl_GapPeriodicity_NB;
long dl_GapDurationCoeff_NB;
//Uplink power control Common
long npusch_p0_NominalNPUSCH;
long npusch_alpha;
long deltaPreambleMsg3;
long npusch_p0_NominalNPUSCH;
long npusch_alpha;
long deltaPreambleMsg3;
//UE timers and constants
long ue_TimersAndConstants_t300_NB;
long ue_TimersAndConstants_t301_NB;
long ue_TimersAndConstants_t310_NB;
long ue_TimersAndConstants_t311_NB;
long ue_TimersAndConstants_n310_NB;
long ue_TimersAndConstants_n311_NB;
long ue_TimersAndConstants_t300_NB;
long ue_TimersAndConstants_t301_NB;
long ue_TimersAndConstants_t310_NB;
long ue_TimersAndConstants_t311_NB;
long ue_TimersAndConstants_n310_NB;
long ue_TimersAndConstants_n311_NB;
} NbIoTRrcConfigurationReq;