first commit to schedule reception of csi measrep
This commit is contained in:
@@ -470,8 +470,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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// This schedule SR
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// This schedule SR
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// TODO
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// TODO
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// This schedule CSI
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// This schedule CSI measurement reporting
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// TODO
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if(UE_list->fiveG_connected[UE_id] == true)
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nr_csi_meas_reporting(module_idP, UE_id, frame, slot, slots_per_frame[*scc->ssbSubcarrierSpacing]);
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// This schedule RA procedure if not in phy_test mode
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// This schedule RA procedure if not in phy_test mode
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// Otherwise already consider 5G already connected
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// Otherwise already consider 5G already connected
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@@ -508,7 +509,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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if (UE_list->fiveG_connected[UE_id] && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot%num_slots_per_tdd))) {
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if (UE_list->fiveG_connected[UE_id] && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot%num_slots_per_tdd))) {
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ue_sched_ctl->current_harq_pid = slot % num_slots_per_tdd;
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ue_sched_ctl->current_harq_pid = slot % num_slots_per_tdd;
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nr_update_pucch_scheduling(module_idP, UE_id, frame, slot, num_slots_per_tdd,&pucch_sched);
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nr_acknack_scheduling(module_idP, UE_id, frame, slot, num_slots_per_tdd,&pucch_sched);
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nr_schedule_uss_dlsch_phytest(module_idP, frame, slot, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL);
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nr_schedule_uss_dlsch_phytest(module_idP, frame, slot, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL);
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// resetting ta flag
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// resetting ta flag
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gNB->ta_len = 0;
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gNB->ta_len = 0;
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@@ -1554,13 +1554,86 @@ void get_pdsch_to_harq_feedback(int Mod_idP,
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}
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}
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}
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}
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void nr_csi_meas_reporting(int Mod_idP,
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int UE_id,
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frame_t frame,
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sub_frame_t slot,
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int n_slots_frame) {
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NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
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NR_sched_pucch *curr_pucch;
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NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
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NR_CSI_MeasConfig_t *csi_measconfig = secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup;
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AssertFatal(csi_measconfig->csi_ReportConfigToAddModList->list.count>0,"NO CSI report configuration available");
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// TODO for now we assume only one csi report config available
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NR_CSI_ReportConfig_t *csirep = csi_measconfig->csi_ReportConfigToAddModList->list.array[0];
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AssertFatal(csirep->reportConfigType.choice.periodic!=NULL,"Only periodic CSI reporting is implemented currently");
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int period, offset;
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NR_CSI_ReportPeriodicityAndOffset_PR p_and_o = csirep->reportConfigType.choice.periodic->reportSlotConfig.present;
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switch(p_and_o){
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case NR_CSI_ReportPeriodicityAndOffset_PR_slots4:
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period = 4;
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offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots4;
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break;
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case NR_CSI_ReportPeriodicityAndOffset_PR_slots5:
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period = 5;
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offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots5;
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break;
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case NR_CSI_ReportPeriodicityAndOffset_PR_slots8:
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period = 8;
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offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots8;
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break;
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case NR_CSI_ReportPeriodicityAndOffset_PR_slots10:
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period = 10;
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offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots10;
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break;
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case NR_CSI_ReportPeriodicityAndOffset_PR_slots16:
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period = 16;
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offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots16;
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break;
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case NR_CSI_ReportPeriodicityAndOffset_PR_slots20:
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period = 20;
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offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots20;
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break;
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case NR_CSI_ReportPeriodicityAndOffset_PR_slots40:
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period = 40;
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offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots40;
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break;
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case NR_CSI_ReportPeriodicityAndOffset_PR_slots80:
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period = 80;
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offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots80;
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break;
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case NR_CSI_ReportPeriodicityAndOffset_PR_slots160:
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period = 160;
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offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots160;
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break;
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case NR_CSI_ReportPeriodicityAndOffset_PR_slots320:
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period = 320;
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offset = csirep->reportConfigType.choice.periodic->reportSlotConfig.choice.slots320;
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break;
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default:
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AssertFatal(1==0,"No periodicity and offset resource found in CSI report");
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}
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// schedule csi measurement reception according to 5.2.1.4 in 38.214
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if ( ((n_slots_frame*frame + slot - offset)%period) == 0) {
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}
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}
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// function to update pucch scheduling parameters in UE list when a USS DL is scheduled
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// function to update pucch scheduling parameters in UE list when a USS DL is scheduled
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void nr_update_pucch_scheduling(int Mod_idP,
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void nr_acknack_scheduling(int Mod_idP,
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int UE_id,
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int UE_id,
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frame_t frameP,
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frame_t frameP,
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sub_frame_t slotP,
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sub_frame_t slotP,
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int slots_per_tdd,
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int slots_per_tdd,
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int *pucch_id) {
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int *pucch_id) {
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NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon;
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NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon;
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NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
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NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
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@@ -1579,25 +1652,28 @@ void nr_update_pucch_scheduling(int Mod_idP,
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// for each possible ul or mixed slot
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// for each possible ul or mixed slot
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for (k=0; k<nr_ulmix_slots; k++) {
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for (k=0; k<nr_ulmix_slots; k++) {
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curr_pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k];
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curr_pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k];
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// if there is free room in current pucch structure
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//if it is possible to schedule acknack in current pucch (no exclusive csi pucch)
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if (curr_pucch->dai_c<MAX_ACK_BITS) {
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if ((curr_pucch->csi_bits == 0) || (curr_pucch->simultaneous_harqcsi==true)) {
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curr_pucch->frame = frameP;
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// if there is free room in current pucch structure
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curr_pucch->dai_c++;
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if (curr_pucch->dai_c<MAX_ACK_BITS) {
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curr_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource
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curr_pucch->frame = frameP;
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// first pucch occasion in first UL or MIXED slot
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curr_pucch->dai_c++;
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first_ul_slot_tdd = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots;
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curr_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource
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i = 0;
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// first pucch occasion in first UL or MIXED slot
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while (i<8 && found == 0) { // look if timing indicator is among allowed values
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first_ul_slot_tdd = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots;
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if (pdsch_to_harq_feedback[i]==(first_ul_slot_tdd+k)-(slotP % slots_per_tdd))
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i = 0;
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found = 1;
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while (i<8 && found == 0) { // look if timing indicator is among allowed values
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if (found == 0) i++;
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if (pdsch_to_harq_feedback[i]==(first_ul_slot_tdd+k)-(slotP % slots_per_tdd))
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}
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found = 1;
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if (found == 1) {
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if (found == 0) i++;
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// computing slot in which pucch is scheduled
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}
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curr_pucch->ul_slot = first_ul_slot_tdd + k + (slotP - (slotP % slots_per_tdd));
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if (found == 1) {
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curr_pucch->timing_indicator = i; // index in the list of timing indicators
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// computing slot in which pucch is scheduled
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*pucch_id = k;
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curr_pucch->ul_slot = first_ul_slot_tdd + k + (slotP - (slotP % slots_per_tdd));
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return;
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curr_pucch->timing_indicator = i; // index in the list of timing indicators
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*pucch_id = k;
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return;
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}
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}
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}
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}
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}
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}
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}
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@@ -168,12 +168,18 @@ void nr_schedule_pucch(int Mod_idP,
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frame_t frameP,
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frame_t frameP,
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sub_frame_t slotP);
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sub_frame_t slotP);
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void nr_update_pucch_scheduling(int Mod_idP,
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void nr_csi_meas_reporting(int Mod_idP,
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int UE_id,
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int UE_id,
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frame_t frameP,
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frame_t frameP,
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sub_frame_t slotP,
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sub_frame_t slotP,
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int slots_per_tdd,
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int n_slots_frame);
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int *pucch_id);
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void nr_acknack_scheduling(int Mod_idP,
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int UE_id,
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frame_t frameP,
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sub_frame_t slotP,
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int slots_per_tdd,
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int *pucch_id);
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void get_pdsch_to_harq_feedback(int Mod_idP,
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void get_pdsch_to_harq_feedback(int Mod_idP,
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int UE_id,
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int UE_id,
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@@ -248,6 +248,9 @@ typedef struct UE_info {
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typedef struct NR_sched_pucch {
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typedef struct NR_sched_pucch {
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int frame;
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int frame;
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int ul_slot;
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int ul_slot;
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bool sr_flag;
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int csi_bits;
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bool simultaneous_harqcsi;
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uint8_t dai_c;
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uint8_t dai_c;
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uint8_t timing_indicator;
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uint8_t timing_indicator;
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uint8_t resource_indicator;
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uint8_t resource_indicator;
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