From d4fe5b504d4c989bec9536cbd256d515c5c22ab4 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Tue, 26 Nov 2019 21:14:46 +0100 Subject: [PATCH] Added NR FAPI for PDCCH and moved DCI filling to MAC accordingly. compiles, still needs to be tested gNB alone with rf-simulator / RF bench. --- .../nfapi/public_inc/nfapi_nr_interface.h | 106 ++- openair1/PHY/NR_TRANSPORT/nr_dci.h | 2 +- openair1/PHY/NR_TRANSPORT/nr_dci_tools.c | 400 +---------- openair1/PHY/NR_TRANSPORT/nr_dlsch.h | 2 +- openair1/SCHED_NR/fapi_nr_l1.c | 28 +- openair1/SCHED_NR/fapi_nr_l1.h | 6 +- openair2/LAYER2/NR_MAC_gNB/config.c | 3 - .../LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c | 8 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 255 +++---- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 678 +++++++++++++----- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 24 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_common.c | 6 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 95 ++- 13 files changed, 879 insertions(+), 734 deletions(-) diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h index 2b5886c86b..a6edd76b73 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h @@ -40,7 +40,7 @@ typedef struct { // nFAPI enums typedef enum { - NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE = 0, + NFAPI_NR_DL_CONFIG_PDCCH_PDU_TYPE = 0, NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE, NFAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE, NFAPI_NR_DL_CONFIG_PCH_PDU_TYPE, @@ -464,6 +464,7 @@ typedef enum { // P7 Sub Structures +/* typedef struct { nfapi_tl_t tl; @@ -526,9 +527,21 @@ uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 uint16_t padding; } nfapi_nr_dl_config_dci_dl_pdu_rel15_t; - +*/ //#define NFAPI_NR_DL_CONFIG_REQUEST_DCI_DL_PDU_REL15_TAG 0x???? +typedef struct { + /// Number of PRGs spanning this allocation. Value : 1->275 + uint16_t numPRGs; + /// Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275 + uint16_t prgSize; + /// Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255 + uint8_t digBFInterfaces; + uint16_t PMIdx[275]; + uint16_t *beamIdx[275]; +} nr_beamforming_t; + +/* typedef struct{ nfapi_tl_t tl; uint8_t coreset_id; @@ -562,6 +575,7 @@ typedef struct{ uint32_t monitoring_symbols_in_slot; uint16_t number_of_candidates[NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS]; } nfapi_nr_search_space_t; +*/ typedef struct { nfapi_tl_t tl; @@ -593,6 +607,60 @@ typedef struct { nfapi_bf_vector_t bf_vector; } nfapi_nr_dl_config_pdcch_parameters_rel15_t; +#define MAX_DCI_CORESET 8 +#define DCI_PAYLOAD_BYTE_LEN 8 + +typedef struct { + ///Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP,Value: 1->275 + uint16_t BWPSize; + ///bandwidth part start RB index from reference CRB, [TS38.213 sec 12], Value: 0->274 + uint16_t BWPStart; + ///subcarrierSpacing [TS38.211 sec 4.2], Value:0->4 + uint8_t SubcarrierSpacing; + ///Cyclic prefix type [TS38.211 sec 4.2], 0: Normal; 1: Extended + uint8_t CyclicPrefix; + ///Starting OFDM symbol for the CORESET, Value: 0->13 + uint8_t StartSymbolIndex; +///Contiguous time duration of the CORESET in number of symbols. Corresponds to L1 parameter π‘π‘ π‘¦π‘šπ‘_𝐢𝑂𝑅𝐸𝑆𝐸𝑇 [TS38.211 sec 7.3.2.2] Value: 1,2,3 + uint8_t DurationSymbols; + ///Frequency domain resources. This is a bitmap defining non-overlapping groups of 6 PRBs in ascending order. [TS38.213 10.1]. Also, corresponds to L1 parameter CORE SET RB N [TS38.211 sec 7.3.2.2] Bitmap of uint8 array. 45 bits. + uint8_t FreqDomainResource[6]; + ///CORESET-CCE-to-REG-mapping-type [TS38.211 sec 7.3.2.2] 0: non-interleaved 1: interleaved + uint8_t CceRegMappingType; + ///The number of REGs in a bundle. Must be 6 for cceRegMappingType = nonInterleaved. For cceRegMappingType = interleaved, must belong to {2,6} if duration = 1,2 and must belong to {3,6} if duration = 3. Corresponds to parameter L. [TS38.211 sec 7.3.2.2] Value: 2,3,6 + uint8_t RegBundleSize; + ///The interleaver size. For interleaved mapping belongs to {2,3,6} and for non-interleaved mapping is NA. Corresponds to parameter R. [TS38.211 sec 7.3.2.2] Value: 2,3,6 CoreSetType + uint8_t InterleaverSize; + ///[TS38.211 sec 7.3.2.2 and sec 7.4.1.3.2] 0: CORESET is configured by the PBCH or SIB1 (subcarrier 0 of CRB0 for DMRS mapping) 1: otherwise (subcarrier 0 of CORESET) + uint8_t CoreSetType; + ///[TS38.211 sec 7.3.2.2] Not applicable for non-interleaved mapping. For interleaved mapping and a PDCCH transmitted in a CORESET configured by the PBCH or SIB1 this should be set to phy cell ID. Value: 10 bits Otherwise, for interleaved mapping this is set to 0-> max num of PRBs. Value 0-> 275 + uint16_t ShiftIndex; + ///Granularity of precoding [TS38.211 sec 7.3.2.2] Field Type Description 0: sameAsRegBundle 1: allContiguousRBs + uint8_t precoderGranularity; + ///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot + uint16_t numDlDci; + ///The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535. + uint16_t RNTI[MAX_DCI_CORESET]; + ///For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535 + uint16_t ScramblingId[MAX_DCI_CORESET]; + ///For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535 + uint16_t ScramblingRNTI[MAX_DCI_CORESET]; + ///CCE start Index used to send the DCI Value: 0->135 + uint8_t CceIndex[MAX_DCI_CORESET]; + ///Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16 + uint8_t AggregationLevel[MAX_DCI_CORESET]; + ///Precoding and Beamforming structure See Table 3-43 + nr_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET]; + ///PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps + uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET]; + ///PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB + uint8_t powerControlOffsetSS[MAX_DCI_CORESET]; +///The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BTYE_LEN*8 + uint16_t PayloadSizeBits[MAX_DCI_CORESET]; + ///DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB + uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN]; +} nfapi_nr_dl_config_pdcch_pdu_rel15_t; + typedef struct { nfapi_tl_t tl; uint16_t length; @@ -605,16 +673,7 @@ typedef struct { nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15; } nfapi_nr_dl_config_bch_pdu; -typedef struct { - /// Number of PRGs spanning this allocation. Value : 1->275 - uint16_t numPRGs; - /// Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275 - uint16_t prgSize; - /// Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255 - uint8_t digBFInterfaces; - uint16_t PMIdx[275]; - uint16_t *beamIdx[275]; -} nr_beamforming_t; + typedef struct { nfapi_tl_t tl; @@ -699,30 +758,37 @@ typedef struct { #define NFAPI_NR_DL_CONFIG_REQUEST_DLSCH_PDU_REL15_TAG typedef struct { - nfapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_pdu_rel15; + nfapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_pdu_rel15; } nfapi_nr_dl_config_dlsch_pdu; typedef struct { nfapi_tl_t tl; - nfapi_nr_search_space_t pagingSearchSpace; - nfapi_nr_coreset_t pagingControlResourceSets; + // nfapi_nr_search_space_t pagingSearchSpace; + // nfapi_nr_coreset_t pagingControlResourceSets; }nfapi_nr_dl_config_pch_pdu_rel15_t; typedef struct { + nfapi_nr_dl_config_pch_pdu_rel15_t pch_pdu_rel15; +} nfapi_nr_dl_config_pch_pdu; + +/*typedef struct { nfapi_nr_dl_config_dci_dl_pdu_rel15_t dci_dl_pdu_rel15; nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params_rel15; -} nfapi_nr_dl_config_dci_dl_pdu; + } nfapi_nr_dl_config_dci_dl_pdu;*/ +typedef struct { + nfapi_nr_dl_config_pdcch_pdu_rel15_t pdcch_pdu_rel15; +} nfapi_nr_dl_config_pdcch_pdu; typedef struct { uint8_t pdu_type; uint8_t pdu_size; union { - nfapi_nr_dl_config_dci_dl_pdu dci_dl_pdu; - nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15; - nfapi_nr_dl_config_dlsch_pdu dlsch_pdu; - nfapi_nr_dl_config_pch_pdu_rel15_t pch_pdu_rel15; + nfapi_nr_dl_config_pdcch_pdu pdcch_pdu; + nfapi_nr_dl_config_bch_pdu bch_pdu; + nfapi_nr_dl_config_dlsch_pdu dlsch_pdu; + nfapi_nr_dl_config_pch_pdu pch_pdu; }; } nfapi_nr_dl_config_request_pdu_t; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.h b/openair1/PHY/NR_TRANSPORT/nr_dci.h index 71f8dc5617..d15f91c1ff 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.h +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.h @@ -47,7 +47,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, int frame, int slot, NR_gNB_DCI_ALLOC_t *dci_alloc, - nfapi_nr_dl_config_dci_dl_pdu *pdu); + nfapi_nr_dl_config_pdcch_pdu *pdu); void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t *dci_alloc, uint16_t n_shift, uint8_t m); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index 17e2b32173..c45ec49bd3 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -124,392 +124,54 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, int frame, int slot, NR_gNB_DCI_ALLOC_t *dci_alloc, - nfapi_nr_dl_config_dci_dl_pdu *pdcch_pdu) { + nfapi_nr_dl_config_pdcch_pdu *pdcch_pdu) { uint8_t n_shift; - uint64_t *dci_pdu = (uint64_t*)dci_alloc->dci_pdu; - memset((void*)dci_pdu,0,2*sizeof(uint64_t)); - nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &pdcch_pdu->dci_dl_pdu_rel15; - nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &pdcch_pdu->pdcch_params_rel15; + nfapi_nr_dl_config_pdcch_pdu_rel15_t *pdu_rel15 = &pdcch_pdu->pdcch_pdu_rel15; - nfapi_nr_config_request_t *cfg = &gNB->gNB_config; NR_gNB_DLSCH_t *dlsch; - - - uint16_t N_RB = params_rel15->n_RB_BWP; + uint16_t N_RB = pdu_rel15->BWPSize; uint8_t fsize=0, pos=0, cand_idx=0; + for (int i=0;inumDlDci;i++) { - int dlsch_id = find_nr_dlsch(params_rel15->rnti,gNB,SEARCH_EXIST_OR_FREE); - if( (dlsch_id<0) || (dlsch_id>=NUMBER_OF_NR_DLSCH_MAX) ){ - LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",params_rel15->rnti,dlsch_id); - return; - } + uint64_t *dci_pdu = (uint64_t*)dci_alloc->dci_pdu; + memset((void*)dci_pdu,0,2*sizeof(uint64_t)); - dlsch = gNB->dlsch[dlsch_id][0]; - - dlsch->slot_tx[slot] = 1; - dlsch->harq_ids[frame%2][slot] = pdu_rel15->harq_pid; - AssertFatal(pdu_rel15->harq_pid < 8 && pdu_rel15->harq_pid >= 0, - "illegal harq_pid %d\n",pdu_rel15->harq_pid); - - dlsch->harq_mask |= (1<harq_pid); - dlsch->rnti = params_rel15->rnti; - - dci_alloc->L = 8; - memcpy((void*)&dci_alloc->pdcch_params, (void*)params_rel15, sizeof(nfapi_nr_dl_config_pdcch_parameters_rel15_t)); - dci_alloc->size = nr_get_dci_size(dci_alloc->pdcch_params.dci_format, - dci_alloc->pdcch_params.rnti_type, - N_RB, - cfg); - - AssertFatal(dci_alloc->size<=64, "DCI sizes above 64 bits not yet supported"); - n_shift = (dci_alloc->pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)? - cfg->sch_config.physical_cell_id.value : dci_alloc->pdcch_params.shift_index; - nr_fill_cce_list(dci_alloc, n_shift, cand_idx); - - /// Payload generation - switch(params_rel15->dci_format) { - - - case NFAPI_NR_DL_DCI_FORMAT_1_0: - switch(params_rel15->rnti_type) { - case NFAPI_NR_RNTI_RA: - - // Freq domain assignment - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - pos=fsize; - *dci_pdu |= ((pdu_rel15->frequency_domain_assignment&((1<size-pos)); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",pdu_rel15->frequency_domain_assignment,fsize,N_RB,dci_alloc->size-pos,*dci_pdu); -#endif - // Time domain assignment - pos+=4; - *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",pdu_rel15->time_domain_assignment,dci_alloc->size-pos,*dci_pdu); -#endif - // VRB to PRB mapping - - pos++; - *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",pdu_rel15->vrb_to_prb_mapping,dci_alloc->size-pos,*dci_pdu); -#endif - // MCS - pos+=5; - *dci_pdu |= ((uint64_t)pdu_rel15->mcs&0x1f)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"mcs %d (5 bits)=> %d (0x%lx)\n",pdu_rel15->mcs,dci_alloc->size-pos,*dci_pdu); -#endif - // TB scaling - pos+=2; - *dci_pdu |= ((uint64_t)pdu_rel15->tb_scaling&0x3)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",pdu_rel15->tb_scaling,dci_alloc->size-pos,*dci_pdu); -#endif - break; - - case NFAPI_NR_RNTI_C: - - // indicating a DL DCI format 1bit - pos++; - *dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",pdu_rel15->format_indicator,1,N_RB,dci_alloc->size-pos,*dci_pdu); -#endif - - // Freq domain assignment (275rb >> fsize = 16) - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - pos+=fsize; - *dci_pdu |= (((uint64_t)pdu_rel15->frequency_domain_assignment&((1<size-pos)); - -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->frequency_domain_assignment,fsize,dci_alloc->size-pos,*dci_pdu); -#endif - - uint16_t is_ra = 1; - for (int i=0; ifrequency_domain_assignment>>i)&1)) { - is_ra = 0; - break; + int dlsch_id = find_nr_dlsch(pdu_rel15->RNTI[i],gNB,SEARCH_EXIST_OR_FREE); + if( (dlsch_id<0) || (dlsch_id>=NUMBER_OF_NR_DLSCH_MAX) ){ + LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdu_rel15->RNTI[i],dlsch_id); + return; } - if (is_ra) //fsize are all 1 38.212 p86 - { - // ra_preamble_index 6 bits - pos+=6; - *dci_pdu |= ((pdu_rel15->ra_preamble_index&0x3f)<<(dci_alloc->size-pos)); + + dlsch = gNB->dlsch[dlsch_id][0]; + int harq_pid = 0;//extract_harq_pid(i,pdu_rel15); - // UL/SUL indicator 1 bit - pos++; - *dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos); - - // SS/PBCH index 6 bits - pos+=6; - *dci_pdu |= ((pdu_rel15->ss_pbch_index&0x3f)<<(dci_alloc->size-pos)); - - // prach_mask_index 4 bits - pos+=4; - *dci_pdu |= ((pdu_rel15->prach_mask_index&0xf)<<(dci_alloc->size-pos)); - - } //end if - - else { - - // Time domain assignment 4bit - - pos+=4; - *dci_pdu |= ((pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->time_domain_assignment,4,dci_alloc->size-pos,*dci_pdu); -#endif - - // VRB to PRB mapping 1bit - pos++; - *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->vrb_to_prb_mapping,1,dci_alloc->size-pos,*dci_pdu); -#endif - - // MCS 5bit //bit over 32, so dci_pdu ++ - pos+=5; - *dci_pdu |= (pdu_rel15->mcs&0x1f)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"MCS %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->mcs,5,dci_alloc->size-pos,*dci_pdu); -#endif - - // New data indicator 1bit - pos++; - *dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"NDI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->ndi,1,dci_alloc->size-pos,*dci_pdu); -#endif - - // Redundancy version 2bit - pos+=2; - *dci_pdu |= (pdu_rel15->rv&0x3)<<(dci_alloc->size-pos); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"RV %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->rv,2,dci_alloc->size-pos,*dci_pdu); -#endif - - // HARQ process number 4bit - pos+=4; - *dci_pdu |= ((pdu_rel15->harq_pid&0xf)<<(dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->harq_pid,4,dci_alloc->size-pos,*dci_pdu); -#endif - - // Downlink assignment index 2bit - pos+=2; - *dci_pdu |= ((pdu_rel15->dai&3)<<(dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"DAI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->dai,2,dci_alloc->size-pos,*dci_pdu); -#endif - - // TPC command for scheduled PUCCH 2bit - pos+=2; - *dci_pdu |= ((pdu_rel15->tpc&3)<<(dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"TPC %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->tpc,2,dci_alloc->size-pos,*dci_pdu); -#endif - - // PUCCH resource indicator 3bit - pos+=3; - *dci_pdu |= ((pdu_rel15->pucch_resource_indicator&0x7)<<(dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->pucch_resource_indicator,3,dci_alloc->size-pos,*dci_pdu); -#endif - - // PDSCH-to-HARQ_feedback timing indicator 3bit - pos+=3; - *dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_alloc->size-pos)); -#ifdef DEBUG_FILL_DCI - LOG_D(PHY,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->pdsch_to_harq_feedback_timing_indicator,3,dci_alloc->size-pos,*dci_pdu); -#endif - - } //end else - break; - - case NFAPI_NR_RNTI_P: - - // Short Messages Indicator – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_alloc->size-pos++); - // Short Messages – 8 bits - for (int i=0; i<8; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->short_messages>>(7-i))&1)<<(dci_alloc->size-pos++); - // Freq domain assignment 0-16 bit - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); - // Time domain assignment 4 bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); - // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); - // MCS 5 bit - for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); - - // TB scaling 2 bit - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_alloc->size-pos++); + dlsch->slot_tx[slot] = 1; + dlsch->harq_ids[frame%2][slot] = harq_pid; + AssertFatal(harq_pid < 8 && harq_pid >= 0, + "illegal harq_pid %d\n",harq_pid); + + dlsch->harq_mask |= (1<rnti = pdu_rel15->RNTI[i]; + + dci_alloc->L = pdu_rel15->AggregationLevel[i]; + memcpy((void*)&dci_alloc->pdcch_params, (void*)pdu_rel15, sizeof(nfapi_nr_dl_config_pdcch_pdu_rel15_t)); + dci_alloc->size = pdu_rel15->PayloadSizeBits[i]; - break; + + /* + LOG_D(PHY, "DCI PDU: [0]->0x%lx \t [1]->0x%lx \n",dci_pdu[0], dci_pdu[1]); + LOG_D(PHY, "DCI type %d payload (size %d) generated on candidate %d\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size, cand_idx); + */ - case NFAPI_NR_RNTI_SI: - // Freq domain assignment 0-16 bit - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); - // Time domain assignment 4 bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); - // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); - // MCS 5bit //bit over 32, so dci_pdu ++ - for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); - // Redundancy version 2bit - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); - - break; - - case NFAPI_NR_RNTI_TC: - // indicating a DL DCI format 1bit - *dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); - // Freq domain assignment 0-16 bit - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); - // Time domain assignment 4 bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); - // VRB to PRB mapping 1 bit - *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); - // MCS 5bit //bit over 32, so dci_pdu ++ - for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); - // New data indicator 1bit - *dci_pdu |= ((uint64_t)pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); - // Redundancy version 2bit - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); - // HARQ process number 4bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); - - // Downlink assignment index – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->dai>>(1-i))&1)<<(dci_alloc->size-pos++); - - // TPC command for scheduled PUCCH – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); - - - // LOG_D(PHY, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n", - // dci_pdu[0], dci_pdu[1], dci_pdu[2], dci_pdu[3]); - - - // PDSCH-to-HARQ_feedback timing indicator – 3 bits - for (int i=0; i<3; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_alloc->size-pos++); - - break; - } - break; - - case NFAPI_NR_UL_DCI_FORMAT_0_0: - switch(params_rel15->rnti_type) - { - case NFAPI_NR_RNTI_C: - // indicating a DL DCI format 1bit - *dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); - // Freq domain assignment max 16 bit - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); - // Time domain assignment 4bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); - // Frequency hopping flag – 1 bit - *dci_pdu |= ((uint64_t)pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++); - // MCS 5 bit - for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); - // New data indicator 1bit - *dci_pdu |= ((uint64_t)pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); - // Redundancy version 2bit - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); - // HARQ process number 4bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); - - // TPC command for scheduled PUSCH – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); - - // Padding bits - for(int a = pos;a<32;a++) - *dci_pdu |= ((uint64_t)pdu_rel15->padding&1)<<(dci_alloc->size-pos++); - - // UL/SUL indicator – 1 bit - if (cfg->pucch_config.pucch_GroupHopping.value) - *dci_pdu |= ((uint64_t)pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++); - - break; - - case NFAPI_NR_RNTI_TC: - - // indicating a DL DCI format 1bit - *dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); - // Freq domain assignment max 16 bit - fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); - for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); - // Time domain assignment 4bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); - // Frequency hopping flag – 1 bit - *dci_pdu |= ((uint64_t)pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++); - // MCS 5 bit - for (int i=0; i<5; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); - // New data indicator 1bit - *dci_pdu |= ((uint64_t)pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); - // Redundancy version 2bit - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); - // HARQ process number 4bit - for (int i=0; i<4; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); - - // TPC command for scheduled PUSCH – 2 bits - for (int i=0; i<2; i++) - *dci_pdu |= (((uint64_t)pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); - - // Padding bits - for(int a = pos;a<32;a++) - *dci_pdu |= ((uint64_t)pdu_rel15->padding&1)<<(dci_alloc->size-pos++); - - // UL/SUL indicator – 1 bit - if (cfg->pucch_config.pucch_GroupHopping.value) - *dci_pdu |= ((uint64_t)pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++); - - break; - } - break; + // convert pdu + dci_alloc++; } - LOG_D(PHY, "DCI PDU: [0]->0x%lx \t [1]->0x%lx \n",dci_pdu[0], dci_pdu[1]); - LOG_D(PHY, "DCI type %d payload (size %d) generated on candidate %d\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size, cand_idx); - } diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h index 1aad2dfb65..e83849a356 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h @@ -36,7 +36,7 @@ #include "PHY/defs_gNB.h" void nr_get_time_domain_allocation_type(nfapi_nr_config_request_t config, - nfapi_nr_dl_config_dci_dl_pdu dci_pdu, + nfapi_nr_dl_config_pdcch_pdu dci_pdu, nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu); void nr_check_time_alloc(uint8_t S, uint8_t L,nfapi_nr_dl_config_dlsch_pdu_rel15_t *rel15,nfapi_nr_config_request_t *cfg); diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c index 82f1e66d0b..8cb683ca76 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.c +++ b/openair1/SCHED_NR/fapi_nr_l1.c @@ -43,8 +43,8 @@ void handle_nr_nfapi_bch_pdu(PHY_VARS_gNB *gNB, uint8_t *sdu) { - AssertFatal(dl_config_pdu->bch_pdu_rel15.length == 3, "BCH PDU has length %d != 3\n", - dl_config_pdu->bch_pdu_rel15.length); + AssertFatal(dl_config_pdu->bch_pdu.bch_pdu_rel15.length == 3, "BCH PDU has length %d != 3\n", + dl_config_pdu->bch_pdu.bch_pdu_rel15.length); LOG_D(PHY,"pbch_pdu[0]: %x,pbch_pdu[1]: %x,gNB->pbch_pdu[2]: %x\n",sdu[0],sdu[1],sdu[2]); gNB->pbch_pdu[0] = sdu[2]; @@ -93,16 +93,16 @@ void handle_nr_nfapi_bch_pdu(PHY_VARS_gNB *gNB, }*/ -void handle_nfapi_nr_dci_dl_pdu(PHY_VARS_gNB *gNB, - int frame, int slot, - nfapi_nr_dl_config_dci_dl_pdu *dci_dl_pdu) { +void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB, + int frame, int slot, + nfapi_nr_dl_config_pdcch_pdu *pdcch_pdu) { int idx = slot&1; NR_gNB_PDCCH *pdcch_vars = &gNB->pdcch_vars; LOG_D(PHY,"Frame %d, Slot %d: DCI processing - populating pdcch_vars->dci_alloc[%d] proc:slot_tx:%d idx:%d pdcch_vars->num_dci:%d\n",frame,slot, pdcch_vars->num_dci, slot, idx, pdcch_vars->num_dci); // copy dci configuration into gNB structure - nr_fill_dci(gNB,frame,slot,&pdcch_vars->dci_alloc[pdcch_vars->num_dci],dci_dl_pdu); + nr_fill_dci(gNB,frame,slot,&pdcch_vars->dci_alloc[pdcch_vars->num_dci],pdcch_pdu); LOG_D(PHY,"Frame %d, Slot %d: DCI processing - populated pdcch_vars->dci_alloc[%d] proc:slot_tx:%d idx:%d pdcch_vars->num_dci:%d\n",frame,slot, pdcch_vars->num_dci, slot, idx, pdcch_vars->num_dci); @@ -158,22 +158,22 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ LOG_D(PHY,"NFAPI: dl_pdu %d : type %d\n",i,dl_config_pdu->pdu_type); switch (dl_config_pdu->pdu_type) { case NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE: - AssertFatal(dl_config_pdu->bch_pdu_rel15.pdu_index < TX_req->tx_request_body.number_of_pdus, - "bch_pdu_rel8.pdu_index>=TX_req->number_of_pdus (%d>%d)\n", - dl_config_pdu->bch_pdu_rel15.pdu_index, + AssertFatal(dl_config_pdu->bch_pdu.bch_pdu_rel15.pdu_index < TX_req->tx_request_body.number_of_pdus, + "bch_pdu.bch_pdu_rel8.pdu_index>=TX_req->number_of_pdus (%d>%d)\n", + dl_config_pdu->bch_pdu.bch_pdu_rel15.pdu_index, TX_req->tx_request_body.number_of_pdus); gNB->pbch_configured=1; do_oai=1; handle_nr_nfapi_bch_pdu(gNB, dl_config_pdu, - TX_req->tx_request_body.tx_pdu_list[dl_config_pdu->bch_pdu_rel15.pdu_index].segments[0].segment_data); + TX_req->tx_request_body.tx_pdu_list[dl_config_pdu->bch_pdu.bch_pdu_rel15.pdu_index].segments[0].segment_data); break; - case NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE: - handle_nfapi_nr_dci_dl_pdu(gNB, - frame, slot, - &dl_config_pdu->dci_dl_pdu); + case NFAPI_NR_DL_CONFIG_PDCCH_PDU_TYPE: + handle_nfapi_nr_pdcch_pdu(gNB, + frame, slot, + &dl_config_pdu->pdcch_pdu); gNB->pdcch_vars.num_dci++; gNB->pdcch_vars.num_pdsch_rnti++; do_oai=1; diff --git a/openair1/SCHED_NR/fapi_nr_l1.h b/openair1/SCHED_NR/fapi_nr_l1.h index 51169660bf..183ed00685 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.h +++ b/openair1/SCHED_NR/fapi_nr_l1.h @@ -37,9 +37,9 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO); -void handle_nfapi_nr_dci_dl_pdu(PHY_VARS_gNB *gNB, - int frame, int subframe, - nfapi_nr_dl_config_dci_dl_pdu *dcl_dl_pdu); +void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB, + int frame, int subframe, + nfapi_nr_dl_config_pdcch_pdu *dcl_dl_pdu); void handle_nr_nfapi_dlsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot, nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu, diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c index 17948f8b22..d5ac6d1c28 100644 --- a/openair2/LAYER2/NR_MAC_gNB/config.c +++ b/openair2/LAYER2/NR_MAC_gNB/config.c @@ -249,9 +249,6 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP, UE_list->secondaryCellGroup[UE_id] = secondaryCellGroup; LOG_I(PHY,"Modified UE_id %d/%x with secondaryCellGroup\n",UE_id,rnti); } - fill_nfapi_coresets_and_searchspaces(secondaryCellGroup, - UE_list->coreset[UE_id], - UE_list->search_space[UE_id]); } VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RRC_MAC_CONFIG, VCD_FUNCTION_OUT); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c index 8dbdbc93fa..ffa3c1b1d0 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c @@ -97,10 +97,10 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ memset((void *) dl_config_pdu, 0,sizeof(nfapi_nr_dl_config_request_pdu_t)); dl_config_pdu->pdu_type = NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE; dl_config_pdu->pdu_size =2 + sizeof(nfapi_nr_dl_config_bch_pdu_rel15_t); - dl_config_pdu->bch_pdu_rel15.tl.tag = NFAPI_NR_DL_CONFIG_REQUEST_BCH_PDU_REL15_TAG; - dl_config_pdu->bch_pdu_rel15.length = mib_sdu_length; - dl_config_pdu->bch_pdu_rel15.pdu_index = gNB->pdu_index[CC_id]; - dl_config_pdu->bch_pdu_rel15.transmission_power = 6000; + dl_config_pdu->bch_pdu.bch_pdu_rel15.tl.tag = NFAPI_NR_DL_CONFIG_REQUEST_BCH_PDU_REL15_TAG; + dl_config_pdu->bch_pdu.bch_pdu_rel15.length = mib_sdu_length; + dl_config_pdu->bch_pdu.bch_pdu_rel15.pdu_index = gNB->pdu_index[CC_id]; + dl_config_pdu->bch_pdu.bch_pdu_rel15.transmission_power = 6000; dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; dl_req->number_pdu++; dl_config_request->header.message_id = NFAPI_DL_CONFIG_REQUEST; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 9002d57a22..95d5f75161 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -65,7 +65,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[0]; nfapi_nr_dl_config_request_body_t *dl_req; - nfapi_nr_dl_config_request_pdu_t *dl_config_dci_pdu; + nfapi_nr_dl_config_request_pdu_t *dl_config_pdcch_pdu; nfapi_nr_dl_config_request_pdu_t *dl_config_dlsch_pdu; nfapi_tx_request_pdu_t *TX_req; @@ -89,18 +89,17 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, dl_req = &nr_mac->DL_req[CC_id].dl_config_request_body; - dl_config_dci_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; - memset((void*)dl_config_dci_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); - dl_config_dci_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE; - dl_config_dci_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_dci_dl_pdu)); + dl_config_pdcch_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; + memset((void*)dl_config_pdcch_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); + dl_config_pdcch_pdu->pdu_type = NFAPI_NR_DL_CONFIG_PDCCH_PDU_TYPE; + dl_config_pdcch_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_pdcch_pdu)); dl_config_dlsch_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu+1]; memset((void*)dl_config_dlsch_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); dl_config_dlsch_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE; dl_config_dlsch_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_dlsch_pdu)); - nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &dl_config_dci_pdu->dci_dl_pdu.dci_dl_pdu_rel15; - nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &dl_config_dci_pdu->dci_dl_pdu.pdcch_params_rel15; + nfapi_nr_dl_config_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_config_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15; nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_pdu_rel15 = &dl_config_dlsch_pdu->dlsch_pdu.dlsch_pdu_rel15; dlsch_pdu_rel15->pduBitmap = 0; @@ -157,8 +156,9 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, scc->dmrs_TypeA_Position, NrOfSymbols); + /* AssertFatal(k0==0,"k0 is not zero for Initial DL BWP TimeDomain Alloc\n"); - nr_configure_css_dci_initial(params_rel15, + nr_configure_css_dci_initial(pdcch_pdu_rel15, scs, scs, FR, @@ -169,7 +169,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, slots_per_frame, dlBWP_carrier_bandwidth); - params_rel15->first_slot = 0; pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(dlsch_pdu_rel15->rbStart, dlsch_pdu_rel15->rbSize, @@ -227,6 +226,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, dlsch_pdu_rel15->nrOfLayers, dlsch_pdu_rel15->NrOfCodewords, dlsch_pdu_rel15->mcsIndex[0]); + */ dl_req->number_dci++; dl_req->number_pdsch_rnti++; @@ -249,16 +249,13 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, int configure_fapi_dl_Tx(int Mod_idP, nfapi_nr_dl_config_request_body_t *dl_req, nfapi_tx_request_pdu_t *TX_req, - nfapi_nr_config_request_t *cfg, - nfapi_nr_coreset_t* coreset, - nfapi_nr_search_space_t* search_space, int16_t pdu_index) { gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP]; NR_COMMON_channels_t *cc = nr_mac->common_channels; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; - nfapi_nr_dl_config_request_pdu_t *dl_config_dci_pdu; + nfapi_nr_dl_config_request_pdu_t *dl_config_pdcch_pdu; nfapi_nr_dl_config_request_pdu_t *dl_config_dlsch_pdu; int TBS; @@ -266,132 +263,155 @@ int configure_fapi_dl_Tx(int Mod_idP, int bwp_id=1; + int UE_id = 0; NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list; AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n",UE_id); + + + LOG_I(PHY,"UE_id %d\n",UE_id); NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; + AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1, + "downlinkBWP_ToAddModList has %d BWP!\n", + secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count); + NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; - dl_config_dci_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; - memset((void*)dl_config_dci_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); - dl_config_dci_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE; - dl_config_dci_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_dci_dl_pdu)); + + dl_config_pdcch_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; + memset((void*)dl_config_pdcch_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); + dl_config_pdcch_pdu->pdu_type = NFAPI_NR_DL_CONFIG_PDCCH_PDU_TYPE; + dl_config_pdcch_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_pdcch_pdu)); dl_config_dlsch_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu+1]; memset((void*)dl_config_dlsch_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); dl_config_dlsch_pdu->pdu_type = NFAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE; dl_config_dlsch_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_dlsch_pdu)); - - nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &dl_config_dci_pdu->dci_dl_pdu.dci_dl_pdu_rel15; - nfapi_nr_dl_config_pdcch_parameters_rel15_t *params_rel15 = &dl_config_dci_pdu->dci_dl_pdu.pdcch_params_rel15; + + nfapi_nr_dl_config_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_config_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15; nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_pdu_rel15 = &dl_config_dlsch_pdu->dlsch_pdu.dlsch_pdu_rel15; - NR_BWP_Downlink_t *bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id-1]; - // get Coreset for PDCCH + dlsch_pdu_rel15->pduBitmap = 0; + dlsch_pdu_rel15->rnti = UE_list->rnti[UE_id]; + dlsch_pdu_rel15->pduIndex = 0; - // Get SSpace for PDCCH + // BWP + dlsch_pdu_rel15->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + dlsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + dlsch_pdu_rel15->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing; + if (bwp->bwp_Common->genericParameters.cyclicPrefix) dlsch_pdu_rel15->CyclicPrefix = *bwp->bwp_Common->genericParameters.cyclicPrefix; + else dlsch_pdu_rel15->CyclicPrefix=0; - // get TimeDomainAllocationList for PDSCH - - NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainResourceAllocationList; - if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList != NULL) - pdsch_TimeDomainResourceAllocationList = bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList->choice.setup; - else pdsch_TimeDomainResourceAllocationList = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList; - - int pdsch_start_symbol,pdsch_length; - int pdsch_K0; - // find index which has first PDCCH symbol equal to 1 and has more than 11 symbols - for (int i=0;ilist.count;i++) { - SLIV2SL(pdsch_TimeDomainResourceAllocationList->list.array[i]->startSymbolAndLength, - &pdsch_start_symbol, - &pdsch_length); - pdsch_K0 = *pdsch_TimeDomainResourceAllocationList->list.array[i]->k0; - if (pdsch_start_symbol == 1 && pdsch_length>=12) - break; - } - AssertFatal(pdsch_K0==0,"can't handle pdsch_K0 > 0\n"); - AssertFatal(pdsch_start_symbol > 0 && pdsch_start_symbol < 8, - "illegal pdsch_start_symbol %d\n",pdsch_start_symbol); - AssertFatal(pdsch_length > 0 && pdsch_length < 14, - "illegal pdsch_length %d\n",pdsch_length); - - dlsch_pdu_rel15->rnti = UE_list->rnti[UE_id]; - dlsch_pdu_rel15->rbStart = 0; - dlsch_pdu_rel15->rbSize = 50; - dlsch_pdu_rel15->StartSymbolIndex = pdsch_start_symbol; - dlsch_pdu_rel15->NrOfSymbols = pdsch_length; - dlsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(bwp->bwp_Dedicated->pdsch_Config->choice.setup, - scc->dmrs_TypeA_Position, - pdsch_length); dlsch_pdu_rel15->NrOfCodewords = 1; - dlsch_pdu_rel15->targetCodeRate[0] = 0; - dlsch_pdu_rel15->qamModOrder[0] = 0; - dlsch_pdu_rel15->mcsIndex[0] = 9; + int mcsIndex = 9; + dlsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,0); + dlsch_pdu_rel15->qamModOrder[0] = 2; + dlsch_pdu_rel15->mcsIndex[0] = mcsIndex; dlsch_pdu_rel15->mcsTable[0] = 0; dlsch_pdu_rel15->rvIndex[0] = 0; - dlsch_pdu_rel15->TBSize[0]=0; - dlsch_pdu_rel15->nrOfLayers =1; + dlsch_pdu_rel15->dataScramblingId = *scc->physCellId; + dlsch_pdu_rel15->nrOfLayers = 1; + dlsch_pdu_rel15->transmissionScheme = 0; + dlsch_pdu_rel15->refPoint = 0; // Point A + + dlsch_pdu_rel15->dmrsConfigType = 1; // 1 by default for InitialBWP + dlsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId; + dlsch_pdu_rel15->SCID = 0; + dlsch_pdu_rel15->numDmrsCdmGrpsNoData = 1; + dlsch_pdu_rel15->dmrsPorts = 1; + dlsch_pdu_rel15->resourceAlloc = 1; + dlsch_pdu_rel15->rbStart = 0; + dlsch_pdu_rel15->rbSize = 50; + dlsch_pdu_rel15->VRBtoPRBMapping = 1; // non-interleaved, check if this is ok for initialBWP + // choose shortest PDSCH + int startSymbolAndLength=0; + int StartSymbolIndex,NrOfSymbols=14,k0=0; + int StartSymbolIndex_tmp,NrOfSymbols_tmp=2; + int time_domain_assignment=0; + for (int i=0; + ibwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; + i++) { + startSymbolAndLength = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength; + SLIV2SL(startSymbolAndLength,&StartSymbolIndex_tmp,&NrOfSymbols_tmp); + if (NrOfSymbols_tmp > NrOfSymbols) { + NrOfSymbols = NrOfSymbols_tmp; + StartSymbolIndex = StartSymbolIndex_tmp; + k0 = *bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0; + time_domain_assignment = i; + } + } + dlsch_pdu_rel15->StartSymbolIndex = StartSymbolIndex; + dlsch_pdu_rel15->NrOfSymbols = NrOfSymbols; + dlsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(NULL, + scc->dmrs_TypeA_Position, + NrOfSymbols); + dci_pdu_rel15_t dci_pdu_rel15; + + dci_pdu_rel15.frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(dlsch_pdu_rel15->rbStart, + dlsch_pdu_rel15->rbSize, + NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275)); + dci_pdu_rel15.time_domain_assignment = 3; // row index used here instead of SLIV; + dci_pdu_rel15.vrb_to_prb_mapping = 1; + dci_pdu_rel15.mcs = dlsch_pdu_rel15->mcsIndex[0]; + dci_pdu_rel15.tb_scaling = 1; + + dci_pdu_rel15.ra_preamble_index = 25; + dci_pdu_rel15.format_indicator = 1; + dci_pdu_rel15.ndi = 1; + dci_pdu_rel15.rv = 0; + dci_pdu_rel15.harq_pid = 0; + dci_pdu_rel15.dai = 2; + dci_pdu_rel15.tpc = 2; + dci_pdu_rel15.pucch_resource_indicator = 7; + dci_pdu_rel15.pdsch_to_harq_feedback_timing_indicator = 7; + + LOG_I(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d, time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", + dci_pdu_rel15.frequency_domain_assignment, + dci_pdu_rel15.time_domain_assignment, + dci_pdu_rel15.vrb_to_prb_mapping, + dci_pdu_rel15.mcs, + dci_pdu_rel15.tb_scaling, + dci_pdu_rel15.ndi, + dci_pdu_rel15.rv); + + nr_configure_pdcch(pdcch_pdu_rel15, + 1, // ue-specific + scc, + bwp); + + pdcch_pdu_rel15->numDlDci = 1; + pdcch_pdu_rel15->AggregationLevel[0] = 4; + pdcch_pdu_rel15->RNTI[0]=UE_list->rnti[0]; + pdcch_pdu_rel15->CceIndex[0] = 0; + pdcch_pdu_rel15->beta_PDCCH_1_0[0]=0; + pdcch_pdu_rel15->powerControlOffsetSS[0]=1; + int dci_formats[pdcch_pdu_rel15->numDlDci]; + int rnti_types[pdcch_pdu_rel15->numDlDci]; + dci_formats[0] = NR_DL_DCI_FORMAT_1_0; + rnti_types[0] = NR_RNTI_C; - nr_configure_dci_from_pdcch_config(params_rel15, - 1, // ue specific, - 4, - 0, - scc, - bwp); - - pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(dlsch_pdu_rel15->rbStart, dlsch_pdu_rel15->rbSize, cfg->rf_config.dl_carrier_bandwidth.value); - pdu_rel15->time_domain_assignment = 3; // row index used here instead of SLIV; - pdu_rel15->vrb_to_prb_mapping = 1; - pdu_rel15->mcs = dlsch_pdu_rel15->mcsIndex[0]; - pdu_rel15->tb_scaling = 1; + fill_dci_pdu_rel15(&dci_pdu_rel15,pdcch_pdu_rel15,dci_formats,rnti_types); - pdu_rel15->ra_preamble_index = 25; - pdu_rel15->format_indicator = 1; - pdu_rel15->ndi = 1; - pdu_rel15->rv = 0; - pdu_rel15->harq_pid = 0; - pdu_rel15->dai = 2; - pdu_rel15->tpc = 2; - pdu_rel15->pucch_resource_indicator = 7; - pdu_rel15->pdsch_to_harq_feedback_timing_indicator = 7; - - LOG_I(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d, time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", - pdu_rel15->frequency_domain_assignment, - pdu_rel15->time_domain_assignment, - pdu_rel15->vrb_to_prb_mapping, - pdu_rel15->mcs, - pdu_rel15->tb_scaling, - pdu_rel15->ndi, - pdu_rel15->rv); - - params_rel15->rnti = UE_list->rnti[UE_id]; - params_rel15->rnti_type = NFAPI_NR_RNTI_C; - params_rel15->dci_format = NFAPI_NR_DL_DCI_FORMAT_1_0; + LOG_I(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ + coreset params: FreqDomainResource %llx, n_symb %d \n \ + ss params : first symb %d\n", + pdcch_pdu_rel15->RNTI[0], + rnti_types[0], + dci_formats[0], + (unsigned long long)pdcch_pdu_rel15->FreqDomainResource, + pdcch_pdu_rel15->StartSymbolIndex); - //params_rel15->aggregation_level = 1; - LOG_I(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d, config type %d\n \ - coreset params: mux_pattern %d, n_rb %d, n_symb %d, rb_offset %d \n \ - ss params : first symb %d, ss type %d\n", - params_rel15->rnti, - params_rel15->rnti_type, - params_rel15->config_type, - params_rel15->dci_format, - params_rel15->mux_pattern, - params_rel15->n_rb, - params_rel15->n_symb, - params_rel15->rb_offset, - params_rel15->first_symbol, - params_rel15->search_space_type); int x_Overhead = 0; // should be 0 for initialBWP - nr_get_tbs_dl(&dl_config_dlsch_pdu->dlsch_pdu, dl_config_dci_pdu->dci_dl_pdu,x_Overhead); + nr_get_tbs_dl(&dl_config_dlsch_pdu->dlsch_pdu, + x_Overhead); // Hardcode it for now TBS = dl_config_dlsch_pdu->dlsch_pdu.dlsch_pdu_rel15.TBSize[0]; - LOG_D(MAC, "DLSCH PDU: start PRB %d n_PRB %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS: %d\n", + LOG_I(MAC, "DLSCH PDU: start PRB %d n_PRB %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS: %d\n", dlsch_pdu_rel15->rbStart, dlsch_pdu_rel15->rbSize, dlsch_pdu_rel15->StartSymbolIndex, @@ -430,14 +450,9 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, nfapi_tx_request_pdu_t *TX_req; uint16_t rnti = 0x1234; - nfapi_nr_config_request_t *cfg = &nr_mac->config[0]; uint16_t sfn_sf = frameP << 7 | slotP; - // everything here is hard-coded to 30 kHz - //int scs = get_dlscs(cfg); - //int slots_per_frame = get_spf(cfg); - int TBS; int TBS_bytes; int lcid; @@ -475,7 +490,6 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, // Hardcode it for now TBS = 6784/8; //TBS in bytes - //nr_get_tbs_dl(&dl_config_dlsch_pdu->dlsch_pdu, dl_config_dci_pdu->dci_dl_pdu, *cfg); //TBS = dl_config_dlsch_pdu->dlsch_pdu.dlsch_pdu_rel15.transport_block_size; for (lcid = NB_RB_MAX - 1; lcid >= DTCH; lcid--) { @@ -568,6 +582,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, ta_update, // timing advance NULL, // contention res id padding, post_padding); + LOG_D(MAC, "Offset bits: %d \n", offset); // Probably there should be other actions done before that @@ -583,9 +598,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, nr_mac->UE_list.DLSCH_pdu[0][0].payload[0][offset + sdu_length_total + j] = 0; } - TBS_bytes = configure_fapi_dl_Tx(module_idP,dl_req, TX_req, cfg, - &nr_mac->UE_list.coreset[1], - &nr_mac->UE_list.search_space[1], + TBS_bytes = configure_fapi_dl_Tx(module_idP,dl_req, TX_req, nr_mac->pdu_index); #if defined(ENABLE_MAC_PAYLOAD_DEBUG) @@ -610,9 +623,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, //When the --NOS1 option is not enabled, DLSCH transmissions with random data //occur every time that the current function is called (dlsch phytest mode) else{ - TBS_bytes = configure_fapi_dl_Tx(module_idP,dl_req, TX_req, cfg, - &nr_mac->UE_list.coreset[1], - &nr_mac->UE_list.search_space[1], + TBS_bytes = configure_fapi_dl_Tx(module_idP,dl_req, TX_req, nr_mac->pdu_index[CC_id]); // HOT FIX for all zero pdu problem // ------------------------------------------------------------------------------------------------ diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index bfe6ac98f8..7639a04dc1 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -349,195 +349,524 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p } -void nr_configure_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params, - int ss_type, - int target_aggregation_level, - int cce_index, - NR_ServingCellConfigCommon_t *scc, - NR_BWP_Downlink_t *bwp) { - +void nr_configure_pdcch(nfapi_nr_dl_config_pdcch_pdu_rel15_t* pdcch_pdu, + int ss_type, + NR_ServingCellConfigCommon_t *scc, + NR_BWP_Downlink_t *bwp) { + uint16_t N_RB=NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); - /// coreset - - //ControlResourceSetId - pdcch_params->config_type = NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG; - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList!=NULL, - "controlResourceSetToAddModList is null\n"); - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count>0, - "controlResourceSetToAddModList is empty\n"); - NR_ControlResourceSet_t *coreset0 = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]; - - //frequencyDomainResources - uint8_t count=0, start=0, start_set=0; - // find coreset descriptor - - uint64_t bitmap = (((uint64_t)coreset0->frequencyDomainResources.buf[0])<<37)| - (((uint64_t)coreset0->frequencyDomainResources.buf[1])<<29)| - (((uint64_t)coreset0->frequencyDomainResources.buf[2])<<21)| - (((uint64_t)coreset0->frequencyDomainResources.buf[3])<<13)| - (((uint64_t)coreset0->frequencyDomainResources.buf[4])<<5)| - (((uint64_t)coreset0->frequencyDomainResources.buf[5])>>3); - - for (int i=0; i<45; i++) - if ((bitmap>>(44-i))&1) { - count++; - if (!start_set) { + if (bwp) { // This is not the InitialBWP + /// coreset + + //ControlResourceSetId + // pdcch_pdu->config_type = NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG; + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList!=NULL, + "controlResourceSetToAddModList is null\n"); + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count>0, + "controlResourceSetToAddModList is empty\n"); + NR_ControlResourceSet_t *coreset0 = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]; + + + pdcch_pdu->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pdcch_pdu->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275); + pdcch_pdu->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing; + pdcch_pdu->CyclicPrefix = bwp->bwp_Common->genericParameters.cyclicPrefix; + + pdcch_pdu->DurationSymbols = coreset0->duration; + + //frequencyDomainResources + /* uint8_t count=0, start=0, start_set=0; + // find coreset descriptor + + uint64_t bitmap = (((uint64_t)coreset0->frequencyDomainResources.buf[0])<<37)| + (((uint64_t)coreset0->frequencyDomainResources.buf[1])<<29)| + (((uint64_t)coreset0->frequencyDomainResources.buf[2])<<21)| + (((uint64_t)coreset0->frequencyDomainResources.buf[3])<<13)| + (((uint64_t)coreset0->frequencyDomainResources.buf[4])<<5)| + (((uint64_t)coreset0->frequencyDomainResources.buf[5])>>3); + + for (int i=0; i<45; i++) + if ((bitmap>>(44-i))&1) { + count++; + if (!start_set) { start = i; start_set = 1; + } + } + pdcch_pdu->rb_offset = 6*start; + pdcch_pdu->n_rb = 6*count; + */ + for (int i=0;i<6;i++) + pdcch_pdu->FreqDomainResource[i] = coreset0->frequencyDomainResources.buf[i]; + //duration + + + //cce-REG-MappingType + pdcch_pdu->CceRegMappingType = coreset0->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved? + NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED : NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED; + if (pdcch_pdu->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { + pdcch_pdu->RegBundleSize = (coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize); + pdcch_pdu->InterleaverSize = (coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize); + AssertFatal(scc->physCellId != NULL,"scc->physCellId is null\n"); + pdcch_pdu->ShiftIndex = coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId; + } + else { + pdcch_pdu->RegBundleSize = 0; + pdcch_pdu->InterleaverSize = 0; + pdcch_pdu->ShiftIndex = 0; + } + + pdcch_pdu->CoreSetType = 1; + + //precoderGranularity + pdcch_pdu->precoderGranularity = coreset0->precoderGranularity; + + //TCI states + // + /* + //TCI present + if (coreset0->tci_PresentInDCI != NULL) { + AssertFatal(coreset0->tci_StatesPDCCH_ToAddList != NULL,"tci_StatesPDCCH_ToAddList is null\n"); + AssertFatal(coreset0->tci_StatesPDCCH_ToAddList->list.count>0,"TCI state list is empty\n"); + for (int i=0;itci_StatesPDCCH_ToAddList->list.count;i++) { + + } + */ + + for (int i=0;inumDlDci;i++) { + //pdcch-DMRS-ScramblingID + pdcch_pdu->ScramblingId[i] = coreset0->pdcch_DMRS_ScramblingID; + + + /// SearchSpace + + // first symbol + //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored"); + int sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; + + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); + AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, + "searchPsacesToAddModList is empty\n"); + NR_SearchSpace_t *ss; + int found=0; + int target_ss = NR_SearchSpace__searchSpaceType_PR_common; + if (ss_type == 1) { + target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; + } + + for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { + ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; + AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); + AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); + if (*ss->controlResourceSetId == coreset0->controlResourceSetId && + ss->searchSpaceType->present == target_ss) { + found=1; + break; } } - pdcch_params->rb_offset = 6*start; - pdcch_params->n_rb = 6*count; - - //duration - pdcch_params->n_symb = coreset0->duration; - - //cce-REG-MappingType - pdcch_params->cr_mapping_type = coreset0->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved? - NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED : NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED; - if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { - pdcch_params->reg_bundle_size = (coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize); - pdcch_params->interleaver_size = (coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize); - AssertFatal(scc->physCellId != NULL,"scc->physCellId is null\n"); - pdcch_params->shift_index = coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId; - } - else { - pdcch_params->reg_bundle_size = 0; - pdcch_params->interleaver_size = 0; - pdcch_params->shift_index = 0; - } - - //precoderGranularity - pdcch_params->precoder_granularity = coreset0->precoderGranularity; - - //TCI states - // - /* - //TCI present - if (coreset0->tci_PresentInDCI != NULL) { - AssertFatal(coreset0->tci_StatesPDCCH_ToAddList != NULL,"tci_StatesPDCCH_ToAddList is null\n"); - AssertFatal(coreset0->tci_StatesPDCCH_ToAddList->list.count>0,"TCI state list is empty\n"); - for (int i=0;itci_StatesPDCCH_ToAddList->list.count;i++) { - - } - */ - - //pdcch-DMRS-ScramblingID - pdcch_params->scrambling_id = coreset0->pdcch_DMRS_ScramblingID; - - -/// SearchSpace - - // first symbol - //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored"); - int sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12; - - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n"); - AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0, - "searchPsacesToAddModList is empty\n"); - NR_SearchSpace_t *ss; - int found=0; - int target_ss = NR_SearchSpace__searchSpaceType_PR_common; - if (ss_type == 1) { - target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; - pdcch_params->search_space_type = NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC; - } else pdcch_params->search_space_type = NFAPI_NR_SEARCH_SPACE_TYPE_COMMON; - - for (int i=0;ibwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) { - ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i]; - AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n"); - AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n"); - if (*ss->controlResourceSetId == coreset0->controlResourceSetId && - ss->searchSpaceType->present == target_ss) { - found=1; - break; + AssertFatal(found==1,"Couldn't find a searchspace corresponding to coreset0\n"); + AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n"); + AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n"); + + // for SPS=14 8 MSBs in positions 13 downto 6, + uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | + (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); + + for (int i=0; i>(sps-1-i))&1) { + pdcch_pdu->StartSymbolIndex=i; + break; + } } } - AssertFatal(found==1,"Couldn't find a searchspace corresponding to coreset0\n"); - AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n"); - AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n"); - - // for SPS=14 8 MSBs in positions 13 downto 6, - uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | - (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps)); - - for (int i=0; i>(sps-1-i))&1) { - pdcch_params->first_symbol=i; - break; - } - - // aggregation, find closest to target - AssertFatal(target_aggregation_level == 1 || target_aggregation_level == 2 || target_aggregation_level == 4 || target_aggregation_level == 8 || target_aggregation_level == 16,"illegal target aggregation level %d\n",target_aggregation_level); - AssertFatal(ss->nrofCandidates!=NULL,"ss->nrofCandidates is null\n"); - switch (target_aggregation_level) { - case 1: - if (ss->nrofCandidates->aggregationLevel1 > 0) pdcch_params->aggregation_level = 1; - else if (ss->nrofCandidates->aggregationLevel2 > 0) pdcch_params->aggregation_level = 2; - else if (ss->nrofCandidates->aggregationLevel4 > 0) pdcch_params->aggregation_level = 4; - else if (ss->nrofCandidates->aggregationLevel8 > 0) pdcch_params->aggregation_level = 8; - else if (ss->nrofCandidates->aggregationLevel16 > 0) pdcch_params->aggregation_level = 16; - else AssertFatal(1==0,"Couldn't find an aggregation level, shouldn't happen\n"); - break; - case 2: - if (ss->nrofCandidates->aggregationLevel2 > 0) pdcch_params->aggregation_level = 2; - else if (ss->nrofCandidates->aggregationLevel4 > 0) pdcch_params->aggregation_level = 4; - else if (ss->nrofCandidates->aggregationLevel1 > 0) pdcch_params->aggregation_level = 1; - else if (ss->nrofCandidates->aggregationLevel8 > 0) pdcch_params->aggregation_level = 8; - else if (ss->nrofCandidates->aggregationLevel16 > 0) pdcch_params->aggregation_level = 16; - else AssertFatal(1==0,"Couldn't find an aggregation level, shouldn't happen\n"); - break; - case 4: - if (ss->nrofCandidates->aggregationLevel4 > 0) pdcch_params->aggregation_level = 4; - else if (ss->nrofCandidates->aggregationLevel8 > 0) pdcch_params->aggregation_level = 8; - else if (ss->nrofCandidates->aggregationLevel2 > 0) pdcch_params->aggregation_level = 2; - else if (ss->nrofCandidates->aggregationLevel16 > 0) pdcch_params->aggregation_level = 16; - else if (ss->nrofCandidates->aggregationLevel1 > 0) pdcch_params->aggregation_level = 1; - else AssertFatal(1==0,"Couldn't find an aggregation level, shouldn't happen\n"); - break; - case 8: - if (ss->nrofCandidates->aggregationLevel8 > 0) pdcch_params->aggregation_level = 8; - else if (ss->nrofCandidates->aggregationLevel16 > 0) pdcch_params->aggregation_level = 16; - else if (ss->nrofCandidates->aggregationLevel4 > 0) pdcch_params->aggregation_level = 4; - else if (ss->nrofCandidates->aggregationLevel2 > 0) pdcch_params->aggregation_level = 2; - else if (ss->nrofCandidates->aggregationLevel1 > 0) pdcch_params->aggregation_level = 1; - else AssertFatal(1==0,"Couldn't find an aggregation level, shouldn't happen\n"); - break; - case 16: - if (ss->nrofCandidates->aggregationLevel16 > 0) pdcch_params->aggregation_level = 16; - else if (ss->nrofCandidates->aggregationLevel8 > 0) pdcch_params->aggregation_level = 8; - else if (ss->nrofCandidates->aggregationLevel4 > 0) pdcch_params->aggregation_level = 4; - else if (ss->nrofCandidates->aggregationLevel2 > 0) pdcch_params->aggregation_level = 2; - else if (ss->nrofCandidates->aggregationLevel1 > 0) pdcch_params->aggregation_level = 1; - else AssertFatal(1==0,"Couldn't find an aggregation level, shouldn't happen\n"); - break; + else { // this is for InitialBWP + AssertFatal(1==0,"Fill in InitialBWP PDCCH configuration\n"); } - - - pdcch_params->n_RB_BWP = N_RB; - pdcch_params->cce_index = cce_index; } -int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space, - nfapi_nr_coreset_t coreset, - uint16_t frame, - uint16_t slot, - nfapi_nr_config_request_t cfg) { +void fill_dci_pdu_rel15(nfapi_nr_dl_config_pdcch_pdu_rel15_t *pdcch_pdu_rel15, + dci_pdu_rel15_t *dci_pdu_rel15, + int *dci_formats, + int *rnti_types + ) { + + uint16_t N_RB = pdcch_pdu_rel15->BWPSize; + uint8_t fsize=0, pos=0, cand_idx=0; - AssertFatal(search_space.coreset_id==coreset.coreset_id, "Invalid association of coreset(%d) and search space(%d)\n", - search_space.search_space_id, coreset.coreset_id); + for (int d=0;dnumDlDci;d++) { - uint8_t is_dci_opportunity=0; - uint16_t Ks=search_space.slot_monitoring_periodicity; - uint16_t Os=search_space.slot_monitoring_offset; - uint8_t Ts=search_space.duration; + uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->Payload[d]; + AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); + /* + n_shift = (dci_alloc->pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)? + cfg->sch_config.physical_cell_id.value : dci_alloc->pdcch_params.shift_index; + nr_fill_cce_list(dci_alloc, n_shift, cand_idx); + */ + int dci_size = pdcch_pdu_rel15->PayloadSizeBits[d]; + + /// Payload generation + switch(dci_formats[d]) { + case NR_DL_DCI_FORMAT_1_0: + switch(rnti_types[d]) { + case NR_RNTI_RA: + // Freq domain assignment + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + pos=fsize; + *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment&((1< %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,N_RB,dci_size-pos,*dci_pdu); +#endif + // Time domain assignment + pos+=4; + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos)); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu); +#endif + // VRB to PRB mapping + + pos++; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_size-pos); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu); +#endif + // MCS + pos+=5; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu); +#endif + // TB scaling + pos+=2; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling&0x3)<<(dci_size-pos); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu); +#endif + break; + + case NR_RNTI_C: + + // indicating a DL DCI format 1bit + pos++; + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,N_RB,dci_size-pos,*dci_pdu); +#endif + + // Freq domain assignment (275rb >> fsize = 16) + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + pos+=fsize; + *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1< %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,dci_size-pos,*dci_pdu); +#endif + + uint16_t is_ra = 1; + for (int i=0; ifrequency_domain_assignment>>i)&1)) { + is_ra = 0; + break; + } + if (is_ra) //fsize are all 1 38.212 p86 + { + // ra_preamble_index 6 bits + pos+=6; + *dci_pdu |= ((dci_pdu_rel15->ra_preamble_index&0x3f)<<(dci_size-pos)); + + // UL/SUL indicator 1 bit + pos++; + *dci_pdu |= (dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos); + + // SS/PBCH index 6 bits + pos+=6; + *dci_pdu |= ((dci_pdu_rel15->ss_pbch_index&0x3f)<<(dci_size-pos)); + + // prach_mask_index 4 bits + pos+=4; + *dci_pdu |= ((dci_pdu_rel15->prach_mask_index&0xf)<<(dci_size-pos)); + + } //end if + + else { + + // Time domain assignment 4bit + + pos+=4; + *dci_pdu |= ((dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos)); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,4,dci_size-pos,*dci_pdu); +#endif + + // VRB to PRB mapping 1bit + pos++; + *dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu); +#endif + + // MCS 5bit //bit over 32, so dci_pdu ++ + pos+=5; + *dci_pdu |= (dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,5,dci_size-pos,*dci_pdu); +#endif + + // New data indicator 1bit + pos++; + *dci_pdu |= (dci_pdu_rel15->ndi&1)<<(dci_size-pos); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu); +#endif + + // Redundancy version 2bit + pos+=2; + *dci_pdu |= (dci_pdu_rel15->rv&0x3)<<(dci_size-pos); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu); +#endif + + // HARQ process number 4bit + pos+=4; + *dci_pdu |= ((dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos)); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu); +#endif + + // Downlink assignment index 2bit + pos+=2; + *dci_pdu |= ((dci_pdu_rel15->dai&3)<<(dci_size-pos)); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu); +#endif + + // TPC command for scheduled PUCCH 2bit + pos+=2; + *dci_pdu |= ((dci_pdu_rel15->tpc&3)<<(dci_size-pos)); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu); +#endif + + // PUCCH resource indicator 3bit + pos+=3; + *dci_pdu |= ((dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos)); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator,3,dci_size-pos,*dci_pdu); +#endif + + // PDSCH-to-HARQ_feedback timing indicator 3bit + pos+=3; + *dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_size-pos)); +#ifdef DEBUG_FILL_DCI + LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator,3,dci_size-pos,*dci_pdu); +#endif + + } //end else + break; + + case NR_RNTI_P: + + // Short Messages Indicator – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_size-pos++); + // Short Messages – 8 bits + for (int i=0; i<8; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages>>(7-i))&1)<<(dci_size-pos++); + // Freq domain assignment 0-16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // VRB to PRB mapping 1 bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + // MCS 5 bit + for (int i=0; i<5; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + + // TB scaling 2 bit + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_size-pos++); + + + break; + + case NR_RNTI_SI: + // Freq domain assignment 0-16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // VRB to PRB mapping 1 bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + // MCS 5bit //bit over 32, so dci_pdu ++ + for (int i=0; i<5; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + + break; + + case NR_RNTI_TC: + // indicating a DL DCI format 1bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); + // Freq domain assignment 0-16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4 bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // VRB to PRB mapping 1 bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); + // MCS 5bit //bit over 32, so dci_pdu ++ + for (int i=0; i<5; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + // New data indicator 1bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + // HARQ process number 4bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); + + // Downlink assignment index – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->dai>>(1-i))&1)<<(dci_size-pos++); + + // TPC command for scheduled PUCCH – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); + + + // LOG_D(MAC, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n", + // dci_pdu[0], dci_pdu[1], dci_pdu[2], dci_pdu[3]); + + + // PDSCH-to-HARQ_feedback timing indicator – 3 bits + for (int i=0; i<3; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_size-pos++); + + break; + } + break; + + case NR_UL_DCI_FORMAT_0_0: + switch(rnti_types[d]) + { + case NR_RNTI_C: + // indicating a DL DCI format 1bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); + // Freq domain assignment max 16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // Frequency hopping flag – 1 bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++); + // MCS 5 bit + for (int i=0; i<5; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + // New data indicator 1bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + // HARQ process number 4bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); + + // TPC command for scheduled PUSCH – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); + + // Padding bits + for(int a = pos;a<32;a++) + *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding&1)<<(dci_size-pos++); + + // UL/SUL indicator – 1 bit + /* commented for now (RK): need to get this from BWP descriptor + if (cfg->pucch_config.pucch_GroupHopping.value) + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++); + */ + break; + + case NFAPI_NR_RNTI_TC: + + // indicating a DL DCI format 1bit + *dci_pdu |= (dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); + // Freq domain assignment max 16 bit + fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); + for (int i=0; ifrequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); + // Time domain assignment 4bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); + // Frequency hopping flag – 1 bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++); + // MCS 5 bit + for (int i=0; i<5; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); + // New data indicator 1bit + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); + // Redundancy version 2bit + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); + // HARQ process number 4bit + for (int i=0; i<4; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); + + // TPC command for scheduled PUSCH – 2 bits + for (int i=0; i<2; i++) + *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); + + // Padding bits + for(int a = pos;a<32;a++) + *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding&1)<<(dci_size-pos++); + + // UL/SUL indicator – 1 bit + /* + commented for now (RK): need to get this information from BWP descriptor + if (cfg->pucch_config.pucch_GroupHopping.value) + *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++); + */ + break; + + } + break; + } + } +} - if (((frame*get_spf(&cfg) + slot - Os)%Ks)dlsch_pdu_rel15; - uint8_t rnti_type = params_rel15.rnti_type; - uint16_t N_PRB_oh = ((rnti_type==NFAPI_NR_RNTI_SI)||(rnti_type==NFAPI_NR_RNTI_RA)||(rnti_type==NFAPI_NR_RNTI_P))? 0 : \ - (x_overhead); + uint16_t N_PRB_oh = x_overhead; uint8_t N_PRB_DMRS = (dlsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1)?6:4; //This only works for antenna port 1000 uint8_t N_sh_symb = dlsch_rel15->NrOfSymbols; uint8_t Imcs = dlsch_rel15->mcsIndex[0]; diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 5ca35bd382..552af9a4c5 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -116,12 +116,6 @@ typedef struct { boolean_t active[MAX_MOBILES_PER_GNB]; rnti_t rnti[MAX_MOBILES_PER_GNB]; NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB]; - /// NFAPI coreset structure - nfapi_nr_coreset_t coreset[MAX_MOBILES_PER_GNB][NFAPI_NR_MAX_NB_CORESETS]; - /// NFAPI search space structure - nfapi_nr_search_space_t search_space[MAX_MOBILES_PER_GNB][NFAPI_NR_MAX_NB_SEARCH_SPACES]; - - } NR_UE_list_t; /*! \brief top level eNB MAC structure */ @@ -193,4 +187,93 @@ typedef struct gNB_MAC_INST_s { time_stats_t schedule_pch; } gNB_MAC_INST; +typedef struct { + + +uint8_t format_indicator; //1 bit +uint16_t frequency_domain_assignment; //up to 16 bits +uint8_t time_domain_assignment; // 4 bits +uint8_t frequency_hopping_flag; //1 bit + +uint8_t ra_preamble_index; //6 bits +uint8_t ss_pbch_index; //6 bits +uint8_t prach_mask_index; //4 bits + +uint8_t vrb_to_prb_mapping; //0 or 1 bit +uint8_t mcs; //5 bits +uint8_t ndi; //1 bit +uint8_t rv; //2 bits +uint8_t harq_pid; //4 bits +uint8_t dai; //0, 2 or 4 bits +uint8_t dai1; //1 or 2 bits +uint8_t dai2; //0 or 2 bits +uint8_t tpc; //2 bits +uint8_t pucch_resource_indicator; //3 bits +uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits + +uint8_t short_messages_indicator; //2 bits +uint8_t short_messages; //8 bits +uint8_t tb_scaling; //2 bits + +uint8_t carrier_indicator; //0 or 3 bits +uint8_t bwp_indicator; //0, 1 or 2 bits +uint8_t prb_bundling_size_indicator; //0 or 1 bits +uint8_t rate_matching_indicator; //0, 1 or 2 bits +uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits +uint8_t transmission_configuration_indication; //0 or 3 bits +uint8_t srs_request; //2 bits +uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits +uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit +uint8_t dmrs_sequence_initialization; //0 or 1 bit + +uint8_t srs_resource_indicator; +uint8_t precoding_information; +uint8_t csi_request; +uint8_t ptrs_dmrs_association; +uint8_t beta_offset_indicator; //0 or 2 bits + +uint8_t slot_format_indicator_count; +uint8_t *slot_format_indicators; + +uint8_t pre_emption_indication_count; +uint16_t *pre_emption_indications; //14 bit + +uint8_t block_number_count; +uint8_t *block_numbers; + +uint8_t ul_sul_indicator; //0 or 1 bit +uint8_t antenna_ports; + +uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits +uint16_t padding; + +} dci_pdu_rel15_t; + +typedef enum { + NR_DL_DCI_FORMAT_1_0 = 0, + NR_DL_DCI_FORMAT_1_1, + NR_DL_DCI_FORMAT_2_0, + NR_DL_DCI_FORMAT_2_1, + NR_DL_DCI_FORMAT_2_2, + NR_DL_DCI_FORMAT_2_3, + NR_UL_DCI_FORMAT_0_0, + NR_UL_DCI_FORMAT_0_1 +} nr_dci_format_t; + +typedef enum { + NR_RNTI_new = 0, + NR_RNTI_C, + NR_RNTI_RA, + NR_RNTI_P, + NR_RNTI_CS, + NR_RNTI_TC, + NR_RNTI_SP_CSI, + NR_RNTI_SI, + NR_RNTI_SFI, + NR_RNTI_INT, + NR_RNTI_TPC_PUSCH, + NR_RNTI_TPC_PUCCH, + NR_RNTI_TPC_SRS +} nr_rnti_type_t; + #endif /*__LAYER2_NR_MAC_GNB_H__ */