Move nr_bwp_switch and schedule_nr_bwp_switch functions to gNB_scheduler_primitives.c
This commit is contained in:
rmagueta
@@ -1001,72 +1001,6 @@ nr_pp_impl_dl nr_init_fr1_dlsch_preprocessor(module_id_t module_id, int CC_id)
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return nr_fr1_dlsch_preprocessor;
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return nr_fr1_dlsch_preprocessor;
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}
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}
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void nr_bwp_switch(module_id_t module_id,
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frame_t frame,
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sub_frame_t slot,
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int UE_id,
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int bwp_id) {
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NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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switch(sched_ctrl->bwp_switch_info.bwp_switch_state) {
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case BWP_SWITCH_TO_START:
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LOG_W(NR_MAC,"(%d.%d) [UE_id %d] Schedule BWP switch from bwp_id %ld to %d\n",
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frame, slot, UE_id, UE_info->UE_sched_ctrl[UE_id].active_bwp->bwp_Id, bwp_id);
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sched_ctrl->bwp_switch_info.bwp_switch_state = BWP_SWITCH_RUNNING;
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sched_ctrl->bwp_switch_info.bwp_switch_slot = slot;
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nr_mac_rrc_bwp_switch_req(module_id, frame, slot, UE_info->rnti[UE_id], bwp_id);
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break;
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case BWP_SWITCH_RUNNING:
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// The BWP switching takes at least 10+6 ms (3GPP TS 38.331 Section 12)
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// gNB needs time to schedule and send RRCReconfiguration message
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// Therefore, we wait for the same slot in next frame (10 ms) before update bwp_id in the gNB
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if (sched_ctrl->bwp_switch_info.bwp_switch_slot == slot) {
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const NR_ServingCellConfig_t *servingCellConfig = UE_info->CellGroup[UE_id] ? UE_info->CellGroup[UE_id]->spCellConfig->spCellConfigDedicated : NULL;
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const struct NR_ServingCellConfig__downlinkBWP_ToAddModList *bwpList = servingCellConfig ? servingCellConfig->downlinkBWP_ToAddModList : NULL;
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const int bwp_id = servingCellConfig && servingCellConfig->firstActiveDownlinkBWP_Id ?
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*servingCellConfig->firstActiveDownlinkBWP_Id : 0;
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sched_ctrl->active_bwp = bwpList && bwp_id > 0 ? bwpList->list.array[bwp_id - 1] : NULL;
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const struct NR_UplinkConfig__uplinkBWP_ToAddModList *ubwpList = servingCellConfig ? servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList : NULL;
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const int ubwp_id = servingCellConfig && servingCellConfig->uplinkConfig && servingCellConfig->uplinkConfig->firstActiveUplinkBWP_Id ?
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*servingCellConfig->uplinkConfig->firstActiveUplinkBWP_Id : 0;
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sched_ctrl->active_ubwp = ubwpList && ubwp_id > 0 ? ubwpList->list.array[ubwp_id - 1] : NULL;
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sched_ctrl->bwp_switch_info.bwp_switch_state = BWP_SWITCH_INACTIVE;
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}
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break;
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case BWP_SWITCH_INACTIVE:
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break;
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default:
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AssertFatal(1==0,"Invalid bwp switch state\n");
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break;
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}
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}
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void schedule_nr_bwp_switch(module_id_t module_id,
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frame_t frame,
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sub_frame_t slot) {
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NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
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const NR_list_t *UE_list = &UE_info->list;
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// TODO: Implementation of a algorithm to perform:
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// - the BWP switch trigger: sched_ctrl->bwp_switch_info.bwp_switch_state = BWP_SWITCH_TO_START
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// - the BWP selection: sched_ctrl->bwp_switch_info.next_bwp = bwp_id
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for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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if(sched_ctrl->bwp_switch_info.bwp_switch_state > BWP_SWITCH_INACTIVE) {
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nr_bwp_switch(module_id, frame, slot, UE_id, sched_ctrl->bwp_switch_info.next_bwp);
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}
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}
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}
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void nr_schedule_ue_spec(module_id_t module_id,
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void nr_schedule_ue_spec(module_id_t module_id,
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frame_t frame,
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frame_t frame,
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sub_frame_t slot) {
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sub_frame_t slot) {
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@@ -2704,6 +2704,71 @@ void nr_csirs_scheduling(int Mod_idP,
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}
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}
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}
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}
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void nr_bwp_switch(module_id_t module_id,
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frame_t frame,
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sub_frame_t slot,
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int UE_id,
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int bwp_id) {
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NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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switch(sched_ctrl->bwp_switch_info.bwp_switch_state) {
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case BWP_SWITCH_TO_START:
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LOG_W(NR_MAC,"(%d.%d) [UE_id %d] Schedule BWP switch from bwp_id %ld to %d\n",
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frame, slot, UE_id, UE_info->UE_sched_ctrl[UE_id].active_bwp->bwp_Id, bwp_id);
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sched_ctrl->bwp_switch_info.bwp_switch_state = BWP_SWITCH_RUNNING;
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sched_ctrl->bwp_switch_info.bwp_switch_slot = slot;
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nr_mac_rrc_bwp_switch_req(module_id, frame, slot, UE_info->rnti[UE_id], bwp_id);
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break;
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case BWP_SWITCH_RUNNING:
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// The BWP switching takes at least 10+6 ms (3GPP TS 38.331 Section 12)
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// gNB needs time to schedule and send RRCReconfiguration message
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// Therefore, we wait for the same slot in next frame (10 ms) before update bwp_id in the gNB
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if (sched_ctrl->bwp_switch_info.bwp_switch_slot == slot) {
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const NR_ServingCellConfig_t *servingCellConfig = UE_info->CellGroup[UE_id] ? UE_info->CellGroup[UE_id]->spCellConfig->spCellConfigDedicated : NULL;
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const struct NR_ServingCellConfig__downlinkBWP_ToAddModList *bwpList = servingCellConfig ? servingCellConfig->downlinkBWP_ToAddModList : NULL;
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const int bwp_id = servingCellConfig && servingCellConfig->firstActiveDownlinkBWP_Id ?
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*servingCellConfig->firstActiveDownlinkBWP_Id : 0;
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sched_ctrl->active_bwp = bwpList && bwp_id > 0 ? bwpList->list.array[bwp_id - 1] : NULL;
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const struct NR_UplinkConfig__uplinkBWP_ToAddModList *ubwpList = servingCellConfig ? servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList : NULL;
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const int ubwp_id = servingCellConfig && servingCellConfig->uplinkConfig && servingCellConfig->uplinkConfig->firstActiveUplinkBWP_Id ?
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*servingCellConfig->uplinkConfig->firstActiveUplinkBWP_Id : 0;
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sched_ctrl->active_ubwp = ubwpList && ubwp_id > 0 ? ubwpList->list.array[ubwp_id - 1] : NULL;
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sched_ctrl->bwp_switch_info.bwp_switch_state = BWP_SWITCH_INACTIVE;
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}
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break;
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case BWP_SWITCH_INACTIVE:
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break;
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default:
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AssertFatal(1==0,"Invalid bwp switch state\n");
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break;
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}
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}
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void schedule_nr_bwp_switch(module_id_t module_id,
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frame_t frame,
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sub_frame_t slot) {
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NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
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const NR_list_t *UE_list = &UE_info->list;
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// TODO: Implementation of a algorithm to perform:
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// - the BWP switch trigger: sched_ctrl->bwp_switch_info.bwp_switch_state = BWP_SWITCH_TO_START
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// - the BWP selection: sched_ctrl->bwp_switch_info.next_bwp = bwp_id
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for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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if(sched_ctrl->bwp_switch_info.bwp_switch_state > BWP_SWITCH_INACTIVE) {
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nr_bwp_switch(module_id, frame, slot, UE_id, sched_ctrl->bwp_switch_info.next_bwp);
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}
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}
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}
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/*void fill_nfapi_coresets_and_searchspaces(NR_CellGroupConfig_t *cg,
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/*void fill_nfapi_coresets_and_searchspaces(NR_CellGroupConfig_t *cg,
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nfapi_nr_coreset_t *coreset,
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nfapi_nr_coreset_t *coreset,
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