Recalculate PUSCH saved params struct in Pre-processor
This commit is contained in:
@@ -407,7 +407,6 @@ void nr_ul_preprocessor_phytest(module_id_t module_id,
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}
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}
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}
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}
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sched_ctrl->sched_pusch.time_domain_allocation = tda;
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sched_ctrl->sched_pusch.slot = sched_slot;
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sched_ctrl->sched_pusch.slot = sched_slot;
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sched_ctrl->sched_pusch.frame = sched_frame;
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sched_ctrl->sched_pusch.frame = sched_frame;
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@@ -435,6 +434,24 @@ void nr_ul_preprocessor_phytest(module_id_t module_id,
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}
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}
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UE_info->num_pdcch_cand[UE_id][cid]++;
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UE_info->num_pdcch_cand[UE_id][cid]++;
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sched_ctrl->sched_pusch.time_domain_allocation = tda;
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const long f = sched_ctrl->search_space->searchSpaceType->choice.ue_Specific->dci_Formats;
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const int dci_format = f ? NR_UL_DCI_FORMAT_0_1 : NR_UL_DCI_FORMAT_0_0;
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const uint8_t num_dmrs_cdm_grps_no_data = 1;
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/* we want to avoid a lengthy deduction of DMRS and other parameters in
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* every TTI if we can save it, so check whether dci_format, TDA, or
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* num_dmrs_cdm_grps_no_data has changed and only then recompute */
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NR_sched_pusch_save_t *ps = &sched_ctrl->pusch_save;
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if (ps->time_domain_allocation != tda
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|| ps->dci_format != dci_format
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|| ps->num_dmrs_cdm_grps_no_data != num_dmrs_cdm_grps_no_data)
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nr_save_pusch_fields(scc,
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sched_ctrl->active_ubwp,
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dci_format,
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tda,
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num_dmrs_cdm_grps_no_data,
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ps);
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sched_ctrl->sched_pusch.mcs = 9;
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sched_ctrl->sched_pusch.mcs = 9;
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sched_ctrl->sched_pusch.rbStart = rbStart;
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sched_ctrl->sched_pusch.rbStart = rbStart;
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sched_ctrl->sched_pusch.rbSize = rbSize;
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sched_ctrl->sched_pusch.rbSize = rbSize;
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@@ -1865,6 +1865,8 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
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UE_info->UE_sched_ctrl[UE_id].ta_update = 31;
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UE_info->UE_sched_ctrl[UE_id].ta_update = 31;
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UE_info->UE_sched_ctrl[UE_id].ta_apply = false;
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UE_info->UE_sched_ctrl[UE_id].ta_apply = false;
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UE_info->UE_sched_ctrl[UE_id].ul_rssi = 0;
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UE_info->UE_sched_ctrl[UE_id].ul_rssi = 0;
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/* set illegal time domain allocation to force recomputation of all fields */
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UE_info->UE_sched_ctrl[UE_id].pusch_save.time_domain_allocation = -1;
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UE_info->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch **)malloc(num_slots_ul*sizeof(NR_sched_pucch *));
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UE_info->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch **)malloc(num_slots_ul*sizeof(NR_sched_pucch *));
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for (int s=0; s<num_slots_ul;s++)
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for (int s=0; s<num_slots_ul;s++)
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UE_info->UE_sched_ctrl[UE_id].sched_pucch[s] = (NR_sched_pucch *)malloc(2*sizeof(NR_sched_pucch));
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UE_info->UE_sched_ctrl[UE_id].sched_pucch[s] = (NR_sched_pucch *)malloc(2*sizeof(NR_sched_pucch));
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@@ -506,7 +506,6 @@ void nr_simple_ulsch_preprocessor(module_id_t module_id,
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while (rbStart + rbSize < bwpSize && !vrb_map_UL[rbStart+rbSize])
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while (rbStart + rbSize < bwpSize && !vrb_map_UL[rbStart+rbSize])
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rbSize++;
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rbSize++;
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sched_ctrl->sched_pusch.time_domain_allocation = tda;
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sched_ctrl->sched_pusch.slot = sched_slot;
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sched_ctrl->sched_pusch.slot = sched_slot;
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sched_ctrl->sched_pusch.frame = sched_frame;
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sched_ctrl->sched_pusch.frame = sched_frame;
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@@ -534,6 +533,24 @@ void nr_simple_ulsch_preprocessor(module_id_t module_id,
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}
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}
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UE_info->num_pdcch_cand[UE_id][cid]++;
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UE_info->num_pdcch_cand[UE_id][cid]++;
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sched_ctrl->sched_pusch.time_domain_allocation = tda;
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const long f = sched_ctrl->search_space->searchSpaceType->choice.ue_Specific->dci_Formats;
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const int dci_format = f ? NR_UL_DCI_FORMAT_0_1 : NR_UL_DCI_FORMAT_0_0;
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const uint8_t num_dmrs_cdm_grps_no_data = 1;
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/* we want to avoid a lengthy deduction of DMRS and other parameters in
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* every TTI if we can save it, so check whether dci_format, TDA, or
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* num_dmrs_cdm_grps_no_data has changed and only then recompute */
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NR_sched_pusch_save_t *ps = &sched_ctrl->pusch_save;
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if (ps->time_domain_allocation != tda
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|| ps->dci_format != dci_format
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|| ps->num_dmrs_cdm_grps_no_data != num_dmrs_cdm_grps_no_data)
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nr_save_pusch_fields(scc,
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sched_ctrl->active_ubwp,
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dci_format,
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tda,
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num_dmrs_cdm_grps_no_data,
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ps);
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sched_ctrl->sched_pusch.mcs = 9;
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sched_ctrl->sched_pusch.mcs = 9;
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sched_ctrl->sched_pusch.rbStart = rbStart;
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sched_ctrl->sched_pusch.rbStart = rbStart;
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sched_ctrl->sched_pusch.rbSize = rbSize;
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sched_ctrl->sched_pusch.rbSize = rbSize;
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@@ -569,34 +586,27 @@ void nr_schedule_ulsch(module_id_t module_id,
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cur_harq->state = ACTIVE_SCHED;
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cur_harq->state = ACTIVE_SCHED;
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cur_harq->last_tx_slot = sched_pusch->slot;
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cur_harq->last_tx_slot = sched_pusch->slot;
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const long f = sched_ctrl->search_space->searchSpaceType->choice.ue_Specific->dci_Formats;
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int dci_formats[2] = { f ? NR_UL_DCI_FORMAT_0_1 : NR_UL_DCI_FORMAT_0_0 , 0 };
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int rnti_types[2] = { NR_RNTI_C, 0 };
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int rnti_types[2] = { NR_RNTI_C, 0 };
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const int tda = sched_pusch->time_domain_allocation;
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/* pre-computed PUSCH values that only change if time domain allocation,
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const uint8_t num_dmrs_cdm_grps_no_data = 1;
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* DCI format, or DMRS parameters change. Updated in the preprocessor
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NR_sched_pusch_save_t ps;
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* through nr_save_pusch_fields() */
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nr_save_pusch_fields(scc,
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NR_sched_pusch_save_t *ps = &sched_ctrl->pusch_save;
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sched_ctrl->active_ubwp,
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dci_formats[0],
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tda,
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num_dmrs_cdm_grps_no_data,
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&ps);
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/* Calculate TBS from MCS */
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/* Calculate TBS from MCS */
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const uint8_t mcs = sched_pusch->mcs;
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const uint8_t mcs = sched_pusch->mcs;
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uint16_t R = nr_get_code_rate_ul(mcs, ps.mcs_table);
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uint16_t R = nr_get_code_rate_ul(mcs, ps->mcs_table);
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uint8_t Qm = nr_get_Qm_ul(mcs, ps.mcs_table);
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uint8_t Qm = nr_get_Qm_ul(mcs, ps->mcs_table);
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if (ps.pusch_Config->tp_pi2BPSK
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if (ps->pusch_Config->tp_pi2BPSK
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&& ((ps.mcs_table == 3 && mcs < 2) || (ps.mcs_table == 4 && mcs < 6))) {
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&& ((ps->mcs_table == 3 && mcs < 2) || (ps->mcs_table == 4 && mcs < 6))) {
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R >>= 1;
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R >>= 1;
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Qm <<= 1;
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Qm <<= 1;
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}
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}
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const uint32_t tb_size = nr_compute_tbs(Qm,
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const uint32_t tb_size = nr_compute_tbs(Qm,
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R,
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R,
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sched_pusch->rbSize,
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sched_pusch->rbSize,
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ps.nrOfSymbols,
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ps->nrOfSymbols,
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ps.N_PRB_DMRS * ps.num_dmrs_symb,
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ps->N_PRB_DMRS * ps->num_dmrs_symb,
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0, // nb_rb_oh
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0, // nb_rb_oh
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0,
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0,
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1 /* NrOfLayers */) >> 3;
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1 /* NrOfLayers */) >> 3;
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@@ -639,23 +649,23 @@ void nr_schedule_ulsch(module_id_t module_id,
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pusch_pdu->target_code_rate = R;
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pusch_pdu->target_code_rate = R;
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pusch_pdu->qam_mod_order = Qm;
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pusch_pdu->qam_mod_order = Qm;
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pusch_pdu->mcs_index = mcs;
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pusch_pdu->mcs_index = mcs;
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pusch_pdu->mcs_table = ps.mcs_table;
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pusch_pdu->mcs_table = ps->mcs_table;
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pusch_pdu->transform_precoding = ps.transform_precoding;
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pusch_pdu->transform_precoding = ps->transform_precoding;
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if (ps.pusch_Config->dataScramblingIdentityPUSCH)
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if (ps->pusch_Config->dataScramblingIdentityPUSCH)
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pusch_pdu->data_scrambling_id = *ps.pusch_Config->dataScramblingIdentityPUSCH;
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pusch_pdu->data_scrambling_id = *ps->pusch_Config->dataScramblingIdentityPUSCH;
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else
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else
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pusch_pdu->data_scrambling_id = *scc->physCellId;
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pusch_pdu->data_scrambling_id = *scc->physCellId;
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pusch_pdu->nrOfLayers = 1;
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pusch_pdu->nrOfLayers = 1;
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/* FAPI: DMRS */
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/* FAPI: DMRS */
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pusch_pdu->ul_dmrs_symb_pos = ps.ul_dmrs_symb_pos;
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pusch_pdu->ul_dmrs_symb_pos = ps->ul_dmrs_symb_pos;
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pusch_pdu->dmrs_config_type = ps.dmrs_config_type;
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pusch_pdu->dmrs_config_type = ps->dmrs_config_type;
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if (pusch_pdu->transform_precoding) { // transform precoding disabled
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if (pusch_pdu->transform_precoding) { // transform precoding disabled
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long *scramblingid;
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long *scramblingid;
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if (pusch_pdu->scid == 0)
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if (pusch_pdu->scid == 0)
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scramblingid = ps.NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0;
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scramblingid = ps->NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0;
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else
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else
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scramblingid = ps.NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1;
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scramblingid = ps->NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1;
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if (scramblingid == NULL)
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if (scramblingid == NULL)
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pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId;
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pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId;
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else
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else
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@@ -663,30 +673,30 @@ void nr_schedule_ulsch(module_id_t module_id,
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}
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}
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else {
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else {
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pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId;
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pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId;
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if (ps.NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity != NULL)
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if (ps->NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity != NULL)
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pusch_pdu->pusch_identity = *ps.NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity;
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pusch_pdu->pusch_identity = *ps->NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity;
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else
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else
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pusch_pdu->pusch_identity = *scc->physCellId;
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pusch_pdu->pusch_identity = *scc->physCellId;
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}
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}
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pusch_pdu->scid = 0; // DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]
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pusch_pdu->scid = 0; // DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]
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pusch_pdu->num_dmrs_cdm_grps_no_data = ps.num_dmrs_cdm_grps_no_data;
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pusch_pdu->num_dmrs_cdm_grps_no_data = ps->num_dmrs_cdm_grps_no_data;
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pusch_pdu->dmrs_ports = 1;
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pusch_pdu->dmrs_ports = 1;
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/* FAPI: Pusch Allocation in frequency domain */
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/* FAPI: Pusch Allocation in frequency domain */
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AssertFatal(ps.pusch_Config->resourceAllocation == NR_PUSCH_Config__resourceAllocation_resourceAllocationType1,
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AssertFatal(ps->pusch_Config->resourceAllocation == NR_PUSCH_Config__resourceAllocation_resourceAllocationType1,
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"Only frequency resource allocation type 1 is currently supported\n");
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"Only frequency resource allocation type 1 is currently supported\n");
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pusch_pdu->resource_alloc = 1; //type 1
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pusch_pdu->resource_alloc = 1; //type 1
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pusch_pdu->rb_start = sched_pusch->rbStart;
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pusch_pdu->rb_start = sched_pusch->rbStart;
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pusch_pdu->rb_size = sched_pusch->rbSize;
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pusch_pdu->rb_size = sched_pusch->rbSize;
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pusch_pdu->vrb_to_prb_mapping = 0;
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pusch_pdu->vrb_to_prb_mapping = 0;
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if (ps.pusch_Config->frequencyHopping==NULL)
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if (ps->pusch_Config->frequencyHopping==NULL)
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pusch_pdu->frequency_hopping = 0;
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pusch_pdu->frequency_hopping = 0;
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else
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else
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pusch_pdu->frequency_hopping = 1;
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pusch_pdu->frequency_hopping = 1;
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/* FAPI: Resource Allocation in time domain */
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/* FAPI: Resource Allocation in time domain */
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pusch_pdu->start_symbol_index = ps.startSymbolIndex;
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pusch_pdu->start_symbol_index = ps->startSymbolIndex;
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pusch_pdu->nr_of_symbols = ps.nrOfSymbols;
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pusch_pdu->nr_of_symbols = ps->nrOfSymbols;
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/* PUSCH PDU */
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/* PUSCH PDU */
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pusch_pdu->pusch_data.rv_index = nr_rv_round_map[cur_harq->round];
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pusch_pdu->pusch_data.rv_index = nr_rv_round_map[cur_harq->round];
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@@ -696,7 +706,7 @@ void nr_schedule_ulsch(module_id_t module_id,
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pusch_pdu->pusch_data.num_cb = 0; //CBG not supported
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pusch_pdu->pusch_data.num_cb = 0; //CBG not supported
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/* PUSCH PTRS */
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/* PUSCH PTRS */
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if (ps.NR_DMRS_UplinkConfig->phaseTrackingRS != NULL) {
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if (ps->NR_DMRS_UplinkConfig->phaseTrackingRS != NULL) {
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// TODO to be fixed from RRC config
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// TODO to be fixed from RRC config
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uint8_t ptrs_mcs1 = 2; // higher layer parameter in PTRS-UplinkConfig
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uint8_t ptrs_mcs1 = 2; // higher layer parameter in PTRS-UplinkConfig
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uint8_t ptrs_mcs2 = 4; // higher layer parameter in PTRS-UplinkConfig
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uint8_t ptrs_mcs2 = 4; // higher layer parameter in PTRS-UplinkConfig
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@@ -740,12 +750,16 @@ void nr_schedule_ulsch(module_id_t module_id,
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memset(dci_pdu_rel15, 0, sizeof(dci_pdu_rel15));
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memset(dci_pdu_rel15, 0, sizeof(dci_pdu_rel15));
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NR_CellGroupConfig_t *secondaryCellGroup = UE_info->secondaryCellGroup[UE_id];
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NR_CellGroupConfig_t *secondaryCellGroup = UE_info->secondaryCellGroup[UE_id];
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const int n_ubwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count;
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const int n_ubwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count;
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// NOTE: below functions assume that dci_formats is an array corresponding
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// to all UL DCIs in the PDCCH, but for us it is a simple int. So before
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// having multiple UEs, the below need to be changed (IMO the functions
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// should fill for one DCI only and not handle all of them).
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config_uldci(sched_ctrl->active_ubwp,
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config_uldci(sched_ctrl->active_ubwp,
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pusch_pdu,
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pusch_pdu,
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pdcch_pdu_rel15,
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pdcch_pdu_rel15,
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&dci_pdu_rel15[0],
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&dci_pdu_rel15[0],
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dci_formats,
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&ps->dci_format,
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tda,
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ps->time_domain_allocation,
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UE_info->UE_sched_ctrl[UE_id].tpc0,
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UE_info->UE_sched_ctrl[UE_id].tpc0,
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n_ubwp,
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n_ubwp,
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sched_ctrl->active_bwp->bwp_Id);
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sched_ctrl->active_bwp->bwp_Id);
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@@ -753,7 +767,7 @@ void nr_schedule_ulsch(module_id_t module_id,
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secondaryCellGroup,
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secondaryCellGroup,
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pdcch_pdu_rel15,
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pdcch_pdu_rel15,
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dci_pdu_rel15,
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dci_pdu_rel15,
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dci_formats,
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&ps->dci_format,
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rnti_types,
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rnti_types,
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pusch_pdu->bwp_size,
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pusch_pdu->bwp_size,
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sched_ctrl->active_bwp->bwp_Id);
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sched_ctrl->active_bwp->bwp_Id);
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@@ -386,6 +386,7 @@ typedef struct {
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/// selected PUCCH index, if scheduled
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/// selected PUCCH index, if scheduled
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int pucch_sched_idx;
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int pucch_sched_idx;
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int pucch_occ_idx;
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int pucch_occ_idx;
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NR_sched_pusch_save_t pusch_save;
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NR_sched_pusch_t sched_pusch;
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NR_sched_pusch_t sched_pusch;
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/// CCE index and aggregation, should be coherent with cce_list
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/// CCE index and aggregation, should be coherent with cce_list
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