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laurent
2019-03-21 14:15:26 +01:00
parent d13644773d
commit d9c68d8b30
21 changed files with 2502 additions and 91 deletions
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executables/nr-ue.c
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/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.0 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file lte-ue.c
* \brief threads and support functions for real-time LTE UE target
* \author R. Knopp, F. Kaltenberger, Navid Nikaein
* \date 2015
* \version 0.1
* \company Eurecom
* \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr, navid.nikaein@eurecom.fr
* \note
* \warning
*/
#include "executables/nr-uesoftmodem.h"
#include "LAYER2/NR_MAC_UE/mac.h"
//#include "RRC/LTE/rrc_extern.h"
#include "PHY_INTERFACE/phy_interface_extern.h"
#undef MALLOC //there are two conflicting definitions, so we better make sure we don't use it at all
//#undef FRAME_LENGTH_COMPLEX_SAMPLES //there are two conflicting definitions, so we better make sure we don't use it at all
#include "fapi_nr_ue_l1.h"
#include "PHY/phy_extern_nr_ue.h"
#include "PHY/INIT/phy_init.h"
#include "PHY/MODULATION/modulation_UE.h"
#include "LAYER2/NR_MAC_UE/mac_proto.h"
#include "RRC/NR_UE/rrc_proto.h"
//#ifndef NO_RAT_NR
#include "SCHED_NR/phy_frame_config_nr.h"
//#endif
#include "SCHED_NR_UE/defs.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "T.h"
#ifdef XFORMS
#include "PHY/TOOLS/nr_phy_scope.h"
extern char do_forms;
#endif
extern double cpuf;
//static nfapi_nr_config_request_t config_t;
//static nfapi_nr_config_request_t* config =&config_t;
/*
* NR SLOT PROCESSING SEQUENCE
*
* Processing occurs with following steps for connected mode:
*
* - Rx samples for a slot are received,
* - PDCCH processing (including DCI extraction for downlink and uplink),
* - PDSCH processing (including transport blocks decoding),
* - PUCCH/PUSCH (transmission of acknowledgements, CSI, ... or data).
*
* Time between reception of the slot and related transmission depends on UE processing performance.
* It is defined by the value NR_UE_CAPABILITY_SLOT_RX_TO_TX.
*
* In NR, network gives the duration between Rx slot and Tx slot in the DCI:
* - for reception of a PDSCH and its associated acknowledgment slot (with a PUCCH or a PUSCH),
* - for reception of an uplink grant and its associated PUSCH slot.
*
* So duration between reception and it associated transmission depends on its transmission slot given in the DCI.
* NR_UE_CAPABILITY_SLOT_RX_TO_TX means the minimum duration but higher duration can be given by the network because UE can support it.
*
* Slot k
* -------+------------+--------
* Frame | Tx samples |
* Subframe | buffer |
* Slot n -------+------------+--------
* ------ +------------+-------- |
* | Rx samples | |
* | buffer | |
* -------+------------+-------- |
* | |
* V |
* +------------+ |
* | PDCCH | |
* | processing | |
* +------------+ |
* | | |
* | v |
* | +------------+ |
* | | PDSCH | |
* | | processing | decoding result |
* | +------------+ -> ACK/NACK of PDSCH |
* | | |
* | v |
* | +-------------+------------+ |
* | | PUCCH/PUSCH | Tx samples | |
* | | processing | transfer | |
* | +-------------+------------+ |
* | |
* |/___________________________________________________________\|
* \ duration between reception and associated transmission /
*
* Remark: processing is done slot by slot, it can be distribute on different threads which are executed in parallel.
* This is an architecture optimization in order to cope with real time constraints.
* By example, for LTE, subframe processing is spread over 4 different threads.
*
*/
#ifndef NO_RAT_NR
#define DURATION_RX_TO_TX (NR_UE_CAPABILITY_SLOT_RX_TO_TX) /* for NR this will certainly depends to such UE capability which is not yet defined */
#else
#define DURATION_RX_TO_TX (4) /* For LTE, this duration is fixed to 4 and it is linked to LTE standard for both modes FDD/TDD */
#endif
#define FRAME_PERIOD 100000000ULL
#define DAQ_PERIOD 66667ULL
#define FIFO_PRIORITY 40
typedef enum {
pss=0,
pbch=1,
si=2
} sync_mode_t;
int32_t **rxdata;
int32_t **txdata;
#define KHz (1000UL)
#define MHz (1000*KHz)
typedef struct eutra_band_s {
int16_t band;
uint32_t ul_min;
uint32_t ul_max;
uint32_t dl_min;
uint32_t dl_max;
lte_frame_type_t frame_type;
} eutra_band_t;
typedef struct band_info_s {
int nbands;
eutra_band_t band_info[100];
} band_info_t;
band_info_t bands_to_scan;
static const eutra_band_t eutra_bands[] = {
{ 1, 1920 * MHz, 1980 * MHz, 2110 * MHz, 2170 * MHz, FDD},
{ 2, 1850 * MHz, 1910 * MHz, 1930 * MHz, 1990 * MHz, FDD},
{ 3, 1710 * MHz, 1785 * MHz, 1805 * MHz, 1880 * MHz, FDD},
{ 4, 1710 * MHz, 1755 * MHz, 2110 * MHz, 2155 * MHz, FDD},
{ 5, 824 * MHz, 849 * MHz, 869 * MHz, 894 * MHz, FDD},
{ 6, 830 * MHz, 840 * MHz, 875 * MHz, 885 * MHz, FDD},
{ 7, 2500 * MHz, 2570 * MHz, 2620 * MHz, 2690 * MHz, FDD},
{ 8, 880 * MHz, 915 * MHz, 925 * MHz, 960 * MHz, FDD},
{ 9, 1749900 * KHz, 1784900 * KHz, 1844900 * KHz, 1879900 * KHz, FDD},
{10, 1710 * MHz, 1770 * MHz, 2110 * MHz, 2170 * MHz, FDD},
{11, 1427900 * KHz, 1452900 * KHz, 1475900 * KHz, 1500900 * KHz, FDD},
{12, 698 * MHz, 716 * MHz, 728 * MHz, 746 * MHz, FDD},
{13, 777 * MHz, 787 * MHz, 746 * MHz, 756 * MHz, FDD},
{14, 788 * MHz, 798 * MHz, 758 * MHz, 768 * MHz, FDD},
{17, 704 * MHz, 716 * MHz, 734 * MHz, 746 * MHz, FDD},
{20, 832 * MHz, 862 * MHz, 791 * MHz, 821 * MHz, FDD},
{22, 3510 * MHz, 3590 * MHz, 3410 * MHz, 3490 * MHz, FDD},
{33, 1900 * MHz, 1920 * MHz, 1900 * MHz, 1920 * MHz, TDD},
{34, 2010 * MHz, 2025 * MHz, 2010 * MHz, 2025 * MHz, TDD},
{35, 1850 * MHz, 1910 * MHz, 1850 * MHz, 1910 * MHz, TDD},
{36, 1930 * MHz, 1990 * MHz, 1930 * MHz, 1990 * MHz, TDD},
{37, 1910 * MHz, 1930 * MHz, 1910 * MHz, 1930 * MHz, TDD},
{38, 2570 * MHz, 2620 * MHz, 2570 * MHz, 2630 * MHz, TDD},
{39, 1880 * MHz, 1920 * MHz, 1880 * MHz, 1920 * MHz, TDD},
{40, 2300 * MHz, 2400 * MHz, 2300 * MHz, 2400 * MHz, TDD},
{41, 2496 * MHz, 2690 * MHz, 2496 * MHz, 2690 * MHz, TDD},
{42, 3400 * MHz, 3600 * MHz, 3400 * MHz, 3600 * MHz, TDD},
{43, 3600 * MHz, 3800 * MHz, 3600 * MHz, 3800 * MHz, TDD},
{44, 703 * MHz, 803 * MHz, 703 * MHz, 803 * MHz, TDD},
};
PHY_VARS_NR_UE *init_nr_ue_vars(NR_DL_FRAME_PARMS *frame_parms,
uint8_t UE_id,
uint8_t abstraction_flag)
{
PHY_VARS_NR_UE *ue;
if (frame_parms!=(NR_DL_FRAME_PARMS *)NULL) { // if we want to give initial frame parms, allocate the PHY_VARS_UE structure and put them in
ue = (PHY_VARS_NR_UE *)malloc(sizeof(PHY_VARS_NR_UE));
memset(ue,0,sizeof(PHY_VARS_NR_UE));
memcpy(&(ue->frame_parms), frame_parms, sizeof(NR_DL_FRAME_PARMS));
} else ue = PHY_vars_UE_g[UE_id][0];
ue->Mod_id = UE_id;
ue->mac_enabled = 1;
// initialize all signal buffers
init_nr_ue_signal(ue,1,abstraction_flag);
// intialize transport
init_nr_ue_transport(ue,abstraction_flag);
return(ue);
}
/*!
* It performs band scanning and synchonization.
* \param arg is a pointer to a \ref PHY_VARS_NR_UE structure.
*/
typedef struct syncData_s {
PHY_VARS_NR_UE *UE;
} syncData_t;
static void UE_synch(void *arg) {
syncData_t *syncD=(syncData_t *) arg;
int i, hw_slot_offset;
PHY_VARS_NR_UE *UE = syncD->UE;
int current_band = 0;
int current_offset = 0;
sync_mode_t sync_mode = pbch;
int CC_id = UE->CC_id;
int freq_offset=0;
UE->is_synchronized = 0;
if (UE->UE_scan == 0) {
int ind;
for ( ind=0; ind < sizeof(eutra_bands) / sizeof(eutra_bands[0]);
ind++) {
current_band = eutra_bands[ind].band;
LOG_D(PHY, "Scanning band %d, dl_min %"PRIu32", ul_min %"PRIu32"\n", current_band, eutra_bands[ind].dl_min,eutra_bands[ind].ul_min);
if ( eutra_bands[ind].dl_min <= downlink_frequency[0][0] && eutra_bands[ind].dl_max >= downlink_frequency[0][0] ) {
for (i=0; i<4; i++)
uplink_frequency_offset[CC_id][i] = eutra_bands[ind].ul_min - eutra_bands[ind].dl_min;
break;
}
}
AssertFatal( ind < sizeof(eutra_bands) / sizeof(eutra_bands[0]), "Can't find EUTRA band for frequency");
LOG_I( PHY, "[SCHED][UE] Check absolute frequency DL %"PRIu32", UL %"PRIu32" (oai_exit %d, rx_num_channels %d)\n",
downlink_frequency[0][0], downlink_frequency[0][0]+uplink_frequency_offset[0][0],
oai_exit, openair0_cfg[0].rx_num_channels);
for (i=0; i<openair0_cfg[UE->rf_map.card].rx_num_channels; i++) {
openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i] = downlink_frequency[CC_id][i];
openair0_cfg[UE->rf_map.card].tx_freq[UE->rf_map.chain+i] =
downlink_frequency[CC_id][i]+uplink_frequency_offset[CC_id][i];
openair0_cfg[UE->rf_map.card].autocal[UE->rf_map.chain+i] = 1;
if (uplink_frequency_offset[CC_id][i] != 0) //
openair0_cfg[UE->rf_map.card].duplex_mode = duplex_mode_FDD;
else //FDD
openair0_cfg[UE->rf_map.card].duplex_mode = duplex_mode_TDD;
}
sync_mode = pbch;
} else {
current_band=0;
for (i=0; i<openair0_cfg[UE->rf_map.card].rx_num_channels; i++) {
downlink_frequency[UE->rf_map.card][UE->rf_map.chain+i] = bands_to_scan.band_info[CC_id].dl_min;
uplink_frequency_offset[UE->rf_map.card][UE->rf_map.chain+i] =
bands_to_scan.band_info[CC_id].ul_min-bands_to_scan.band_info[CC_id].dl_min;
openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i] = downlink_frequency[CC_id][i];
openair0_cfg[UE->rf_map.card].tx_freq[UE->rf_map.chain+i] =
downlink_frequency[CC_id][i]+uplink_frequency_offset[CC_id][i];
openair0_cfg[UE->rf_map.card].rx_gain[UE->rf_map.chain+i] = UE->rx_total_gain_dB;
}
}
LOG_W(PHY, "Starting sync detection\n");
switch (sync_mode) {
case pss:
LOG_I(PHY,"[SCHED][UE] Scanning band %d (%d), freq %u\n",bands_to_scan.band_info[current_band].band, current_band,bands_to_scan.band_info[current_band].dl_min+current_offset);
//lte_sync_timefreq(UE,current_band,bands_to_scan.band_info[current_band].dl_min+current_offset);
current_offset += 20000000; // increase by 20 MHz
if (current_offset > bands_to_scan.band_info[current_band].dl_max-bands_to_scan.band_info[current_band].dl_min) {
current_band++;
current_offset=0;
}
if (current_band==bands_to_scan.nbands) {
current_band=0;
oai_exit=1;
}
for (i=0; i<openair0_cfg[UE->rf_map.card].rx_num_channels; i++) {
downlink_frequency[UE->rf_map.card][UE->rf_map.chain+i] = bands_to_scan.band_info[current_band].dl_min+current_offset;
uplink_frequency_offset[UE->rf_map.card][UE->rf_map.chain+i] = bands_to_scan.band_info[current_band].ul_min-bands_to_scan.band_info[0].dl_min + current_offset;
openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i] = downlink_frequency[CC_id][i];
openair0_cfg[UE->rf_map.card].tx_freq[UE->rf_map.chain+i] = downlink_frequency[CC_id][i]+uplink_frequency_offset[CC_id][i];
openair0_cfg[UE->rf_map.card].rx_gain[UE->rf_map.chain+i] = UE->rx_total_gain_dB;
if (UE->UE_scan_carrier) {
openair0_cfg[UE->rf_map.card].autocal[UE->rf_map.chain+i] = 1;
}
}
break;
case pbch:
LOG_I(PHY, "[UE thread Synch] Running Initial Synch (mode %d)\n",UE->mode);
if (nr_initial_sync( UE, UE->mode ) == 0) {
freq_offset = UE->common_vars.freq_offset; // frequency offset computed with pss in initial sync
hw_slot_offset = (UE->rx_offset<<1) / UE->frame_parms.samples_per_slot;
LOG_I(PHY,"Got synch: hw_slot_offset %d, carrier off %d Hz, rxgain %d (DL %u, UL %u), UE_scan_carrier %d\n",
hw_slot_offset,
freq_offset,
UE->rx_total_gain_dB,
downlink_frequency[0][0]+freq_offset,
downlink_frequency[0][0]+uplink_frequency_offset[0][0]+freq_offset,
UE->UE_scan_carrier );
// rerun with new cell parameters and frequency-offset
for (i=0; i<openair0_cfg[UE->rf_map.card].rx_num_channels; i++) {
openair0_cfg[UE->rf_map.card].rx_gain[UE->rf_map.chain+i] = UE->rx_total_gain_dB;//-USRP_GAIN_OFFSET;
if (freq_offset >= 0)
openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i] += abs(freq_offset);
else
openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i] -= abs(freq_offset);
openair0_cfg[UE->rf_map.card].tx_freq[UE->rf_map.chain+i] =
openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i]+uplink_frequency_offset[CC_id][i];
downlink_frequency[CC_id][i] = openair0_cfg[CC_id].rx_freq[i];
}
// reconfigure for potentially different bandwidth
switch(UE->frame_parms.N_RB_DL) {
case 6:
openair0_cfg[UE->rf_map.card].sample_rate =1.92e6;
openair0_cfg[UE->rf_map.card].rx_bw =.96e6;
openair0_cfg[UE->rf_map.card].tx_bw =.96e6;
// openair0_cfg[0].rx_gain[0] -= 12;
break;
case 25:
openair0_cfg[UE->rf_map.card].sample_rate =7.68e6;
openair0_cfg[UE->rf_map.card].rx_bw =2.5e6;
openair0_cfg[UE->rf_map.card].tx_bw =2.5e6;
// openair0_cfg[0].rx_gain[0] -= 6;
break;
case 50:
openair0_cfg[UE->rf_map.card].sample_rate =15.36e6;
openair0_cfg[UE->rf_map.card].rx_bw =5.0e6;
openair0_cfg[UE->rf_map.card].tx_bw =5.0e6;
// openair0_cfg[0].rx_gain[0] -= 3;
break;
case 100:
openair0_cfg[UE->rf_map.card].sample_rate=30.72e6;
openair0_cfg[UE->rf_map.card].rx_bw=10.0e6;
openair0_cfg[UE->rf_map.card].tx_bw=10.0e6;
// openair0_cfg[0].rx_gain[0] -= 0;
break;
}
if (UE->mode != loop_through_memory) {
UE->rfdevice.trx_set_freq_func(&UE->rfdevice,&openair0_cfg[0],0);
//UE->rfdevice.trx_set_gains_func(&openair0,&openair0_cfg[0]);
//UE->rfdevice.trx_stop_func(&UE->rfdevice);
// sleep(1);
//nr_init_frame_parms_ue(&UE->frame_parms);
/*if (UE->rfdevice.trx_start_func(&UE->rfdevice) != 0 ) {
LOG_E(HW,"Could not start the device\n");
oai_exit=1;
}*/
}
if (UE->UE_scan_carrier == 1) {
UE->UE_scan_carrier = 0;
} else {
UE->is_synchronized = 1;
}
} else {
// initial sync failed
// calculate new offset and try again
if (UE->UE_scan_carrier == 1) {
if (freq_offset >= 0)
freq_offset += 100;
freq_offset *= -1;
LOG_I(PHY, "[initial_sync] trying carrier off %d Hz, rxgain %d (DL %u, UL %u)\n",
freq_offset,
UE->rx_total_gain_dB,
downlink_frequency[0][0]+freq_offset,
downlink_frequency[0][0]+uplink_frequency_offset[0][0]+freq_offset );
for (i=0; i<openair0_cfg[UE->rf_map.card].rx_num_channels; i++) {
openair0_cfg[UE->rf_map.card].rx_freq[UE->rf_map.chain+i] = downlink_frequency[CC_id][i]+freq_offset;
openair0_cfg[UE->rf_map.card].tx_freq[UE->rf_map.chain+i] = downlink_frequency[CC_id][i]+uplink_frequency_offset[CC_id][i]+freq_offset;
openair0_cfg[UE->rf_map.card].rx_gain[UE->rf_map.chain+i] = UE->rx_total_gain_dB;//-USRP_GAIN_OFFSET;
if (UE->UE_scan_carrier==1)
openair0_cfg[UE->rf_map.card].autocal[UE->rf_map.chain+i] = 1;
}
if (UE->mode != loop_through_memory)
UE->rfdevice.trx_set_freq_func(&UE->rfdevice,&openair0_cfg[0],0);
}// initial_sync=0
break;
case si:
default:
break;
}
}
}
void processSubframeRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
// Process Rx data for one sub-frame
if (slot_select_nr(&UE->frame_parms, proc->frame_tx, proc->nr_tti_tx) & NR_DOWNLINK_SLOT) {
//clean previous FAPI MESSAGE
UE->rx_ind.number_pdus = 0;
UE->dci_ind.number_of_dcis = 0;
//clean previous FAPI MESSAGE
// call L2 for DL_CONFIG (DCI)
UE->dcireq.module_id = UE->Mod_id;
UE->dcireq.gNB_index = 0;
UE->dcireq.cc_id = 0;
UE->dcireq.frame = proc->frame_rx;
UE->dcireq.slot = proc->nr_tti_rx;
nr_ue_dcireq(&UE->dcireq); //to be replaced with function pointer later
NR_UE_MAC_INST_t *UE_mac = get_mac_inst(0);
UE_mac->scheduled_response.dl_config = &UE->dcireq.dl_config_req;
UE_mac->scheduled_response.slot = proc->nr_tti_rx;
nr_ue_scheduled_response(&UE_mac->scheduled_response);
//write_output("uerxdata_frame.m", "uerxdata_frame", UE->common_vars.rxdata[0], UE->frame_parms.samples_per_frame, 1, 1);
printf("Processing slot %d\n",proc->nr_tti_rx);
#ifdef UE_SLOT_PARALLELISATION
phy_procedures_slot_parallelization_nrUE_RX( UE, proc, 0, 0, 1, UE->mode, no_relay, NULL );
#else
phy_procedures_nrUE_RX( UE, proc, 0, 1, UE->mode);
// printf(">>> nr_ue_pdcch_procedures ended\n");
#endif
}
if (UE->mac_enabled==1) {
// trigger L2 to run ue_scheduler thru IF module
// [TODO] mapping right after NR initial sync
if(UE->if_inst != NULL && UE->if_inst->ul_indication != NULL) {
UE->ul_indication.module_id = 0;
UE->ul_indication.gNB_index = 0;
UE->ul_indication.cc_id = 0;
UE->ul_indication.frame = proc->frame_rx;
UE->ul_indication.slot = proc->nr_tti_rx;
UE->if_inst->ul_indication(&UE->ul_indication);
}
}
}
/*!
* \brief This is the UE thread for RX subframe n and TX subframe n+4.
* This thread performs the phy_procedures_UE_RX() on every received slot.
* then, if TX is enabled it performs TX for n+4.
* \param arg is a pointer to a \ref PHY_VARS_NR_UE structure.
* \returns a pointer to an int. The storage is not on the heap and must not be freed.
*/
typedef struct processingData_s {
UE_nr_rxtx_proc_t proc;
PHY_VARS_NR_UE *UE;
} processingData_t;
void UE_processing(void *arg) {
processingData_t *rxtxD=(processingData_t *) arg;
UE_nr_rxtx_proc_t *proc = &rxtxD->proc;
PHY_VARS_NR_UE *UE = rxtxD->UE;
processSubframeRX(UE, proc);
//printf(">>> mac ended\n");
// Prepare the future Tx data
#if 0
#ifndef NO_RAT_NR
if (slot_select_nr(&UE->frame_parms, proc->frame_tx, proc->nr_tti_tx) & NR_UPLINK_SLOT)
#else
if ((subframe_select( &UE->frame_parms, proc->subframe_tx) == SF_UL) ||
(UE->frame_parms.frame_type == FDD) )
#endif
if (UE->mode != loop_through_memory)
phy_procedures_nrUE_TX(UE,proc,0,0,UE->mode,no_relay);
//phy_procedures_UE_TX(UE,proc,0,0,UE->mode,no_relay);
#endif
#if 0
if ((subframe_select( &UE->frame_parms, proc->subframe_tx) == SF_S) &&
(UE->frame_parms.frame_type == TDD))
if (UE->mode != loop_through_memory)
//phy_procedures_UE_S_TX(UE,0,0,no_relay);
updateTimes(current, &t3, 10000, timing_proc_name);
#endif
}
void readFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp) {
void *rxp[NB_ANTENNAS_RX];
void *dummy_tx[UE->frame_parms.nb_antennas_tx];
for (int i=0; i<UE->frame_parms.nb_antennas_tx; i++)
dummy_tx[i]=malloc16_clear(UE->frame_parms.samples_per_subframe*4);
for(int x=0; x<10; x++) {
for (int i=0; i<UE->frame_parms.nb_antennas_rx; i++)
rxp[i] = ((void *)&UE->common_vars.rxdata[i][0]) + 4*x*UE->frame_parms.samples_per_subframe;
AssertFatal( UE->frame_parms.samples_per_subframe ==
UE->rfdevice.trx_read_func(&UE->rfdevice,
timestamp,
rxp,
UE->frame_parms.samples_per_subframe,
UE->frame_parms.nb_antennas_rx), "");
}
for (int i=0; i<UE->frame_parms.nb_antennas_tx; i++)
free(dummy_tx[i]);
}
void trashFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp) {
void *dummy_tx[UE->frame_parms.nb_antennas_tx];
for (int i=0; i<UE->frame_parms.nb_antennas_tx; i++)
dummy_tx[i]=malloc16_clear(UE->frame_parms.samples_per_subframe*4);
void *dummy_rx[UE->frame_parms.nb_antennas_rx];
for (int i=0; i<UE->frame_parms.nb_antennas_rx; i++)
dummy_rx[i]=malloc16(UE->frame_parms.samples_per_subframe*4);
for (int sf=0; sf<NR_NUMBER_OF_SUBFRAMES_PER_FRAME; sf++) {
// printf("Reading dummy sf %d\n",sf);
UE->rfdevice.trx_read_func(&UE->rfdevice,
timestamp,
dummy_rx,
UE->frame_parms.samples_per_subframe,
UE->frame_parms.nb_antennas_rx);
}
for (int i=0; i<UE->frame_parms.nb_antennas_tx; i++)
free(dummy_tx[i]);
for (int i=0; i<UE->frame_parms.nb_antennas_rx; i++)
free(dummy_rx[i]);
}
void syncInFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp) {
if (UE->no_timing_correction==0) {
LOG_I(PHY,"Resynchronizing RX by %d samples (mode = %d)\n",UE->rx_offset,UE->mode);
void *dummy_tx[UE->frame_parms.nb_antennas_tx];
for (int i=0; i<UE->frame_parms.nb_antennas_tx; i++)
dummy_tx[i]=malloc16_clear(UE->frame_parms.samples_per_subframe*4);
for ( int size=UE->rx_offset ; size > 0 ; size -= UE->frame_parms.samples_per_subframe ) {
int unitTransfer=size>UE->frame_parms.samples_per_subframe ? UE->frame_parms.samples_per_subframe : size ;
AssertFatal(unitTransfer ==
UE->rfdevice.trx_read_func(&UE->rfdevice,
timestamp,
(void **)UE->common_vars.rxdata,
unitTransfer,
UE->frame_parms.nb_antennas_rx),"");
}
for (int i=0; i<UE->frame_parms.nb_antennas_tx; i++)
free(dummy_tx[i]);
}
}
int computeSamplesShift(PHY_VARS_NR_UE *UE) {
if ( getenv("RFSIMULATOR") != 0) {
LOG_E(PHY,"SET rx_offset %d \n",UE->rx_offset);
//UE->rx_offset_diff=0;
return 0;
}
// compute TO compensation that should be applied for this frame
if ( UE->rx_offset < 5*UE->frame_parms.samples_per_slot &&
UE->rx_offset > 0 )
return -1 ;
if ( UE->rx_offset > 5*UE->frame_parms.samples_per_slot &&
UE->rx_offset < 10*UE->frame_parms.samples_per_slot )
return 1;
return 0;
}
void *UE_thread(void *arg) {
PHY_VARS_NR_UE *UE = (PHY_VARS_NR_UE *) arg;
// int tx_enabled = 0;
openair0_timestamp timestamp;
void *rxp[NB_ANTENNAS_RX], *txp[NB_ANTENNAS_TX];
int start_rx_stream = 0;
const uint16_t table_sf_slot[20] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9};
AssertFatal(0== openair0_device_load(&(UE->rfdevice), &openair0_cfg[0]), "");
UE->rfdevice.host_type = RAU_HOST;
AssertFatal(UE->rfdevice.trx_start_func(&UE->rfdevice) == 0, "Could not start the device\n");
notifiedFIFO_t nf;
initNotifiedFIFO(&nf);
bool syncRunning=false;
notifiedFIFO_elt_t *syncMsg=newNotifiedFIFO_elt(sizeof(syncData_t),0,&nf,UE_synch);
syncData_t *syncD=(syncData_t *)NotifiedFifoData(syncMsg);
syncD->UE=UE;
int nbSlotProcessing=0;
int thread_idx=0;
notifiedFIFO_elt_t *processingMsg[RX_NB_TH];
for (int i=0; i<RX_NB_TH; i++) {
processingMsg[i]= newNotifiedFIFO_elt(sizeof(processingData_t), 0,&nf,UE_processing);
processingData_t *tmp=(processingData_t *)NotifiedFifoData(processingMsg[i]);
tmp->UE=UE;
}
const int nb_slot_frame = 10*UE->frame_parms.slots_per_subframe;
int absolute_slot=-1;
while (!oai_exit) {
if (!syncD->UE->is_synchronized) {
if (syncRunning) {
notifiedFIFO_elt_t *res=tryPullTpool(&nf, Tpool);
if (res) {
syncRunning=false;
} else
trashFrame(UE, &timestamp);
} else {
readFrame(UE, &timestamp);
pushTpool(Tpool, syncMsg);
syncRunning=true;
}
continue;
}
if (start_rx_stream==0) {
start_rx_stream=1;
syncInFrame(UE, &timestamp);
UE->rx_offset=0;
UE->time_sync_cell=0;
//printf("first stream frame rx %d\n",UE->proc.proc_rxtx[0].frame_rx);
// read in first symbol
AssertFatal (UE->frame_parms.ofdm_symbol_size+UE->frame_parms.nb_prefix_samples0 ==
UE->rfdevice.trx_read_func(&UE->rfdevice,
&timestamp,
(void **)UE->common_vars.rxdata,
UE->frame_parms.ofdm_symbol_size+UE->frame_parms.nb_prefix_samples0,
UE->frame_parms.nb_antennas_rx),"");
continue;
}
absolute_slot++;
thread_idx = absolute_slot % RX_NB_TH;
int slot_nr=absolute_slot % nb_slot_frame;
UE_nr_rxtx_proc_t *proc=&(((processingData_t *)NotifiedFifoData(processingMsg[thread_idx]))->proc);
// update thread index for received subframe
proc->nr_tti_rx= slot_nr;
UE->current_thread_id[slot_nr] = thread_idx;
proc->subframe_rx=table_sf_slot[slot_nr];
proc->nr_tti_tx = (absolute_slot + DURATION_RX_TO_TX) % nb_slot_frame;
proc->subframe_tx=proc->nr_tti_rx;
proc->frame_rx = ( absolute_slot/nb_slot_frame ) % MAX_FRAME_NUMBER;
proc->frame_tx = ( (absolute_slot + DURATION_RX_TO_TX) /nb_slot_frame ) % MAX_FRAME_NUMBER;
LOG_D(PHY,"Process slot %d thread Idx %d \n", slot_nr, thread_idx);
for (int i=0; i<UE->frame_parms.nb_antennas_rx; i++)
rxp[i] = (void *)&UE->common_vars.rxdata[i][UE->frame_parms.ofdm_symbol_size+
UE->frame_parms.nb_prefix_samples0+
slot_nr*UE->frame_parms.samples_per_slot];
for (int i=0; i<UE->frame_parms.nb_antennas_tx; i++)
txp[i] = (void *)&UE->common_vars.txdata[i][proc->nr_tti_tx*UE->frame_parms.samples_per_slot];
int readBlockSize, writeBlockSize;
if (slot_nr<(nb_slot_frame - 1)) {
readBlockSize=UE->frame_parms.samples_per_slot;
writeBlockSize=UE->frame_parms.samples_per_slot;
} else {
UE->rx_offset_diff = computeSamplesShift(UE);
readBlockSize=UE->frame_parms.samples_per_slot -
UE->frame_parms.ofdm_symbol_size -
UE->frame_parms.nb_prefix_samples0 -
UE->rx_offset_diff;
writeBlockSize=UE->frame_parms.samples_per_slot -
UE->rx_offset_diff;
}
AssertFatal(readBlockSize ==
UE->rfdevice.trx_read_func(&UE->rfdevice,
&timestamp,
rxp,
readBlockSize,
UE->frame_parms.nb_antennas_rx),"");
AssertFatal( writeBlockSize ==
UE->rfdevice.trx_write_func(&UE->rfdevice,
timestamp+
(2*UE->frame_parms.samples_per_slot) -
UE->frame_parms.ofdm_symbol_size-UE->frame_parms.nb_prefix_samples0 -
openair0_cfg[0].tx_sample_advance,
txp,
writeBlockSize,
UE->frame_parms.nb_antennas_tx,
1),"");
if( slot_nr==(nb_slot_frame-1)) {
// read in first symbol of next frame and adjust for timing drift
int first_symbols=writeBlockSize-readBlockSize;
if ( first_symbols > 0 )
AssertFatal(first_symbols ==
UE->rfdevice.trx_read_func(&UE->rfdevice,
&timestamp,
(void **)UE->common_vars.rxdata,
first_symbols,
UE->frame_parms.nb_antennas_rx),"");
else
LOG_E(PHY,"can't compensate: diff =%d\n", first_symbols);
}
proc->timestamp_tx = timestamp+
(DURATION_RX_TO_TX*UE->frame_parms.samples_per_slot)-
UE->frame_parms.ofdm_symbol_size-UE->frame_parms.nb_prefix_samples0;
if (getenv("RFSIMULATOR")) {
// FixMe: Wait previous thread is done, because race conditions seems too bad
// in case of actual RF board, the overlap between threads mitigate the issue
while (!tryPullTpool(&nf, Tpool)) {
nbSlotProcessing--;
usleep(200);
}
}
while (nbSlotProcessing >= RX_NB_TH && !tryPullTpool(&nf, Tpool)) {
nbSlotProcessing--;
usleep(200);
}
pushTpool(Tpool, processingMsg[thread_idx]);
} // while !oai_exit
return NULL;
}
void init_UE(int nb_inst) {
int inst;
NR_UE_MAC_INST_t *mac_inst;
pthread_t threads[nb_inst];
pthread_attr_t attr;
pthread_attr_init(&attr);
pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED);
pthread_attr_setinheritsched(&attr, PTHREAD_EXPLICIT_SCHED);
pthread_attr_setschedpolicy(&attr, SCHED_RR);
struct sched_param sched;
sched.sched_priority = sched_get_priority_max(SCHED_RR)-1;
pthread_attr_setschedparam(&attr, &sched);
for (inst=0; inst < nb_inst; inst++) {
// UE->rfdevice.type = NONE_DEV;
//PHY_VARS_NR_UE *UE = PHY_vars_UE_g[inst][0];
LOG_I(PHY,"Initializing memory for UE instance %d (%p)\n",inst,PHY_vars_UE_g[inst]);
PHY_vars_UE_g[inst][0] = init_nr_ue_vars(NULL,inst,0);
PHY_VARS_NR_UE *UE = PHY_vars_UE_g[inst][0];
AssertFatal((UE->if_inst = nr_ue_if_module_init(inst)) != NULL, "can not initial IF module\n");
nr_l3_init_ue();
nr_l2_init_ue();
mac_inst = get_mac_inst(0);
mac_inst->if_module = UE->if_inst;
UE->if_inst->scheduled_response = nr_ue_scheduled_response;
UE->if_inst->phy_config_request = nr_ue_phy_config_request;
LOG_I(PHY,"Intializing UE Threads for instance %d (%p,%p)...\n",inst,PHY_vars_UE_g[inst],PHY_vars_UE_g[inst][0]);
//init_UE_threads(inst);
//UE = PHY_vars_UE_g[inst][0];
AssertFatal(0 == pthread_create(&threads[inst],
&attr,
UE_thread,
(void *)UE), "");
}
printf("UE threads created by %ld\n", gettid());
}