Merge remote-tracking branch 'origin/develop' into NR_UL_VRB_MAP_improv
This commit is contained in:
@@ -73,6 +73,8 @@ void fill_ul_config(fapi_nr_ul_config_request_t *ul_config, frame_t frame_tx, in
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memset(ul_config->ul_config_list, 0, sizeof(ul_config->ul_config_list));
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}
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ul_config->ul_config_list[ul_config->number_pdus].pdu_type = pdu_type;
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//ul_config->slot = slot_tx;
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//ul_config->sfn = frame_tx;
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ul_config->slot = slot_tx;
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ul_config->sfn = frame_tx;
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ul_config->number_pdus++;
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@@ -971,6 +973,8 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
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uint8_t ulsch_input_buffer_array[NFAPI_MAX_NUM_UL_PDU][MAX_ULSCH_PAYLOAD_BYTES];
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nr_scheduled_response_t scheduled_response;
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fapi_nr_tx_request_t tx_req;
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//tx_req.slot = slot_tx;
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//tx_req.sfn = frame_tx;
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tx_req.slot = slot_tx;
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tx_req.sfn = frame_tx;
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tx_req.number_of_pdus = 0;
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@@ -55,6 +55,7 @@
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#include <errno.h>
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#include <string.h>
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const uint8_t nr_rv_round_map[4] = { 0, 2, 3, 1 };
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uint16_t nr_pdcch_order_table[6] = { 31, 31, 511, 2047, 2047, 8191 };
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uint8_t vnf_first_sched_entry = 1;
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@@ -272,6 +273,7 @@ bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot) {
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void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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frame_t frame,
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sub_frame_t slot){
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//pthread_mutex_lock(&mutextest);
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protocol_ctxt_t ctxt={0};
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PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frame, slot,module_idP);
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@@ -387,7 +389,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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nr_schedule_ulsch(module_idP, frame, slot);
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// This schedules the DCI for Downlink and PDSCH
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nr_schedule_ue_spec(module_idP, frame, slot);
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start_meas(&gNB->schedule_dlsch);
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nr_schedule_ue_spec(module_idP, frame, slot);
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stop_meas(&gNB->schedule_dlsch);
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nr_schedule_pucch(module_idP, frame, slot);
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@@ -433,6 +433,7 @@ uint32_t schedule_control_sib1(module_id_t module_id,
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void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
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nfapi_nr_dl_tti_request_body_t *dl_req,
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int pdu_index,
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NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config,
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uint32_t TBS,
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int StartSymbolIndex,
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@@ -465,7 +466,7 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
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pdsch_pdu_rel15->pduBitmap = 0;
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pdsch_pdu_rel15->rnti = SI_RNTI;
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pdsch_pdu_rel15->pduIndex = gNB_mac->pdu_index[0]++;
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pdsch_pdu_rel15->pduIndex = pdu_index;
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pdsch_pdu_rel15->BWPSize = type0_PDCCH_CSS_config->num_rbs;
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pdsch_pdu_rel15->BWPStart = type0_PDCCH_CSS_config->cset_start_rb;
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@@ -632,7 +633,8 @@ void schedule_nr_sib1(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
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candidate_idx, sib1_sdu_length);
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nfapi_nr_dl_tti_request_body_t *dl_req = &gNB_mac->DL_req[CC_id].dl_tti_request_body;
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nr_fill_nfapi_dl_sib1_pdu(module_idP, dl_req, type0_PDCCH_CSS_config, TBS, startSymbolIndex, nrOfSymbols, dlDmrsSymbPos);
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int pdu_index = gNB_mac->pdu_index[0]++;
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nr_fill_nfapi_dl_sib1_pdu(module_idP, dl_req, pdu_index, type0_PDCCH_CSS_config, TBS, startSymbolIndex, nrOfSymbols, dlDmrsSymbPos);
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const int ntx_req = gNB_mac->TX_req[CC_id].Number_of_PDUs;
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nfapi_nr_pdu_t *tx_req = &gNB_mac->TX_req[CC_id].pdu_list[ntx_req];
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@@ -642,7 +644,7 @@ void schedule_nr_sib1(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
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memcpy(tx_req->TLVs[0].value.direct, sib1_payload, sib1_sdu_length);
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tx_req->PDU_length = TBS;
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tx_req->PDU_index = gNB_mac->pdu_index[0]++;
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tx_req->PDU_index = pdu_index;
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tx_req->num_TLV = 1;
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tx_req->TLVs[0].length = TBS + 2;
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gNB_mac->TX_req[CC_id].Number_of_PDUs++;
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@@ -409,7 +409,7 @@ int get_mcs_from_bler(module_id_t mod_id, int CC_id, frame_t frame, sub_frame_t
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/*const int dret3x = stats->dlsch_rounds[3] - bler_stats->dlsch_rounds[3];
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if (dret3x > 0) {
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if there is a third retransmission, decrease MCS for stabilization and
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restart averaging window to stabilize transmission
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restart averaging window to stabilize transmission
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bler_stats->last_frame_slot = now;
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bler_stats->mcs = max(9, bler_stats->mcs - 1);
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memcpy(bler_stats->dlsch_rounds, stats->dlsch_rounds, sizeof(stats->dlsch_rounds));
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@@ -431,7 +431,7 @@ int get_mcs_from_bler(module_id_t mod_id, int CC_id, frame_t frame, sub_frame_t
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int new_mcs = old_mcs;
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// TODO put back this condition when relevant
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/* first ensure that number of 2nd retx is below threshold. If this is the
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* case, use 1st retx to adjust faster
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* case, use 1st retx to adjust faster
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if (bler_stats->rd2_bler > nrmac->dl_rd2_bler_threshold && old_mcs > 6) {
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new_mcs -= 2;
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} else if (bler_stats->rd2_bler < nrmac->dl_rd2_bler_threshold) {*/
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@@ -486,7 +486,8 @@ void nr_store_dlsch_buffer(module_id_t module_id,
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DL_SCH_LCID_DCCH,
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0,
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0);
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if ((sched_ctrl->lcid_mask&(1<<4)) > 0)
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if ((sched_ctrl->lcid_mask&(1<<4)) > 0) {
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start_meas(&RC.nrmac[module_id]->rlc_status_ind);
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sched_ctrl->rlc_status[DL_SCH_LCID_DTCH] = mac_rlc_status_ind(module_id,
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rnti,
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module_id,
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@@ -497,16 +498,17 @@ void nr_store_dlsch_buffer(module_id_t module_id,
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DL_SCH_LCID_DTCH,
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0,
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0);
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if(sched_ctrl->rlc_status[DL_SCH_LCID_DCCH].bytes_in_buffer > 0){
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lcid = DL_SCH_LCID_DCCH;
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}
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else if (sched_ctrl->rlc_status[DL_SCH_LCID_DCCH1].bytes_in_buffer > 0)
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{
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lcid = DL_SCH_LCID_DCCH1;
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}else{
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lcid = DL_SCH_LCID_DTCH;
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}
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stop_meas(&RC.nrmac[module_id]->rlc_status_ind);
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}
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if(sched_ctrl->rlc_status[DL_SCH_LCID_DCCH].bytes_in_buffer > 0){
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lcid = DL_SCH_LCID_DCCH;
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}
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else if (sched_ctrl->rlc_status[DL_SCH_LCID_DCCH1].bytes_in_buffer > 0)
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{
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lcid = DL_SCH_LCID_DCCH1;
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}else{
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lcid = DL_SCH_LCID_DTCH;
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}
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sched_ctrl->num_total_bytes += sched_ctrl->rlc_status[lcid].bytes_in_buffer;
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//later multiplex here. Just select DCCH/SRB before DTCH/DRB
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@@ -584,10 +586,10 @@ bool allocate_dl_retransmission(module_id_t module_id,
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temp_ps.nrOfLayers = 1;
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nr_set_pdsch_semi_static(scc, cg, sched_ctrl->active_bwp, bwpd, tda, f, &temp_ps);
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while (rbStart < bwpSize &&
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!(rballoc_mask[rbStart]&SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols)))
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!(rballoc_mask[rbStart]&SL_to_bitmap(temp_ps.startSymbolIndex, temp_ps.nrOfSymbols)))
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rbStart++;
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while (rbStart + rbSize < bwpSize &&
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(rballoc_mask[rbStart + rbSize]&SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols)))
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(rballoc_mask[rbStart + rbSize]&SL_to_bitmap(temp_ps.startSymbolIndex, temp_ps.nrOfSymbols)))
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rbSize++;
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uint32_t new_tbs;
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uint16_t new_rbSize;
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@@ -613,7 +615,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
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/* Find a free CCE */
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const int cid = sched_ctrl->coreset->controlResourceSetId;
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const uint16_t Y = RC.nrmac[module_id]->UE_info.Y[UE_id][cid%3][slot];
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const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
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uint8_t nr_of_candidates;
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for (int i=0; i<5; i++) {
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// for now taking the lowest value among the available aggregation levels
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@@ -775,7 +777,7 @@ void pf_dl(module_id_t module_id,
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/* Find a free CCE */
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const int cid = sched_ctrl->coreset->controlResourceSetId;
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const uint16_t Y = RC.nrmac[module_id]->UE_info.Y[UE_id][cid%3][slot];
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const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
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uint8_t nr_of_candidates;
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for (int i=0; i<5; i++) {
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// for now taking the lowest value among the available aggregation levels
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@@ -1163,6 +1165,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
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pdsch_pdu->pduBitmap |= 0x1; // Bit 0: pdschPtrs - Indicates PTRS included (FR2)
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}
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LOG_D(NR_MAC,"Configuring DCI/PDCCH in %d.%d at CCE %d, rnti %x\n", frame,slot,sched_ctrl->cce_index,rnti);
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/* Fill PDCCH DL DCI PDU */
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nfapi_nr_dl_dci_pdu_t *dci_pdu = &pdcch_pdu->dci_pdu[pdcch_pdu->numDlDci];
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pdcch_pdu->numDlDci++;
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@@ -1295,6 +1298,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
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// const int lcid = DL_SCH_LCID_DTCH;
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const int lcid = sched_ctrl->lcid_to_schedule;
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int dlsch_total_bytes = 0;
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start_meas(&gNB_mac->rlc_data_req);
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if (sched_ctrl->num_total_bytes > 0) {
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tbs_size_t len = 0;
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while (size > 3) {
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@@ -1308,6 +1312,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
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/* limit requested number of bytes to what preprocessor specified, or
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* such that TBS is full */
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const rlc_buffer_occupancy_t ndata = min(sched_ctrl->rlc_status[lcid].bytes_in_buffer, size);
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len = mac_rlc_data_req(module_id,
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rnti,
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module_id,
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@@ -1368,6 +1373,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
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buf += size;
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dlsch_total_bytes += size;
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}
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stop_meas(&gNB_mac->rlc_data_req);
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// Add padding header and zero rest out if there is space left
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if (size > 0) {
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@@ -53,7 +53,6 @@
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//#define UL_HARQ_PRINT
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extern RAN_CONTEXT_t RC;
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const uint8_t nr_rv_round_map[4] = {0, 2, 3, 1};
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//#define ENABLE_MAC_PAYLOAD_DEBUG 1
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//uint8_t mac_pdu[MAX_NR_DLSCH_PAYLOAD_BYTES];
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@@ -345,7 +344,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
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AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
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const int cid = sched_ctrl->coreset->controlResourceSetId;
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const uint16_t Y = UE_info->Y[UE_id][cid%3][slot];
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const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
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int CCEIndex = find_pdcch_candidate(RC.nrmac[module_id],
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CC_id,
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@@ -408,7 +407,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
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/* mark the corresponding RBs as used */
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for (int rb = 0; rb < sched_pdsch->rbSize; rb++)
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vrb_map[rb + sched_pdsch->rbStart + BWPStart] = ((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex;
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vrb_map[rb + sched_pdsch->rbStart + BWPStart] = SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols);
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if ((frame&127) == 0) LOG_D(MAC,"phytest: %d.%d DL mcs %d, DL rbStart %d, DL rbSize %d\n", frame, slot, sched_pdsch->mcs, rbStart,rbSize);
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}
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@@ -510,7 +509,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
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AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
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const int cid = sched_ctrl->coreset->controlResourceSetId;
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const uint16_t Y = UE_info->Y[UE_id][cid%3][slot];
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const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
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int CCEIndex = find_pdcch_candidate(nr_mac,
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CC_id,
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@@ -306,13 +306,13 @@ int cce_to_reg_interleaving(const int R, int k, int n_shift, const int C, int L,
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return f;
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}
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uint8_t find_pdcch_candidate(gNB_MAC_INST *mac,
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int cc_id,
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int aggregation,
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int nr_of_candidates,
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NR_sched_pdcch_t *pdcch,
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NR_ControlResourceSet_t *coreset,
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uint16_t Y){
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int find_pdcch_candidate(gNB_MAC_INST *mac,
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int cc_id,
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int aggregation,
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int nr_of_candidates,
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NR_sched_pdcch_t *pdcch,
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NR_ControlResourceSet_t *coreset,
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uint16_t Y){
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uint16_t *vrb_map = mac->common_channels[cc_id].vrb_map;
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const int next_cand = mac->pdcch_cand[coreset->controlResourceSetId];
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@@ -332,12 +332,11 @@ uint8_t find_pdcch_candidate(gNB_MAC_INST *mac,
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const int C = R>0 ? N_regs/(L*R) : 0;
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const int B_rb = L/N_symb; // nb of RBs occupied by each REG bundle
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int first_cce;
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bool taken = false; // flag if the resource for a given candidate are taken
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// loop over all the available candidates
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// this implements TS 38.211 Sec. 7.3.2.2
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for(int m=next_cand; m<nr_of_candidates; m++) { // loop over candidates
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first_cce = aggregation * (( Y + CEILIDIV((m*N_cces),(aggregation*nr_of_candidates)) + N_ci ) % CEILIDIV(N_cces,aggregation));
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bool taken = false; // flag if the resource for a given candidate are taken
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int first_cce = aggregation * (( Y + CEILIDIV((m*N_cces),(aggregation*nr_of_candidates)) + N_ci ) % CEILIDIV(N_cces,aggregation));
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for (int j=first_cce; (j<first_cce+aggregation) && !taken; j++) { // loop over CCEs
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for (int k=6*j/L; (k<(6*j/L+6/L)) && !taken; k++) { // loop over REG bundles
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int f = cce_to_reg_interleaving(R, k, pdcch->ShiftIndex, C, L, N_regs);
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@@ -376,14 +375,7 @@ void fill_pdcch_vrb_map(gNB_MAC_INST *mac,
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for (int j=first_cce; j<first_cce+aggregation; j++) { // loop over CCEs
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for (int k=6*j/L; k<(6*j/L+6/L); k++) { // loop over REG bundles
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int f; // interleaving function
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if(R==0)
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f = k;
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else {
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int c = k/R;
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int r = k%R;
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f = (r*C + c + n_shift)%(N_regs/L);
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}
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int f = cce_to_reg_interleaving(R, k, n_shift, C, L, N_regs);
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for(int rb=0; rb<B_rb; rb++) // loop over the RBs of the bundle
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vrb_map[pdcch->BWPStart + f*B_rb + rb] |= SL_to_bitmap(pdcch->StartSymbolIndex, N_symb);
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}
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@@ -1963,19 +1955,18 @@ int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP)
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return -1;
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}
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||||
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||||
void set_Y(int Y[3][160], rnti_t rnti) {
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uint16_t get_Y(int cid, int slot, rnti_t rnti) {
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const int A[3] = {39827, 39829, 39839};
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const int D = 65537;
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int Y;
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Y[0][0] = (A[0] * rnti) % D;
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Y[1][0] = (A[1] * rnti) % D;
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Y[2][0] = (A[2] * rnti) % D;
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Y = (A[cid] * rnti) % D;
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||||
|
||||
for (int s = 1; s < 160; s++) {
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Y[0][s] = (A[0] * Y[0][s - 1]) % D;
|
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Y[1][s] = (A[1] * Y[1][s - 1]) % D;
|
||||
Y[2][s] = (A[2] * Y[2][s - 1]) % D;
|
||||
}
|
||||
for (int s = 0; s < slot; s++)
|
||||
Y = (A[cid] * Y) % D;
|
||||
|
||||
return Y;
|
||||
}
|
||||
|
||||
int find_nr_RA_id(module_id_t mod_idP, int CC_idP, rnti_t rntiP) {
|
||||
@@ -2059,8 +2050,7 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP, NR_CellGroupConfig_t *CellG
|
||||
UE_info->CellGroup[UE_id] = CellGroup;
|
||||
add_nr_list(&UE_info->list, UE_id);
|
||||
memset(&UE_info->mac_stats[UE_id], 0, sizeof(NR_mac_stats_t));
|
||||
set_Y(UE_info->Y[UE_id], rntiP);
|
||||
if (CellGroup && CellGroup->spCellConfig && CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated)
|
||||
if (CellGroup && CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated)
|
||||
compute_csi_bitlen (CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup, UE_info, UE_id, mod_idP);
|
||||
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
|
||||
memset(sched_ctrl, 0, sizeof(*sched_ctrl));
|
||||
|
||||
@@ -142,7 +142,6 @@ void nr_schedule_pucch(int Mod_idP,
|
||||
|
||||
for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
|
||||
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
|
||||
if (sched_ctrl->ul_failure==1 && get_softmodem_params()->phy_test==0) continue;
|
||||
const int n = sizeof(sched_ctrl->sched_pucch) / sizeof(*sched_ctrl->sched_pucch);
|
||||
for (int i = 0; i < n; i++) {
|
||||
NR_sched_pucch_t *curr_pucch = &UE_info->UE_sched_ctrl[UE_id].sched_pucch[i];
|
||||
@@ -1123,7 +1122,7 @@ void handle_nr_uci_pucch_0_1(module_id_t mod_id,
|
||||
|
||||
// tpc (power control) only if we received AckNack or positive SR. For a
|
||||
// negative SR, the UE won't have sent anything, and the SNR is not valid
|
||||
if (((uci_01->pduBitmap >> 1) & 0x1) || sched_ctrl->SR) {
|
||||
if (((uci_01->pduBitmap >> 1) & 0x1) ) {
|
||||
if ((uci_01->harq) && (uci_01->harq->harq_confidence_level==0)) sched_ctrl->tpc1 = nr_get_tpc(RC.nrmac[mod_id]->pucch_target_snrx10, uci_01->ul_cqi, 30);
|
||||
else sched_ctrl->tpc1 = 3;
|
||||
sched_ctrl->pucch_snrx10 = uci_01->ul_cqi * 5 - 640;
|
||||
|
||||
@@ -711,7 +711,8 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
|
||||
UE_info->mac_stats[UE_id].ulsch_DTX++;
|
||||
}
|
||||
if (UE_info->UE_sched_ctrl[UE_id].pusch_consecutive_dtx_cnt >= pusch_failure_thres) {
|
||||
LOG_D(NR_MAC,"Detected UL Failure on PUSCH, stopping scheduling\n");
|
||||
LOG_W(NR_MAC,"Detected UL Failure on PUSCH after %d PUSCH DTX, stopping scheduling\n",
|
||||
UE_info->UE_sched_ctrl[UE_id].pusch_consecutive_dtx_cnt);
|
||||
UE_info->UE_sched_ctrl[UE_id].ul_failure = 1;
|
||||
nr_mac_gNB_rrc_ul_failure(gnb_mod_idP,CC_idP,frameP,slotP,rntiP);
|
||||
}
|
||||
@@ -910,13 +911,22 @@ bool nr_UE_is_to_be_scheduled(module_id_t mod_id, int CC_id, int UE_id, frame_t
|
||||
const NR_UE_sched_ctrl_t *sched_ctrl = &nrmac->UE_info.UE_sched_ctrl[UE_id];
|
||||
const int last_ul_sched = sched_ctrl->last_ul_frame * n + sched_ctrl->last_ul_slot;
|
||||
|
||||
const NR_TDD_UL_DL_Pattern_t *tdd =
|
||||
scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
|
||||
int num_slots_per_period;
|
||||
int tdd_period_len[8] = {500,625,1000,1250,2000,2500,5000,10000};
|
||||
if (tdd)
|
||||
num_slots_per_period = n*tdd_period_len[tdd->dl_UL_TransmissionPeriodicity]/10000;
|
||||
else
|
||||
num_slots_per_period = n;
|
||||
|
||||
const int diff = (now - last_ul_sched + 1024 * n) % (1024 * n);
|
||||
/* UE is to be scheduled if
|
||||
* (1) we think the UE has more bytes awaiting than what we scheduled
|
||||
* (2) there is a scheduling request
|
||||
* (3) or we did not schedule it in more than 10 frames */
|
||||
const bool has_data = sched_ctrl->estimated_ul_buffer > sched_ctrl->sched_ul_bytes;
|
||||
const bool high_inactivity = diff >= nrmac->ulsch_max_frame_inactivity * n;
|
||||
const bool high_inactivity = diff >= (nrmac->ulsch_max_frame_inactivity>0 ? (nrmac->ulsch_max_frame_inactivity * n) : num_slots_per_period);
|
||||
LOG_D(NR_MAC,
|
||||
"%4d.%2d UL inactivity %d slots has_data %d SR %d\n",
|
||||
frame,
|
||||
@@ -1017,7 +1027,7 @@ bool allocate_ul_retransmission(module_id_t module_id,
|
||||
|
||||
/* Find a free CCE */
|
||||
const int cid = sched_ctrl->coreset->controlResourceSetId;
|
||||
const uint16_t Y = RC.nrmac[module_id]->UE_info.Y[UE_id][cid%3][slot];
|
||||
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
|
||||
uint8_t nr_of_candidates;
|
||||
for (int i=0; i<5; i++) {
|
||||
// for now taking the lowest value among the available aggregation levels
|
||||
@@ -1163,7 +1173,7 @@ void pf_ul(module_id_t module_id,
|
||||
/* if no data, pre-allocate 5RB */
|
||||
/* Find a free CCE */
|
||||
const int cid = sched_ctrl->coreset->controlResourceSetId;
|
||||
const uint16_t Y = RC.nrmac[module_id]->UE_info.Y[UE_id][cid%3][slot];
|
||||
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
|
||||
uint8_t nr_of_candidates;
|
||||
for (int i=0; i<5; i++) {
|
||||
// for now taking the lowest value among the available aggregation levels
|
||||
@@ -1276,7 +1286,7 @@ void pf_ul(module_id_t module_id,
|
||||
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
|
||||
|
||||
const int cid = sched_ctrl->coreset->controlResourceSetId;
|
||||
const uint16_t Y = RC.nrmac[module_id]->UE_info.Y[UE_id][cid%3][slot];
|
||||
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
|
||||
uint8_t nr_of_candidates;
|
||||
for (int i=0; i<5; i++) {
|
||||
// for now taking the lowest value among the available aggregation levels
|
||||
@@ -1522,6 +1532,11 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
|
||||
nfapi_nr_ul_dci_request_t *ul_dci_req = &RC.nrmac[module_id]->UL_dci_req[CC_id];
|
||||
ul_dci_req->SFN = frame;
|
||||
ul_dci_req->Slot = slot;
|
||||
/* a PDCCH PDU groups DCIs per BWP and CORESET. Save a pointer to each
|
||||
* allocated PDCCH so we can easily allocate UE's DCIs independent of any
|
||||
* CORESET order */
|
||||
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_coreset[MAX_NUM_CORESET] = {0};
|
||||
|
||||
|
||||
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon;
|
||||
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
|
||||
@@ -1760,7 +1775,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
|
||||
NR_SearchSpace_t *ss = (sched_ctrl->active_bwp || ubwpd) ? sched_ctrl->search_space: RC.nrmac[module_id]->sched_ctrlCommon->search_space;
|
||||
NR_ControlResourceSet_t *coreset = (sched_ctrl->active_bwp || ubwpd) ? sched_ctrl->coreset: RC.nrmac[module_id]->sched_ctrlCommon->coreset;
|
||||
const int coresetid = coreset->controlResourceSetId;
|
||||
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = nr_mac->pdcch_pdu_idx[CC_id][coresetid];
|
||||
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = pdcch_pdu_coreset[coresetid];
|
||||
if (!pdcch_pdu) {
|
||||
nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &ul_dci_req->ul_dci_pdu_list[ul_dci_req->numPdus];
|
||||
memset(ul_dci_request_pdu, 0, sizeof(nfapi_nr_ul_dci_request_pdus_t));
|
||||
@@ -1769,7 +1784,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
|
||||
pdcch_pdu = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15;
|
||||
ul_dci_req->numPdus += 1;
|
||||
nr_configure_pdcch(pdcch_pdu, coreset, genericParameters, &sched_ctrl->sched_pdcch);
|
||||
nr_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu;
|
||||
pdcch_pdu_coreset[coresetid] = pdcch_pdu;
|
||||
}
|
||||
|
||||
LOG_D(NR_MAC,"Configuring ULDCI/PDCCH in %d.%d at CCE %d, rnti %x\n", frame,slot,sched_ctrl->cce_index,rnti);
|
||||
|
||||
@@ -260,13 +260,13 @@ NR_sched_pdcch_t set_pdcch_structure(gNB_MAC_INST *gNB_mac,
|
||||
NR_BWP_t *bwp,
|
||||
NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config);
|
||||
|
||||
uint8_t find_pdcch_candidate(gNB_MAC_INST *mac,
|
||||
int cc_id,
|
||||
int aggregation,
|
||||
int nr_of_candidates,
|
||||
NR_sched_pdcch_t *pdcch,
|
||||
NR_ControlResourceSet_t *coreset,
|
||||
uint16_t Y);
|
||||
int find_pdcch_candidate(gNB_MAC_INST *mac,
|
||||
int cc_id,
|
||||
int aggregation,
|
||||
int nr_of_candidates,
|
||||
NR_sched_pdcch_t *pdcch,
|
||||
NR_ControlResourceSet_t *coreset,
|
||||
uint16_t Y);
|
||||
|
||||
void fill_pdcch_vrb_map(gNB_MAC_INST *mac,
|
||||
int CC_id,
|
||||
@@ -326,6 +326,8 @@ void nr_set_pusch_semi_static(const NR_ServingCellConfigCommon_t *scc,
|
||||
uint8_t num_dmrs_cdm_grps_no_data,
|
||||
NR_pusch_semi_static_t *ps);
|
||||
|
||||
uint16_t get_Y(int cid, int slot, rnti_t rnti);
|
||||
|
||||
uint8_t nr_get_tpc(int target, uint8_t cqi, int incr);
|
||||
|
||||
int get_spf(nfapi_nr_config_request_scf_t *cfg);
|
||||
|
||||
@@ -128,7 +128,10 @@ void dump_mac_stats(gNB_MAC_INST *gNB, char *output, int strlen, bool reset_rsrp
|
||||
}
|
||||
}
|
||||
}
|
||||
print_meas_log(&gNB->eNB_scheduler, "DL & UL scheduling timing stats", NULL, NULL, output+stroff);
|
||||
print_meas(&gNB->eNB_scheduler, "DL & UL scheduling timing stats", NULL, NULL);
|
||||
print_meas(&gNB->schedule_dlsch,"dlsch scheduler",NULL,NULL);
|
||||
print_meas(&gNB->rlc_data_req, "rlc_data_req",NULL,NULL);
|
||||
print_meas(&gNB->rlc_status_ind,"rlc_status_ind",NULL,NULL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -675,7 +675,6 @@ typedef struct {
|
||||
rnti_t rnti[MAX_MOBILES_PER_GNB];
|
||||
NR_CellGroupConfig_t *CellGroup[MAX_MOBILES_PER_GNB];
|
||||
/// CCE indexing
|
||||
int Y[MAX_MOBILES_PER_GNB][3][160];
|
||||
int m[MAX_MOBILES_PER_GNB];
|
||||
// UE selected beam index
|
||||
uint8_t UE_beam_index[MAX_MOBILES_PER_GNB];
|
||||
@@ -761,6 +760,10 @@ typedef struct gNB_MAC_INST_s {
|
||||
time_stats_t schedule_dlsch_preprocessor;
|
||||
/// processing time of eNB DLSCH scheduler
|
||||
time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor
|
||||
/// processing time of rlc_data_req
|
||||
time_stats_t rlc_data_req;
|
||||
/// processing time of rlc_status_ind
|
||||
time_stats_t rlc_status_ind;
|
||||
/// processing time of eNB MCH scheduler
|
||||
time_stats_t schedule_mch;
|
||||
/// processing time of eNB ULSCH reception
|
||||
|
||||
Reference in New Issue
Block a user