Merge remote-tracking branch 'origin/develop' into NR_UL_VRB_MAP_improv

This commit is contained in:
francescomani
2022-02-08 15:37:39 +01:00
242 changed files with 5499 additions and 5142 deletions
@@ -73,6 +73,8 @@ void fill_ul_config(fapi_nr_ul_config_request_t *ul_config, frame_t frame_tx, in
memset(ul_config->ul_config_list, 0, sizeof(ul_config->ul_config_list));
}
ul_config->ul_config_list[ul_config->number_pdus].pdu_type = pdu_type;
//ul_config->slot = slot_tx;
//ul_config->sfn = frame_tx;
ul_config->slot = slot_tx;
ul_config->sfn = frame_tx;
ul_config->number_pdus++;
@@ -971,6 +973,8 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
uint8_t ulsch_input_buffer_array[NFAPI_MAX_NUM_UL_PDU][MAX_ULSCH_PAYLOAD_BYTES];
nr_scheduled_response_t scheduled_response;
fapi_nr_tx_request_t tx_req;
//tx_req.slot = slot_tx;
//tx_req.sfn = frame_tx;
tx_req.slot = slot_tx;
tx_req.sfn = frame_tx;
tx_req.number_of_pdus = 0;
+5 -1
View File
@@ -55,6 +55,7 @@
#include <errno.h>
#include <string.h>
const uint8_t nr_rv_round_map[4] = { 0, 2, 3, 1 };
uint16_t nr_pdcch_order_table[6] = { 31, 31, 511, 2047, 2047, 8191 };
uint8_t vnf_first_sched_entry = 1;
@@ -272,6 +273,7 @@ bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot) {
void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
frame_t frame,
sub_frame_t slot){
//pthread_mutex_lock(&mutextest);
protocol_ctxt_t ctxt={0};
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frame, slot,module_idP);
@@ -387,7 +389,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
nr_schedule_ulsch(module_idP, frame, slot);
// This schedules the DCI for Downlink and PDSCH
nr_schedule_ue_spec(module_idP, frame, slot);
start_meas(&gNB->schedule_dlsch);
nr_schedule_ue_spec(module_idP, frame, slot);
stop_meas(&gNB->schedule_dlsch);
nr_schedule_pucch(module_idP, frame, slot);
@@ -433,6 +433,7 @@ uint32_t schedule_control_sib1(module_id_t module_id,
void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
nfapi_nr_dl_tti_request_body_t *dl_req,
int pdu_index,
NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config,
uint32_t TBS,
int StartSymbolIndex,
@@ -465,7 +466,7 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
pdsch_pdu_rel15->pduBitmap = 0;
pdsch_pdu_rel15->rnti = SI_RNTI;
pdsch_pdu_rel15->pduIndex = gNB_mac->pdu_index[0]++;
pdsch_pdu_rel15->pduIndex = pdu_index;
pdsch_pdu_rel15->BWPSize = type0_PDCCH_CSS_config->num_rbs;
pdsch_pdu_rel15->BWPStart = type0_PDCCH_CSS_config->cset_start_rb;
@@ -632,7 +633,8 @@ void schedule_nr_sib1(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
candidate_idx, sib1_sdu_length);
nfapi_nr_dl_tti_request_body_t *dl_req = &gNB_mac->DL_req[CC_id].dl_tti_request_body;
nr_fill_nfapi_dl_sib1_pdu(module_idP, dl_req, type0_PDCCH_CSS_config, TBS, startSymbolIndex, nrOfSymbols, dlDmrsSymbPos);
int pdu_index = gNB_mac->pdu_index[0]++;
nr_fill_nfapi_dl_sib1_pdu(module_idP, dl_req, pdu_index, type0_PDCCH_CSS_config, TBS, startSymbolIndex, nrOfSymbols, dlDmrsSymbPos);
const int ntx_req = gNB_mac->TX_req[CC_id].Number_of_PDUs;
nfapi_nr_pdu_t *tx_req = &gNB_mac->TX_req[CC_id].pdu_list[ntx_req];
@@ -642,7 +644,7 @@ void schedule_nr_sib1(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
memcpy(tx_req->TLVs[0].value.direct, sib1_payload, sib1_sdu_length);
tx_req->PDU_length = TBS;
tx_req->PDU_index = gNB_mac->pdu_index[0]++;
tx_req->PDU_index = pdu_index;
tx_req->num_TLV = 1;
tx_req->TLVs[0].length = TBS + 2;
gNB_mac->TX_req[CC_id].Number_of_PDUs++;
@@ -409,7 +409,7 @@ int get_mcs_from_bler(module_id_t mod_id, int CC_id, frame_t frame, sub_frame_t
/*const int dret3x = stats->dlsch_rounds[3] - bler_stats->dlsch_rounds[3];
if (dret3x > 0) {
if there is a third retransmission, decrease MCS for stabilization and
restart averaging window to stabilize transmission
restart averaging window to stabilize transmission
bler_stats->last_frame_slot = now;
bler_stats->mcs = max(9, bler_stats->mcs - 1);
memcpy(bler_stats->dlsch_rounds, stats->dlsch_rounds, sizeof(stats->dlsch_rounds));
@@ -431,7 +431,7 @@ int get_mcs_from_bler(module_id_t mod_id, int CC_id, frame_t frame, sub_frame_t
int new_mcs = old_mcs;
// TODO put back this condition when relevant
/* first ensure that number of 2nd retx is below threshold. If this is the
* case, use 1st retx to adjust faster
* case, use 1st retx to adjust faster
if (bler_stats->rd2_bler > nrmac->dl_rd2_bler_threshold && old_mcs > 6) {
new_mcs -= 2;
} else if (bler_stats->rd2_bler < nrmac->dl_rd2_bler_threshold) {*/
@@ -486,7 +486,8 @@ void nr_store_dlsch_buffer(module_id_t module_id,
DL_SCH_LCID_DCCH,
0,
0);
if ((sched_ctrl->lcid_mask&(1<<4)) > 0)
if ((sched_ctrl->lcid_mask&(1<<4)) > 0) {
start_meas(&RC.nrmac[module_id]->rlc_status_ind);
sched_ctrl->rlc_status[DL_SCH_LCID_DTCH] = mac_rlc_status_ind(module_id,
rnti,
module_id,
@@ -497,16 +498,17 @@ void nr_store_dlsch_buffer(module_id_t module_id,
DL_SCH_LCID_DTCH,
0,
0);
if(sched_ctrl->rlc_status[DL_SCH_LCID_DCCH].bytes_in_buffer > 0){
lcid = DL_SCH_LCID_DCCH;
}
else if (sched_ctrl->rlc_status[DL_SCH_LCID_DCCH1].bytes_in_buffer > 0)
{
lcid = DL_SCH_LCID_DCCH1;
}else{
lcid = DL_SCH_LCID_DTCH;
}
stop_meas(&RC.nrmac[module_id]->rlc_status_ind);
}
if(sched_ctrl->rlc_status[DL_SCH_LCID_DCCH].bytes_in_buffer > 0){
lcid = DL_SCH_LCID_DCCH;
}
else if (sched_ctrl->rlc_status[DL_SCH_LCID_DCCH1].bytes_in_buffer > 0)
{
lcid = DL_SCH_LCID_DCCH1;
}else{
lcid = DL_SCH_LCID_DTCH;
}
sched_ctrl->num_total_bytes += sched_ctrl->rlc_status[lcid].bytes_in_buffer;
//later multiplex here. Just select DCCH/SRB before DTCH/DRB
@@ -584,10 +586,10 @@ bool allocate_dl_retransmission(module_id_t module_id,
temp_ps.nrOfLayers = 1;
nr_set_pdsch_semi_static(scc, cg, sched_ctrl->active_bwp, bwpd, tda, f, &temp_ps);
while (rbStart < bwpSize &&
!(rballoc_mask[rbStart]&SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols)))
!(rballoc_mask[rbStart]&SL_to_bitmap(temp_ps.startSymbolIndex, temp_ps.nrOfSymbols)))
rbStart++;
while (rbStart + rbSize < bwpSize &&
(rballoc_mask[rbStart + rbSize]&SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols)))
(rballoc_mask[rbStart + rbSize]&SL_to_bitmap(temp_ps.startSymbolIndex, temp_ps.nrOfSymbols)))
rbSize++;
uint32_t new_tbs;
uint16_t new_rbSize;
@@ -613,7 +615,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
/* Find a free CCE */
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = RC.nrmac[module_id]->UE_info.Y[UE_id][cid%3][slot];
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
uint8_t nr_of_candidates;
for (int i=0; i<5; i++) {
// for now taking the lowest value among the available aggregation levels
@@ -775,7 +777,7 @@ void pf_dl(module_id_t module_id,
/* Find a free CCE */
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = RC.nrmac[module_id]->UE_info.Y[UE_id][cid%3][slot];
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
uint8_t nr_of_candidates;
for (int i=0; i<5; i++) {
// for now taking the lowest value among the available aggregation levels
@@ -1163,6 +1165,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
pdsch_pdu->pduBitmap |= 0x1; // Bit 0: pdschPtrs - Indicates PTRS included (FR2)
}
LOG_D(NR_MAC,"Configuring DCI/PDCCH in %d.%d at CCE %d, rnti %x\n", frame,slot,sched_ctrl->cce_index,rnti);
/* Fill PDCCH DL DCI PDU */
nfapi_nr_dl_dci_pdu_t *dci_pdu = &pdcch_pdu->dci_pdu[pdcch_pdu->numDlDci];
pdcch_pdu->numDlDci++;
@@ -1295,6 +1298,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
// const int lcid = DL_SCH_LCID_DTCH;
const int lcid = sched_ctrl->lcid_to_schedule;
int dlsch_total_bytes = 0;
start_meas(&gNB_mac->rlc_data_req);
if (sched_ctrl->num_total_bytes > 0) {
tbs_size_t len = 0;
while (size > 3) {
@@ -1308,6 +1312,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
/* limit requested number of bytes to what preprocessor specified, or
* such that TBS is full */
const rlc_buffer_occupancy_t ndata = min(sched_ctrl->rlc_status[lcid].bytes_in_buffer, size);
len = mac_rlc_data_req(module_id,
rnti,
module_id,
@@ -1368,6 +1373,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
buf += size;
dlsch_total_bytes += size;
}
stop_meas(&gNB_mac->rlc_data_req);
// Add padding header and zero rest out if there is space left
if (size > 0) {
@@ -53,7 +53,6 @@
//#define UL_HARQ_PRINT
extern RAN_CONTEXT_t RC;
const uint8_t nr_rv_round_map[4] = {0, 2, 3, 1};
//#define ENABLE_MAC_PAYLOAD_DEBUG 1
//uint8_t mac_pdu[MAX_NR_DLSCH_PAYLOAD_BYTES];
@@ -345,7 +344,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = UE_info->Y[UE_id][cid%3][slot];
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
int CCEIndex = find_pdcch_candidate(RC.nrmac[module_id],
CC_id,
@@ -408,7 +407,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
/* mark the corresponding RBs as used */
for (int rb = 0; rb < sched_pdsch->rbSize; rb++)
vrb_map[rb + sched_pdsch->rbStart + BWPStart] = ((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex;
vrb_map[rb + sched_pdsch->rbStart + BWPStart] = SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols);
if ((frame&127) == 0) LOG_D(MAC,"phytest: %d.%d DL mcs %d, DL rbStart %d, DL rbSize %d\n", frame, slot, sched_pdsch->mcs, rbStart,rbSize);
}
@@ -510,7 +509,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = UE_info->Y[UE_id][cid%3][slot];
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
int CCEIndex = find_pdcch_candidate(nr_mac,
CC_id,
@@ -306,13 +306,13 @@ int cce_to_reg_interleaving(const int R, int k, int n_shift, const int C, int L,
return f;
}
uint8_t find_pdcch_candidate(gNB_MAC_INST *mac,
int cc_id,
int aggregation,
int nr_of_candidates,
NR_sched_pdcch_t *pdcch,
NR_ControlResourceSet_t *coreset,
uint16_t Y){
int find_pdcch_candidate(gNB_MAC_INST *mac,
int cc_id,
int aggregation,
int nr_of_candidates,
NR_sched_pdcch_t *pdcch,
NR_ControlResourceSet_t *coreset,
uint16_t Y){
uint16_t *vrb_map = mac->common_channels[cc_id].vrb_map;
const int next_cand = mac->pdcch_cand[coreset->controlResourceSetId];
@@ -332,12 +332,11 @@ uint8_t find_pdcch_candidate(gNB_MAC_INST *mac,
const int C = R>0 ? N_regs/(L*R) : 0;
const int B_rb = L/N_symb; // nb of RBs occupied by each REG bundle
int first_cce;
bool taken = false; // flag if the resource for a given candidate are taken
// loop over all the available candidates
// this implements TS 38.211 Sec. 7.3.2.2
for(int m=next_cand; m<nr_of_candidates; m++) { // loop over candidates
first_cce = aggregation * (( Y + CEILIDIV((m*N_cces),(aggregation*nr_of_candidates)) + N_ci ) % CEILIDIV(N_cces,aggregation));
bool taken = false; // flag if the resource for a given candidate are taken
int first_cce = aggregation * (( Y + CEILIDIV((m*N_cces),(aggregation*nr_of_candidates)) + N_ci ) % CEILIDIV(N_cces,aggregation));
for (int j=first_cce; (j<first_cce+aggregation) && !taken; j++) { // loop over CCEs
for (int k=6*j/L; (k<(6*j/L+6/L)) && !taken; k++) { // loop over REG bundles
int f = cce_to_reg_interleaving(R, k, pdcch->ShiftIndex, C, L, N_regs);
@@ -376,14 +375,7 @@ void fill_pdcch_vrb_map(gNB_MAC_INST *mac,
for (int j=first_cce; j<first_cce+aggregation; j++) { // loop over CCEs
for (int k=6*j/L; k<(6*j/L+6/L); k++) { // loop over REG bundles
int f; // interleaving function
if(R==0)
f = k;
else {
int c = k/R;
int r = k%R;
f = (r*C + c + n_shift)%(N_regs/L);
}
int f = cce_to_reg_interleaving(R, k, n_shift, C, L, N_regs);
for(int rb=0; rb<B_rb; rb++) // loop over the RBs of the bundle
vrb_map[pdcch->BWPStart + f*B_rb + rb] |= SL_to_bitmap(pdcch->StartSymbolIndex, N_symb);
}
@@ -1963,19 +1955,18 @@ int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP)
return -1;
}
void set_Y(int Y[3][160], rnti_t rnti) {
uint16_t get_Y(int cid, int slot, rnti_t rnti) {
const int A[3] = {39827, 39829, 39839};
const int D = 65537;
int Y;
Y[0][0] = (A[0] * rnti) % D;
Y[1][0] = (A[1] * rnti) % D;
Y[2][0] = (A[2] * rnti) % D;
Y = (A[cid] * rnti) % D;
for (int s = 1; s < 160; s++) {
Y[0][s] = (A[0] * Y[0][s - 1]) % D;
Y[1][s] = (A[1] * Y[1][s - 1]) % D;
Y[2][s] = (A[2] * Y[2][s - 1]) % D;
}
for (int s = 0; s < slot; s++)
Y = (A[cid] * Y) % D;
return Y;
}
int find_nr_RA_id(module_id_t mod_idP, int CC_idP, rnti_t rntiP) {
@@ -2059,8 +2050,7 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP, NR_CellGroupConfig_t *CellG
UE_info->CellGroup[UE_id] = CellGroup;
add_nr_list(&UE_info->list, UE_id);
memset(&UE_info->mac_stats[UE_id], 0, sizeof(NR_mac_stats_t));
set_Y(UE_info->Y[UE_id], rntiP);
if (CellGroup && CellGroup->spCellConfig && CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated)
if (CellGroup && CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated)
compute_csi_bitlen (CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup, UE_info, UE_id, mod_idP);
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
memset(sched_ctrl, 0, sizeof(*sched_ctrl));
@@ -142,7 +142,6 @@ void nr_schedule_pucch(int Mod_idP,
for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
if (sched_ctrl->ul_failure==1 && get_softmodem_params()->phy_test==0) continue;
const int n = sizeof(sched_ctrl->sched_pucch) / sizeof(*sched_ctrl->sched_pucch);
for (int i = 0; i < n; i++) {
NR_sched_pucch_t *curr_pucch = &UE_info->UE_sched_ctrl[UE_id].sched_pucch[i];
@@ -1123,7 +1122,7 @@ void handle_nr_uci_pucch_0_1(module_id_t mod_id,
// tpc (power control) only if we received AckNack or positive SR. For a
// negative SR, the UE won't have sent anything, and the SNR is not valid
if (((uci_01->pduBitmap >> 1) & 0x1) || sched_ctrl->SR) {
if (((uci_01->pduBitmap >> 1) & 0x1) ) {
if ((uci_01->harq) && (uci_01->harq->harq_confidence_level==0)) sched_ctrl->tpc1 = nr_get_tpc(RC.nrmac[mod_id]->pucch_target_snrx10, uci_01->ul_cqi, 30);
else sched_ctrl->tpc1 = 3;
sched_ctrl->pucch_snrx10 = uci_01->ul_cqi * 5 - 640;
@@ -711,7 +711,8 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
UE_info->mac_stats[UE_id].ulsch_DTX++;
}
if (UE_info->UE_sched_ctrl[UE_id].pusch_consecutive_dtx_cnt >= pusch_failure_thres) {
LOG_D(NR_MAC,"Detected UL Failure on PUSCH, stopping scheduling\n");
LOG_W(NR_MAC,"Detected UL Failure on PUSCH after %d PUSCH DTX, stopping scheduling\n",
UE_info->UE_sched_ctrl[UE_id].pusch_consecutive_dtx_cnt);
UE_info->UE_sched_ctrl[UE_id].ul_failure = 1;
nr_mac_gNB_rrc_ul_failure(gnb_mod_idP,CC_idP,frameP,slotP,rntiP);
}
@@ -910,13 +911,22 @@ bool nr_UE_is_to_be_scheduled(module_id_t mod_id, int CC_id, int UE_id, frame_t
const NR_UE_sched_ctrl_t *sched_ctrl = &nrmac->UE_info.UE_sched_ctrl[UE_id];
const int last_ul_sched = sched_ctrl->last_ul_frame * n + sched_ctrl->last_ul_slot;
const NR_TDD_UL_DL_Pattern_t *tdd =
scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
int num_slots_per_period;
int tdd_period_len[8] = {500,625,1000,1250,2000,2500,5000,10000};
if (tdd)
num_slots_per_period = n*tdd_period_len[tdd->dl_UL_TransmissionPeriodicity]/10000;
else
num_slots_per_period = n;
const int diff = (now - last_ul_sched + 1024 * n) % (1024 * n);
/* UE is to be scheduled if
* (1) we think the UE has more bytes awaiting than what we scheduled
* (2) there is a scheduling request
* (3) or we did not schedule it in more than 10 frames */
const bool has_data = sched_ctrl->estimated_ul_buffer > sched_ctrl->sched_ul_bytes;
const bool high_inactivity = diff >= nrmac->ulsch_max_frame_inactivity * n;
const bool high_inactivity = diff >= (nrmac->ulsch_max_frame_inactivity>0 ? (nrmac->ulsch_max_frame_inactivity * n) : num_slots_per_period);
LOG_D(NR_MAC,
"%4d.%2d UL inactivity %d slots has_data %d SR %d\n",
frame,
@@ -1017,7 +1027,7 @@ bool allocate_ul_retransmission(module_id_t module_id,
/* Find a free CCE */
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = RC.nrmac[module_id]->UE_info.Y[UE_id][cid%3][slot];
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
uint8_t nr_of_candidates;
for (int i=0; i<5; i++) {
// for now taking the lowest value among the available aggregation levels
@@ -1163,7 +1173,7 @@ void pf_ul(module_id_t module_id,
/* if no data, pre-allocate 5RB */
/* Find a free CCE */
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = RC.nrmac[module_id]->UE_info.Y[UE_id][cid%3][slot];
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
uint8_t nr_of_candidates;
for (int i=0; i<5; i++) {
// for now taking the lowest value among the available aggregation levels
@@ -1276,7 +1286,7 @@ void pf_ul(module_id_t module_id,
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = RC.nrmac[module_id]->UE_info.Y[UE_id][cid%3][slot];
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
uint8_t nr_of_candidates;
for (int i=0; i<5; i++) {
// for now taking the lowest value among the available aggregation levels
@@ -1522,6 +1532,11 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
nfapi_nr_ul_dci_request_t *ul_dci_req = &RC.nrmac[module_id]->UL_dci_req[CC_id];
ul_dci_req->SFN = frame;
ul_dci_req->Slot = slot;
/* a PDCCH PDU groups DCIs per BWP and CORESET. Save a pointer to each
* allocated PDCCH so we can easily allocate UE's DCIs independent of any
* CORESET order */
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_coreset[MAX_NUM_CORESET] = {0};
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon;
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
@@ -1760,7 +1775,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
NR_SearchSpace_t *ss = (sched_ctrl->active_bwp || ubwpd) ? sched_ctrl->search_space: RC.nrmac[module_id]->sched_ctrlCommon->search_space;
NR_ControlResourceSet_t *coreset = (sched_ctrl->active_bwp || ubwpd) ? sched_ctrl->coreset: RC.nrmac[module_id]->sched_ctrlCommon->coreset;
const int coresetid = coreset->controlResourceSetId;
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = nr_mac->pdcch_pdu_idx[CC_id][coresetid];
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = pdcch_pdu_coreset[coresetid];
if (!pdcch_pdu) {
nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &ul_dci_req->ul_dci_pdu_list[ul_dci_req->numPdus];
memset(ul_dci_request_pdu, 0, sizeof(nfapi_nr_ul_dci_request_pdus_t));
@@ -1769,7 +1784,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
pdcch_pdu = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15;
ul_dci_req->numPdus += 1;
nr_configure_pdcch(pdcch_pdu, coreset, genericParameters, &sched_ctrl->sched_pdcch);
nr_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu;
pdcch_pdu_coreset[coresetid] = pdcch_pdu;
}
LOG_D(NR_MAC,"Configuring ULDCI/PDCCH in %d.%d at CCE %d, rnti %x\n", frame,slot,sched_ctrl->cce_index,rnti);
+9 -7
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@@ -260,13 +260,13 @@ NR_sched_pdcch_t set_pdcch_structure(gNB_MAC_INST *gNB_mac,
NR_BWP_t *bwp,
NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config);
uint8_t find_pdcch_candidate(gNB_MAC_INST *mac,
int cc_id,
int aggregation,
int nr_of_candidates,
NR_sched_pdcch_t *pdcch,
NR_ControlResourceSet_t *coreset,
uint16_t Y);
int find_pdcch_candidate(gNB_MAC_INST *mac,
int cc_id,
int aggregation,
int nr_of_candidates,
NR_sched_pdcch_t *pdcch,
NR_ControlResourceSet_t *coreset,
uint16_t Y);
void fill_pdcch_vrb_map(gNB_MAC_INST *mac,
int CC_id,
@@ -326,6 +326,8 @@ void nr_set_pusch_semi_static(const NR_ServingCellConfigCommon_t *scc,
uint8_t num_dmrs_cdm_grps_no_data,
NR_pusch_semi_static_t *ps);
uint16_t get_Y(int cid, int slot, rnti_t rnti);
uint8_t nr_get_tpc(int target, uint8_t cqi, int incr);
int get_spf(nfapi_nr_config_request_scf_t *cfg);
+4 -1
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@@ -128,7 +128,10 @@ void dump_mac_stats(gNB_MAC_INST *gNB, char *output, int strlen, bool reset_rsrp
}
}
}
print_meas_log(&gNB->eNB_scheduler, "DL & UL scheduling timing stats", NULL, NULL, output+stroff);
print_meas(&gNB->eNB_scheduler, "DL & UL scheduling timing stats", NULL, NULL);
print_meas(&gNB->schedule_dlsch,"dlsch scheduler",NULL,NULL);
print_meas(&gNB->rlc_data_req, "rlc_data_req",NULL,NULL);
print_meas(&gNB->rlc_status_ind,"rlc_status_ind",NULL,NULL);
}
+4 -1
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@@ -675,7 +675,6 @@ typedef struct {
rnti_t rnti[MAX_MOBILES_PER_GNB];
NR_CellGroupConfig_t *CellGroup[MAX_MOBILES_PER_GNB];
/// CCE indexing
int Y[MAX_MOBILES_PER_GNB][3][160];
int m[MAX_MOBILES_PER_GNB];
// UE selected beam index
uint8_t UE_beam_index[MAX_MOBILES_PER_GNB];
@@ -761,6 +760,10 @@ typedef struct gNB_MAC_INST_s {
time_stats_t schedule_dlsch_preprocessor;
/// processing time of eNB DLSCH scheduler
time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor
/// processing time of rlc_data_req
time_stats_t rlc_data_req;
/// processing time of rlc_status_ind
time_stats_t rlc_status_ind;
/// processing time of eNB MCH scheduler
time_stats_t schedule_mch;
/// processing time of eNB ULSCH reception