debugging for MPDCCH
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@@ -210,6 +210,7 @@ uint8_t *generate_dci0(uint8_t *dci,
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uint8_t *e,
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uint8_t *e,
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uint8_t DCI_LENGTH,
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uint8_t DCI_LENGTH,
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uint8_t aggregation_level,
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uint8_t aggregation_level,
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uint8_r bitsperCCE,
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uint16_t rnti)
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uint16_t rnti)
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{
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{
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@@ -230,7 +231,7 @@ uint8_t *generate_dci0(uint8_t *dci,
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"generate_dci FATAL, illegal aggregation_level %d\n",aggregation_level);
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"generate_dci FATAL, illegal aggregation_level %d\n",aggregation_level);
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coded_bits = 72 * aggregation_level;
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coded_bits = bitsperCCE * aggregation_level;
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/*
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/*
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@@ -2293,6 +2294,7 @@ uint8_t generate_dci_top(uint8_t num_pdcch_symbols,
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e+(72*dci_alloc[i].firstCCE),
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e+(72*dci_alloc[i].firstCCE),
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dci_alloc[i].dci_length,
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dci_alloc[i].dci_length,
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dci_alloc[i].L,
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dci_alloc[i].L,
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72,
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dci_alloc[i].rnti);
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dci_alloc[i].rnti);
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}
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}
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}
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}
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@@ -96,16 +96,18 @@ void mpdcch_scrambling(LTE_DL_FRAME_PARMS *frame_parms,
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}
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}
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}
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}
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// this table is the allocation of modulated MPDCCH format 5 symbols to REs
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// this table is the allocation of modulated MPDCCH format 5 symbols to REs, antenna ports 107,108
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// There are in total 36 REs/ECCE * 4 ECCE/PRB_pair = 144 REs in total/PRB_pair, total is 168 REs => 24 REs for DMRS
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// start symbol is symbol 1 and L'=24 => all 6 PRBs in the set
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// For format 5 there are 6 PRB pairs => 864 REs for 24 total ECCE
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// 9 symbols without DMRS = 9*12*6 REs = 648 REs
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static uint16_t mpdcch5tab[864];
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// 4 symbols with DMRS (3 REs stolen per symbol = 4*9*6 REs = 216 REs
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// Total = 648+216 = 864 REs = 1728 bits
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static uint16_t mpdcch5ss1tab[864];
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void init_mpdcch5tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) {
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void init_mpdcch5ss1p107108tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) {
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int l,k,kmod,re;
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int l,k,kmod,re;
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LOG_I(PHY,"Inititalizing mpdcch5tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n");
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LOG_I(PHY,"Inititalizing mpdcch5tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n");
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for (l=0,re=0;l<14;l++) {
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for (l=1,re=0;l<14;l++) {
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for (k=0;k<72;k++){
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for (k=0;k<72;k++){
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kmod = k % 12;
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kmod = k % 12;
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if (((l!=5) && (l!=6) && (l!=12) && (l!=13)) ||
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if (((l!=5) && (l!=6) && (l!=12) && (l!=13)) ||
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@@ -116,9 +118,74 @@ void init_mpdcch5tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) {
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AssertFatal(re==864,"RE count not equal to 864\n");
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AssertFatal(re==864,"RE count not equal to 864\n");
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}
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}
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// this table is the allocation of modulated MPDCCH format 5 symbols to REs, antenna ports 107,108
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// start symbol is symbol 2 and L'=24 => all 6 PRBs in the set
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// 8 symbols without DMRS = 9*12*6 REs = 576 REs
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// 4 symbols with DMRS (3 REs stolen per symbol = 4*9*6 REs = 216 REs
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// Total = 576+216 = 792 REs = 1584 bits
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static uint16_t mpdcch5ss2tab[864];
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void init_mpdcch5ss2p107108tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) {
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int l,k,kmod,re;
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LOG_I(PHY,"Inititalizing mpdcch5tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n");
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for (l=2,re=0;l<14;l++) {
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for (k=0;k<72;k++){
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kmod = k % 12;
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if (((l!=5) && (l!=6) && (l!=12) && (l!=13)) ||
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(((l==5)||(l==6)||(l==12)||(l==13))&&(kmod!=0)&&(kmod!=5)&&(kmod!=10)))
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mpdcch5tab[re++]=(l*eNB->frame_parms.ofdm_symbol_size)+k;
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}
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}
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}
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// this table is the allocation of modulated MPDCCH format 3 symbols to REs, antenna ports 107,108
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// with start symbol 1, using L'=16 => first 4 PRBs in the set
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// 8 symbols without DMRS = 9*12*4 REs = 432 REs
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// 4 symbols with DMRS (3 REs stolen per symbol = 4*9*4 REs = 144 REs
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// Total = 432+144 = 576 = 16CCE*36RE/CCE
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static uint16_t mpdcch3ss1tab[864];
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void init_mpdcch3ss1tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) {
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int l,k,kmod,re;
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LOG_I(PHY,"Inititalizing mpdcch3ss2tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n");
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for (l=1,re=0;l<14;l++) {
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for (k=0;k<48;k++){
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kmod = k % 12;
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if (((l!=5) && (l!=6) && (l!=12) && (l!=13)) ||
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(((l==5)||(l==6)||(l==12)||(l==13))&&(kmod!=0)&&(kmod!=5)&&(kmod!=10)))
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mpdcch5tab[re++]=(l*eNB->frame_parms.ofdm_symbol_size)+k;
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}
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}
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AssertFatal(re==864,"RE count not equal to 864\n");
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}
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// this table is the allocation of modulated MPDCCH format 2 symbols to REs, antenna ports 107,108
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// with start symbol 1, using L'=8 => last 2 PRBs in the set
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// 8 symbols without DMRS = 9*12*2 REs = 216 REs
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// 4 symbols with DMRS (3 REs stolen per symbol = 4*9*2 REs = 72 REs
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// Total = 216+72 = 288 = 8CCE*36RE/CCE
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static uint16_t mpdcch2ss1tab[864];
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void init_mpdcch2ss1tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) {
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int l,k,kmod,re;
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LOG_I(PHY,"Inititalizing mpdcch3ss2tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n");
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for (l=1,re=0;l<14;l++) {
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for (k=0;k<48;k++){
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kmod = k % 12;
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if (((l!=5) && (l!=6) && (l!=12) && (l!=13)) ||
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(((l==5)||(l==6)||(l==12)||(l==13))&&(kmod!=0)&&(kmod!=5)&&(kmod!=10)))
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mpdcch5tab[re++]=(l*eNB->frame_parms.ofdm_symbol_size)+k;
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}
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}
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AssertFatal(re==864,"RE count not equal to 864\n");
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}
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extern uint8_t *generate_dci0(uint8_t *dci,
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extern uint8_t *generate_dci0(uint8_t *dci,
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uint8_t *e,
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uint8_t *e,
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uint8_t DCI_LENGTH,
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uint8_t DCI_LENGTH,
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uint8_t bitsperCCE,
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uint8_t aggregation_level,
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uint8_t aggregation_level,
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uint16_t rnti);
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uint16_t rnti);
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@@ -130,7 +197,15 @@ void generate_mdci_top(PHY_VARS_eNB *eNB, int frame, int subframe,int16_t amp,in
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LTE_DL_FRAME_PARMS *fp=&eNB->frame_parms;
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LTE_DL_FRAME_PARMS *fp=&eNB->frame_parms;
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int i;
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int i;
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int gain_lin_QPSK;
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int gain_lin_QPSK;
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uint8_t bitsperCCE;
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if (mpdcch->start_symbol == 1)
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bitsperCCE = 72;
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else if (mpdcch->start_symbol == 2)
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bitsperCCE = 66;
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else if (mpdcch->start_symbol == 3)
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bitsperCCE = 60;
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for (i=0;i<mpdcch->num_dci;i++) {
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for (i=0;i<mpdcch->num_dci;i++) {
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mdci = &mpdcch->mdci_alloc[i];
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mdci = &mpdcch->mdci_alloc[i];
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@@ -150,11 +225,12 @@ void generate_mdci_top(PHY_VARS_eNB *eNB, int frame, int subframe,int16_t amp,in
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generate_dci0(mdci->dci_pdu,
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generate_dci0(mdci->dci_pdu,
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mpdcch->e+(72*mdci->firstCCE),
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mpdcch->e+(72*mdci->firstCCE),
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mdci->dci_length,
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mdci->dci_length,
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bitsperCCE,
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mdci->L,
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mdci->L,
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mdci->rnti);
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mdci->rnti);
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coded_bits = 72 * mdci->L;
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coded_bits = bitsperCCE * mdci->L;
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// scrambling
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// scrambling
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uint16_t absSF = (frame*10)+subframe;
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uint16_t absSF = (frame*10)+subframe;
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@@ -166,7 +242,7 @@ void generate_mdci_top(PHY_VARS_eNB *eNB, int frame, int subframe,int16_t amp,in
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mpdcch_scrambling(fp,
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mpdcch_scrambling(fp,
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mdci,
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mdci,
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absSF,
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absSF,
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mpdcch->e+(72*mdci->firstCCE),
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mpdcch->e+(bitsperCCE*mdci->firstCCE),
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coded_bits);
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coded_bits);
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// Modulation for PDCCH
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// Modulation for PDCCH
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@@ -304,20 +304,16 @@ void generate_Msg2(module_id_t module_idP,int CC_idP,frame_t frameP,sub_frame_t
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dl_config_pdu->mpdcch_pdu.mpdcch_pdu_rel13.number_of_tx_antenna_ports = 1;
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dl_config_pdu->mpdcch_pdu.mpdcch_pdu_rel13.number_of_tx_antenna_ports = 1;
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RA_template->msg2_mpdcch_repetition_cnt++;
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RA_template->msg2_mpdcch_repetition_cnt++;
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dl_req->number_pdu++;
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dl_req->number_pdu++;
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RA_template->Msg2_subframe = (RA_template->Msg2_subframe+9)%10;
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} //repetition_count==0 && SF condition met
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} //repetition_count==0 && SF condition met
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if (RA_template->msg2_mpdcch_repetition_cnt>0) { // we're in a stream of repetitions
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if (RA_template->msg2_mpdcch_repetition_cnt>0) { // we're in a stream of repetitions
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LOG_I(MAC,"[eNB %d][RAPROC] Frame %d, Subframe %d : In generate_Msg2, MPDCCH repetition %d\n",
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module_idP,frameP,subframeP,RA_template->msg2_mpdcch_repetition_cnt);
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if (RA_template->msg2_mpdcch_repetition_cnt==reps) { // this is the last mpdcch repetition
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if (RA_template->msg2_mpdcch_repetition_cnt==reps) { // this is the last mpdcch repetition
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if (cc[CC_idP].tdd_Config==NULL) { // FDD case
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if (cc[CC_idP].tdd_Config==NULL) { // FDD case
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// wait 2 subframes for PDSCH transmission
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// wait 2 subframes for PDSCH transmission
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if (subframeP>7) RA_template->Msg2_frame = (frameP+1)&1023;
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if (subframeP>7) RA_template->Msg2_frame = (frameP+1)&1023;
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else RA_template->Msg2_frame = frameP;
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else RA_template->Msg2_frame = frameP;
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RA_template->Msg2_subframe = (subframeP+2)%10; // +2 is the "n+x" from Section 7.1.11 in 36.213
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RA_template->Msg2_subframe = (subframeP+2)%10; // +2 is the "n+x" from Section 7.1.11 in 36.213
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LOG_I(MAC,"[eNB %d][RAPROC] SFN %d.%d : Set Msg2 in %d.%d\n",frameP,subframeP,RA_template->Msg2_frame,RA_template->Msg2_subframe);
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}
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}
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else {
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else {
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AssertFatal(1==0,"TDD case not done yet\n");
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AssertFatal(1==0,"TDD case not done yet\n");
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