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fixes for do-ra mode including moving to sc_info some info non related to a specific BWP

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This commit is contained in:
francescomani
2023-12-12 14:10:10 +01:00
parent 78041a2012
commit e25bec6a89
11 changed files with 89 additions and 81 deletions
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openair2/LAYER2/NR_MAC_COMMON/nr_mac.h
+8 -8
View File
@@ -560,29 +560,22 @@ typedef struct nr_srs_feedback {
typedef struct NR_UE_DL_BWP { typedef struct NR_UE_DL_BWP {
NR_BWP_Id_t bwp_id; NR_BWP_Id_t bwp_id;
int n_dl_bwp;
int scs; int scs;
long *cyclicprefix; long *cyclicprefix;
uint16_t BWPSize; uint16_t BWPSize;
uint16_t BWPStart; uint16_t BWPStart;
uint16_t initial_BWPSize;
uint16_t initial_BWPStart;
NR_PDSCH_TimeDomainResourceAllocationList_t *tdaList_Common; NR_PDSCH_TimeDomainResourceAllocationList_t *tdaList_Common;
NR_PDSCH_Config_t *pdsch_Config; NR_PDSCH_Config_t *pdsch_Config;
uint8_t mcsTableIdx; uint8_t mcsTableIdx;
nr_dci_format_t dci_format; nr_dci_format_t dci_format;
int bw_tbslbrm;
} NR_UE_DL_BWP_t; } NR_UE_DL_BWP_t;
typedef struct NR_UE_UL_BWP { typedef struct NR_UE_UL_BWP {
NR_BWP_Id_t bwp_id; NR_BWP_Id_t bwp_id;
int n_ul_bwp;
int scs; int scs;
long *cyclicprefix; long *cyclicprefix;
uint16_t BWPSize; uint16_t BWPSize;
uint16_t BWPStart; uint16_t BWPStart;
uint16_t initial_BWPSize;
uint16_t initial_BWPStart;
NR_RACH_ConfigCommon_t *rach_ConfigCommon; NR_RACH_ConfigCommon_t *rach_ConfigCommon;
NR_PUSCH_TimeDomainResourceAllocationList_t *tdaList_Common; NR_PUSCH_TimeDomainResourceAllocationList_t *tdaList_Common;
NR_ConfiguredGrantConfig_t *configuredGrantConfig; NR_ConfiguredGrantConfig_t *configuredGrantConfig;
@@ -594,7 +587,6 @@ typedef struct NR_UE_UL_BWP {
long transform_precoding; long transform_precoding;
uint8_t mcs_table; uint8_t mcs_table;
nr_dci_format_t dci_format; nr_dci_format_t dci_format;
int bw_tbslbrm;
int max_fb_time; int max_fb_time;
} NR_UE_UL_BWP_t; } NR_UE_UL_BWP_t;
@@ -613,6 +605,14 @@ typedef struct {
long *maxMIMO_Layers_PUSCH; long *maxMIMO_Layers_PUSCH;
NR_CSI_MeasConfig_t *csi_MeasConfig; NR_CSI_MeasConfig_t *csi_MeasConfig;
NR_CSI_AperiodicTriggerStateList_t *aperiodicTriggerStateList; NR_CSI_AperiodicTriggerStateList_t *aperiodicTriggerStateList;
uint16_t initial_dl_BWPSize;
uint16_t initial_dl_BWPStart;
uint16_t initial_ul_BWPSize;
uint16_t initial_ul_BWPStart;
int n_dl_bwp;
int n_ul_bwp;
int dl_bw_tbslbrm;
int ul_bw_tbslbrm;
} NR_UE_ServingCell_Info_t; } NR_UE_ServingCell_Info_t;
typedef enum { typedef enum {
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
+8 -9
View File
@@ -3286,7 +3286,6 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
uint16_t cset0_bwp_size, uint16_t cset0_bwp_size,
uint16_t alt_size) uint16_t alt_size)
{ {
uint16_t size = 0; uint16_t size = 0;
uint16_t numRBG = 0; uint16_t numRBG = 0;
long rbg_size_config; long rbg_size_config;
@@ -3304,8 +3303,8 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
cset0_bwp_size, cset0_bwp_size,
UL_BWP->BWPSize, UL_BWP->BWPSize,
DL_BWP->BWPSize, DL_BWP->BWPSize,
UL_BWP->initial_BWPSize, sc_info->initial_ul_BWPSize,
DL_BWP->initial_BWPSize); sc_info->initial_dl_BWPSize);
switch(format) { switch(format) {
case NR_UL_DCI_FORMAT_0_0: case NR_UL_DCI_FORMAT_0_0:
@@ -3336,11 +3335,11 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
size += dci_pdu->ul_sul_indicator.nbits; size += dci_pdu->ul_sul_indicator.nbits;
} }
// BWP Indicator // BWP Indicator
if (UL_BWP->n_ul_bwp < 2) if (sc_info->n_ul_bwp < 2)
dci_pdu->bwp_indicator.nbits = UL_BWP->n_ul_bwp; dci_pdu->bwp_indicator.nbits = sc_info->n_ul_bwp;
else else
dci_pdu->bwp_indicator.nbits = 2; dci_pdu->bwp_indicator.nbits = 2;
LOG_D(NR_MAC, "BWP indicator nbits %d, num UL BWPs %d\n", dci_pdu->bwp_indicator.nbits, UL_BWP->n_ul_bwp); LOG_D(NR_MAC, "BWP indicator nbits %d, num UL BWPs %d\n", dci_pdu->bwp_indicator.nbits, sc_info->n_ul_bwp);
size += dci_pdu->bwp_indicator.nbits; size += dci_pdu->bwp_indicator.nbits;
// Freq domain assignment // Freq domain assignment
if (pusch_Config) { if (pusch_Config) {
@@ -3485,8 +3484,8 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
} }
// BWP Indicator // BWP Indicator
if (DL_BWP->n_dl_bwp < 2) if (sc_info->n_dl_bwp < 2)
dci_pdu->bwp_indicator.nbits = DL_BWP->n_dl_bwp; dci_pdu->bwp_indicator.nbits = sc_info->n_dl_bwp;
else else
dci_pdu->bwp_indicator.nbits = 2; dci_pdu->bwp_indicator.nbits = 2;
size += dci_pdu->bwp_indicator.nbits; size += dci_pdu->bwp_indicator.nbits;
@@ -3610,7 +3609,7 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
default: default:
AssertFatal(1==0, "Invalid NR DCI format %d\n", format); AssertFatal(1==0, "Invalid NR DCI format %d\n", format);
} }
LOG_D(NR_MAC, "DCI size: %d\n", size);
return size; return size;
} }
openair2/LAYER2/NR_MAC_UE/config_ue.c
+22 -20
View File
@@ -1517,11 +1517,11 @@ NR_UE_DL_BWP_t *get_dl_bwp_structure(NR_UE_MAC_INST_t *mac,
ASN_SEQUENCE_ADD(&mac->dl_BWPs, bwp); ASN_SEQUENCE_ADD(&mac->dl_BWPs, bwp);
} }
if (!setup) { if (!setup) {
bwp->n_dl_bwp = mac->dl_BWPs.count - 1; mac->sc_info.n_dl_bwp = mac->dl_BWPs.count - 1;
bwp->bw_tbslbrm = 0; mac->sc_info.dl_bw_tbslbrm = 0;
for (int i = 0; i < mac->dl_BWPs.count; i++) { for (int i = 0; i < mac->dl_BWPs.count; i++) {
if (mac->dl_BWPs.array[i]->BWPSize > bwp->bw_tbslbrm) if (mac->dl_BWPs.array[i]->BWPSize > mac->sc_info.dl_bw_tbslbrm)
bwp->bw_tbslbrm = mac->dl_BWPs.array[i]->BWPSize; mac->sc_info.dl_bw_tbslbrm = mac->dl_BWPs.array[i]->BWPSize;
} }
} }
return bwp; return bwp;
@@ -1543,11 +1543,11 @@ NR_UE_UL_BWP_t *get_ul_bwp_structure(NR_UE_MAC_INST_t *mac,
ASN_SEQUENCE_ADD(&mac->ul_BWPs, bwp); ASN_SEQUENCE_ADD(&mac->ul_BWPs, bwp);
} }
if (!setup) { if (!setup) {
bwp->n_ul_bwp = mac->ul_BWPs.count - 1; mac->sc_info.n_ul_bwp = mac->ul_BWPs.count - 1;
bwp->bw_tbslbrm = 0; mac->sc_info.ul_bw_tbslbrm = 0;
for (int i = 0; i < mac->ul_BWPs.count; i++) { for (int i = 0; i < mac->ul_BWPs.count; i++) {
if (mac->ul_BWPs.array[i]->BWPSize > bwp->bw_tbslbrm) if (mac->ul_BWPs.array[i]->BWPSize > mac->sc_info.ul_bw_tbslbrm)
bwp->bw_tbslbrm = mac->ul_BWPs.array[i]->BWPSize; mac->sc_info.ul_bw_tbslbrm = mac->ul_BWPs.array[i]->BWPSize;
} }
} }
return bwp; return bwp;
@@ -1657,8 +1657,8 @@ void configure_common_BWP_dl(NR_UE_MAC_INST_t *mac,
bwp->BWPSize = NRRIV2BW(dl_genericParameters->locationAndBandwidth, MAX_BWP_SIZE); bwp->BWPSize = NRRIV2BW(dl_genericParameters->locationAndBandwidth, MAX_BWP_SIZE);
bwp->BWPStart = NRRIV2PRBOFFSET(dl_genericParameters->locationAndBandwidth, MAX_BWP_SIZE); bwp->BWPStart = NRRIV2PRBOFFSET(dl_genericParameters->locationAndBandwidth, MAX_BWP_SIZE);
if (bwp_id == 0) { if (bwp_id == 0) {
bwp->initial_BWPSize = bwp->BWPSize; mac->sc_info.initial_dl_BWPSize = bwp->BWPSize;
bwp->initial_BWPStart = bwp->BWPStart; mac->sc_info.initial_dl_BWPStart = bwp->BWPStart;
} }
if (dl_common->pdsch_ConfigCommon) { if (dl_common->pdsch_ConfigCommon) {
if (dl_common->pdsch_ConfigCommon->present == if (dl_common->pdsch_ConfigCommon->present ==
@@ -1699,8 +1699,8 @@ void configure_common_BWP_ul(NR_UE_MAC_INST_t *mac,
bwp->BWPSize = NRRIV2BW(ul_genericParameters->locationAndBandwidth, MAX_BWP_SIZE); bwp->BWPSize = NRRIV2BW(ul_genericParameters->locationAndBandwidth, MAX_BWP_SIZE);
bwp->BWPStart = NRRIV2PRBOFFSET(ul_genericParameters->locationAndBandwidth, MAX_BWP_SIZE); bwp->BWPStart = NRRIV2PRBOFFSET(ul_genericParameters->locationAndBandwidth, MAX_BWP_SIZE);
if (bwp_id == 0) { if (bwp_id == 0) {
bwp->initial_BWPSize = bwp->BWPSize; mac->sc_info.initial_ul_BWPSize = bwp->BWPSize;
bwp->initial_BWPStart = bwp->BWPStart; mac->sc_info.initial_ul_BWPStart = bwp->BWPStart;
} }
if (ul_common->rach_ConfigCommon) { if (ul_common->rach_ConfigCommon) {
handleMACsetuprelease(bwp->rach_ConfigCommon, handleMACsetuprelease(bwp->rach_ConfigCommon,
@@ -1793,11 +1793,20 @@ void handle_reconfiguration_with_sync(NR_UE_MAC_INST_t *mac,
AssertFatal(reconfigurationWithSync->rach_ConfigDedicated->present == AssertFatal(reconfigurationWithSync->rach_ConfigDedicated->present ==
NR_ReconfigurationWithSync__rach_ConfigDedicated_PR_uplink, NR_ReconfigurationWithSync__rach_ConfigDedicated_PR_uplink,
"RACH on supplementaryUplink not supported\n"); "RACH on supplementaryUplink not supported\n");
ra->rach_ConfigDedicated = reconfigurationWithSync->rach_ConfigDedicated->choice.uplink; updateMACie(ra->rach_ConfigDedicated,
reconfigurationWithSync->rach_ConfigDedicated->choice.uplink,
NR_RACH_ConfigDedicated_t);
} }
if (reconfigurationWithSync->spCellConfigCommon) { if (reconfigurationWithSync->spCellConfigCommon) {
NR_ServingCellConfigCommon_t *scc = reconfigurationWithSync->spCellConfigCommon; NR_ServingCellConfigCommon_t *scc = reconfigurationWithSync->spCellConfigCommon;
if (scc->physCellId)
mac->physCellId = *scc->physCellId;
mac->dmrs_TypeA_Position = scc->dmrs_TypeA_Position;
updateMACie(mac->tdd_UL_DL_ConfigurationCommon,
scc->tdd_UL_DL_ConfigurationCommon,
NR_TDD_UL_DL_ConfigCommon_t);
config_common_ue(mac, scc, module_id, cc_idP);
if (scc->downlinkConfigCommon) if (scc->downlinkConfigCommon)
configure_common_BWP_dl(mac, configure_common_BWP_dl(mac,
0, // bwp-id 0, // bwp-id
@@ -1806,13 +1815,6 @@ void handle_reconfiguration_with_sync(NR_UE_MAC_INST_t *mac,
configure_common_BWP_ul(mac, configure_common_BWP_ul(mac,
0, // bwp-id 0, // bwp-id
scc->uplinkConfigCommon->initialUplinkBWP); scc->uplinkConfigCommon->initialUplinkBWP);
if (scc->physCellId)
mac->physCellId = *scc->physCellId;
mac->dmrs_TypeA_Position = scc->dmrs_TypeA_Position;
updateMACie(mac->tdd_UL_DL_ConfigurationCommon,
scc->tdd_UL_DL_ConfigurationCommon,
NR_TDD_UL_DL_ConfigCommon_t);
config_common_ue(mac, scc, module_id, cc_idP);
} }
mac->state = UE_NOT_SYNC; mac->state = UE_NOT_SYNC;
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
+5 -5
View File
@@ -616,7 +616,7 @@ static int nr_ue_process_dci_dl_10(module_id_t module_id,
NR_PDSCH_Config_t *pdsch_config = (current_DL_BWP || !mac->get_sib1) ? current_DL_BWP->pdsch_Config : NULL; NR_PDSCH_Config_t *pdsch_config = (current_DL_BWP || !mac->get_sib1) ? current_DL_BWP->pdsch_Config : NULL;
if (dci_ind->ss_type == NR_SearchSpace__searchSpaceType_PR_common) { if (dci_ind->ss_type == NR_SearchSpace__searchSpaceType_PR_common) {
dlsch_pdu->BWPSize = dlsch_pdu->BWPSize =
mac->type0_PDCCH_CSS_config.num_rbs ? mac->type0_PDCCH_CSS_config.num_rbs : current_DL_BWP->initial_BWPSize; mac->type0_PDCCH_CSS_config.num_rbs ? mac->type0_PDCCH_CSS_config.num_rbs : mac->sc_info.initial_dl_BWPSize;
dlsch_pdu->BWPStart = dci_ind->cset_start; dlsch_pdu->BWPStart = dci_ind->cset_start;
} else { } else {
dlsch_pdu->BWPSize = current_DL_BWP->BWPSize; dlsch_pdu->BWPSize = current_DL_BWP->BWPSize;
@@ -737,7 +737,7 @@ static int nr_ue_process_dci_dl_10(module_id_t module_id,
} }
int bw_tbslbrm = current_DL_BWP? int bw_tbslbrm = current_DL_BWP?
current_DL_BWP->bw_tbslbrm : mac->sc_info.dl_bw_tbslbrm :
dlsch_pdu->BWPSize; dlsch_pdu->BWPSize;
dlsch_pdu->tbslbrm = nr_compute_tbslbrm(dlsch_pdu->mcs_table, bw_tbslbrm, 1); dlsch_pdu->tbslbrm = nr_compute_tbslbrm(dlsch_pdu->mcs_table, bw_tbslbrm, 1);
@@ -1168,7 +1168,7 @@ static int nr_ue_process_dci_dl_11(module_id_t module_id,
// TBS_LBRM according to section 5.4.2.1 of 38.212 // TBS_LBRM according to section 5.4.2.1 of 38.212
AssertFatal(sc_info->maxMIMO_Layers_PDSCH != NULL, "Option with max MIMO layers not configured is not supported\n"); AssertFatal(sc_info->maxMIMO_Layers_PDSCH != NULL, "Option with max MIMO layers not configured is not supported\n");
int nl_tbslbrm = *sc_info->maxMIMO_Layers_PDSCH < 4 ? *sc_info->maxMIMO_Layers_PDSCH : 4; int nl_tbslbrm = *sc_info->maxMIMO_Layers_PDSCH < 4 ? *sc_info->maxMIMO_Layers_PDSCH : 4;
dlsch_pdu->tbslbrm = nr_compute_tbslbrm(dlsch_pdu->mcs_table, current_DL_BWP->bw_tbslbrm, nl_tbslbrm); dlsch_pdu->tbslbrm = nr_compute_tbslbrm(dlsch_pdu->mcs_table, sc_info->dl_bw_tbslbrm, nl_tbslbrm);
/*PTRS configuration */ /*PTRS configuration */
dlsch_pdu->pduBitmap = 0; dlsch_pdu->pduBitmap = 0;
if (pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS != NULL) { if (pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS != NULL) {
@@ -2885,8 +2885,8 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
mac->type0_PDCCH_CSS_config.num_rbs, mac->type0_PDCCH_CSS_config.num_rbs,
current_UL_BWP->BWPSize, current_UL_BWP->BWPSize,
current_DL_BWP->BWPSize, current_DL_BWP->BWPSize,
current_UL_BWP->initial_BWPSize, mac->sc_info.initial_dl_BWPSize,
current_DL_BWP->initial_BWPSize); mac->sc_info.initial_dl_BWPSize);
else else
N_RB = mac->type0_PDCCH_CSS_config.num_rbs; N_RB = mac->type0_PDCCH_CSS_config.num_rbs;
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
+3 -3
View File
@@ -445,8 +445,8 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
if (rar_grant) { if (rar_grant) {
// Note: for Msg3 or MsgA PUSCH transmission the N_PRB_oh is always set to 0 // Note: for Msg3 or MsgA PUSCH transmission the N_PRB_oh is always set to 0
int ibwp_start = current_UL_BWP->initial_BWPStart; int ibwp_start = sc_info->initial_ul_BWPStart;
int ibwp_size = current_UL_BWP->initial_BWPSize; int ibwp_size = sc_info->initial_ul_BWPSize;
int abwp_start = current_UL_BWP->BWPStart; int abwp_start = current_UL_BWP->BWPStart;
int abwp_size = current_UL_BWP->BWPSize; int abwp_size = current_UL_BWP->BWPSize;
int scs = current_UL_BWP->scs; int scs = current_UL_BWP->scs;
@@ -669,7 +669,7 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
maxMIMO_Layers = pusch_Config ? pusch_Config->maxRank : NULL; maxMIMO_Layers = pusch_Config ? pusch_Config->maxRank : NULL;
AssertFatal (maxMIMO_Layers != NULL,"Option with max MIMO layers not configured is not supported\n"); AssertFatal (maxMIMO_Layers != NULL,"Option with max MIMO layers not configured is not supported\n");
pusch_config_pdu->tbslbrm = nr_compute_tbslbrm(pusch_config_pdu->mcs_table, pusch_config_pdu->tbslbrm = nr_compute_tbslbrm(pusch_config_pdu->mcs_table,
current_UL_BWP->bw_tbslbrm, sc_info->ul_bw_tbslbrm,
*maxMIMO_Layers); *maxMIMO_Layers);
} else } else
pusch_config_pdu->tbslbrm = 0; pusch_config_pdu->tbslbrm = 0;
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+15 -11
View File
@@ -703,6 +703,7 @@ static void nr_generate_Msg3_retransmission(module_id_t module_idP,
NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
NR_UE_UL_BWP_t *ul_bwp = &ra->UL_BWP; NR_UE_UL_BWP_t *ul_bwp = &ra->UL_BWP;
NR_UE_ServingCell_Info_t *sc_info = &ra->sc_info;
NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = ul_bwp->tdaList_Common; NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = ul_bwp->tdaList_Common;
int mu = ul_bwp->scs; int mu = ul_bwp->scs;
@@ -736,8 +737,8 @@ static void nr_generate_Msg3_retransmission(module_id_t module_idP,
int buffer_index = ul_buffer_index(sched_frame, sched_slot, mu, nr_mac->vrb_map_UL_size); int buffer_index = ul_buffer_index(sched_frame, sched_slot, mu, nr_mac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[buffer_index * MAX_BWP_SIZE]; uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[buffer_index * MAX_BWP_SIZE];
const int BWPSize = ul_bwp->initial_BWPSize; const int BWPSize = sc_info->initial_ul_BWPSize;
const int BWPStart = ul_bwp->initial_BWPStart; const int BWPStart = sc_info->initial_ul_BWPStart;
int rbStart = 0; int rbStart = 0;
for (int i = 0; (i < ra->msg3_nb_rb) && (rbStart <= (BWPSize - ra->msg3_nb_rb)); i++) { for (int i = 0; (i < ra->msg3_nb_rb) && (rbStart <= (BWPSize - ra->msg3_nb_rb)); i++) {
@@ -834,7 +835,7 @@ static void nr_generate_Msg3_retransmission(module_id_t module_idP,
1, // Not toggling NDI in msg3 retransmissions 1, // Not toggling NDI in msg3 retransmissions
ul_bwp); ul_bwp);
fill_dci_pdu_rel15(NULL, // parameter not needed for DCI 0_0 fill_dci_pdu_rel15(sc_info,
&ra->DL_BWP, &ra->DL_BWP,
ul_bwp, ul_bwp,
dci_pdu, dci_pdu,
@@ -882,6 +883,7 @@ static void nr_get_Msg3alloc(module_id_t module_id,
frame_type_t frame_type = mac->common_channels->frame_type; frame_type_t frame_type = mac->common_channels->frame_type;
NR_UE_UL_BWP_t *ul_bwp = &ra->UL_BWP; NR_UE_UL_BWP_t *ul_bwp = &ra->UL_BWP;
NR_UE_ServingCell_Info_t *sc_info = &ra->sc_info;
int mu = ul_bwp->scs; int mu = ul_bwp->scs;
int StartSymbolIndex = 0; int StartSymbolIndex = 0;
@@ -959,8 +961,8 @@ static void nr_get_Msg3alloc(module_id_t module_id,
const int buffer_index = ul_buffer_index(ra->Msg3_frame, ra->Msg3_slot, mu, mac->vrb_map_UL_size); const int buffer_index = ul_buffer_index(ra->Msg3_frame, ra->Msg3_slot, mu, mac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &mac->common_channels[CC_id].vrb_map_UL[buffer_index * MAX_BWP_SIZE]; uint16_t *vrb_map_UL = &mac->common_channels[CC_id].vrb_map_UL[buffer_index * MAX_BWP_SIZE];
int bwpSize = ul_bwp->initial_BWPSize; int bwpSize = sc_info->initial_ul_BWPSize;
int bwpStart = ul_bwp->initial_BWPStart; int bwpStart = sc_info->initial_ul_BWPStart;
if (bwpSize != ul_bwp->BWPSize || bwpStart != ul_bwp->BWPStart) { if (bwpSize != ul_bwp->BWPSize || bwpStart != ul_bwp->BWPStart) {
int act_bwp_start = ul_bwp->BWPStart; int act_bwp_start = ul_bwp->BWPStart;
int act_bwp_size = ul_bwp->BWPSize; int act_bwp_size = ul_bwp->BWPSize;
@@ -1085,6 +1087,7 @@ static void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_f
NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; NR_COMMON_channels_t *cc = &mac->common_channels[CC_id];
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
NR_UE_UL_BWP_t *ul_bwp = &ra->UL_BWP; NR_UE_UL_BWP_t *ul_bwp = &ra->UL_BWP;
NR_UE_ServingCell_Info_t *sc_info = &ra->sc_info;
if (ra->state == RA_IDLE) { if (ra->state == RA_IDLE) {
LOG_W(NR_MAC,"RA is not active for RA %X. skipping msg3 scheduling\n", ra->rnti); LOG_W(NR_MAC,"RA is not active for RA %X. skipping msg3 scheduling\n", ra->rnti);
@@ -1119,7 +1122,7 @@ static void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_f
nfapi_nr_pusch_pdu_t *pusch_pdu = &future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pusch_pdu; nfapi_nr_pusch_pdu_t *pusch_pdu = &future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pusch_pdu;
memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t)); memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t));
const int ibwp_size = ul_bwp->initial_BWPSize; const int ibwp_size = sc_info->initial_ul_BWPSize;
const int fh = (ul_bwp->pusch_Config && ul_bwp->pusch_Config->frequencyHopping) ? 1 : 0; const int fh = (ul_bwp->pusch_Config && ul_bwp->pusch_Config->frequencyHopping) ? 1 : 0;
const int startSymbolAndLength = ul_bwp->tdaList_Common->list.array[ra->Msg3_tda_id]->startSymbolAndLength; const int startSymbolAndLength = ul_bwp->tdaList_Common->list.array[ra->Msg3_tda_id]->startSymbolAndLength;
const int mappingtype = ul_bwp->tdaList_Common->list.array[ra->Msg3_tda_id]->mappingType; const int mappingtype = ul_bwp->tdaList_Common->list.array[ra->Msg3_tda_id]->mappingType;
@@ -1159,6 +1162,7 @@ static void nr_generate_Msg2(module_id_t module_idP,
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
NR_UE_DL_BWP_t *dl_bwp = &ra->DL_BWP; NR_UE_DL_BWP_t *dl_bwp = &ra->DL_BWP;
NR_UE_ServingCell_Info_t *sc_info = &ra->sc_info;
if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) { if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) {
@@ -1174,7 +1178,7 @@ static void nr_generate_Msg2(module_id_t module_idP,
NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config = NULL; NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config = NULL;
if(*ss->controlResourceSetId != 0) { if(*ss->controlResourceSetId != 0) {
BWPStart = dl_bwp->BWPStart; BWPStart = dl_bwp->BWPStart;
BWPSize = dl_bwp->initial_BWPSize; BWPSize = sc_info->initial_dl_BWPSize;
} else { } else {
type0_PDCCH_CSS_config = &nr_mac->type0_PDCCH_CSS_config[ra->beam_id]; type0_PDCCH_CSS_config = &nr_mac->type0_PDCCH_CSS_config[ra->beam_id];
BWPStart = type0_PDCCH_CSS_config->cset_start_rb; BWPStart = type0_PDCCH_CSS_config->cset_start_rb;
@@ -1311,7 +1315,7 @@ static void nr_generate_Msg2(module_id_t module_idP,
} }
pdsch_pdu_rel15->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(mcsTableIdx, pdsch_pdu_rel15->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(mcsTableIdx,
dl_bwp->bw_tbslbrm, sc_info->dl_bw_tbslbrm,
1); 1);
pdsch_pdu_rel15->maintenance_parms_v3.ldpcBaseGraph = get_BG(TBS<<3,R); pdsch_pdu_rel15->maintenance_parms_v3.ldpcBaseGraph = get_BG(TBS<<3,R);
@@ -1360,7 +1364,7 @@ static void nr_generate_Msg2(module_id_t module_idP,
pdcch_pdu_rel15->StartSymbolIndex, pdcch_pdu_rel15->StartSymbolIndex,
pdcch_pdu_rel15->DurationSymbols); pdcch_pdu_rel15->DurationSymbols);
fill_dci_pdu_rel15(NULL, // parameter not needed for DCI 1_0 fill_dci_pdu_rel15(sc_info,
dl_bwp, dl_bwp,
&ra->UL_BWP, &ra->UL_BWP,
&pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci - 1], &pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci - 1],
@@ -1520,7 +1524,7 @@ static void prepare_dl_pdus(gNB_MAC_INST *nr_mac,
nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, pdsch_pdu_rel15->numDmrsCdmGrpsNoData, tb_scaling); nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, pdsch_pdu_rel15->numDmrsCdmGrpsNoData, tb_scaling);
pdsch_pdu_rel15->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(mcsTableIdx, pdsch_pdu_rel15->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(mcsTableIdx,
dl_bwp->bw_tbslbrm, ra->sc_info.dl_bw_tbslbrm,
1); 1);
pdsch_pdu_rel15->maintenance_parms_v3.ldpcBaseGraph = get_BG(tb_size<<3,R); pdsch_pdu_rel15->maintenance_parms_v3.ldpcBaseGraph = get_BG(tb_size<<3,R);
@@ -1582,7 +1586,7 @@ static void prepare_dl_pdus(gNB_MAC_INST *nr_mac,
pdcch_pdu_rel15->DurationSymbols, pdcch_pdu_rel15->DurationSymbols,
pdsch_pdu_rel15->BWPSize); pdsch_pdu_rel15->BWPSize);
fill_dci_pdu_rel15(NULL, // parameter not needed for DCI 1_0 fill_dci_pdu_rel15(&ra->sc_info,
dl_bwp, dl_bwp,
&ra->UL_BWP, &ra->UL_BWP,
&pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci - 1], &pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci - 1],
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+4 -4
View File
@@ -400,8 +400,8 @@ static void get_start_stop_allocation(gNB_MAC_INST *mac,
*rbStop = *rbStart + mac->cset0_bwp_size; *rbStop = *rbStart + mac->cset0_bwp_size;
} }
else { else {
*rbStart = dl_bwp->initial_BWPStart; *rbStart = UE->sc_info.initial_dl_BWPStart;
*rbStop = *rbStart + dl_bwp->initial_BWPSize; *rbStop = *rbStart + UE->sc_info.initial_dl_BWPSize;
} }
} }
} }
@@ -1086,7 +1086,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
const int nl_tbslbrm = min(maxMIMO_Layers, 4); const int nl_tbslbrm = min(maxMIMO_Layers, 4);
// Maximum number of PRBs across all configured DL BWPs // Maximum number of PRBs across all configured DL BWPs
pdsch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(current_BWP->mcsTableIdx, pdsch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(current_BWP->mcsTableIdx,
current_BWP->bw_tbslbrm, UE->sc_info.dl_bw_tbslbrm,
nl_tbslbrm); nl_tbslbrm);
pdsch_pdu->maintenance_parms_v3.ldpcBaseGraph = get_BG(TBS<<3,R); pdsch_pdu->maintenance_parms_v3.ldpcBaseGraph = get_BG(TBS<<3,R);
@@ -1138,7 +1138,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
memset(&dci_payload, 0, sizeof(dci_pdu_rel15_t)); memset(&dci_payload, 0, sizeof(dci_pdu_rel15_t));
// bwp indicator // bwp indicator
// as per table 7.3.1.1.2-1 in 38.212 // as per table 7.3.1.1.2-1 in 38.212
dci_payload.bwp_indicator.val = current_BWP->n_dl_bwp < 4 ? bwp_id : bwp_id - 1; dci_payload.bwp_indicator.val = UE->sc_info.n_dl_bwp < 4 ? bwp_id : bwp_id - 1;
AssertFatal(pdsch_Config == NULL || pdsch_Config->resourceAllocation == NR_PDSCH_Config__resourceAllocation_resourceAllocationType1, AssertFatal(pdsch_Config == NULL || pdsch_Config->resourceAllocation == NR_PDSCH_Config__resourceAllocation_resourceAllocationType1,
"Only frequency resource allocation type 1 is currently supported\n"); "Only frequency resource allocation type 1 is currently supported\n");
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+21 -19
View File
@@ -684,8 +684,8 @@ void config_uldci(const NR_UE_ServingCell_Info_t *sc_info,
int time_domain_assignment, int time_domain_assignment,
uint8_t tpc, uint8_t tpc,
uint8_t ndi, uint8_t ndi,
NR_UE_UL_BWP_t *ul_bwp) { NR_UE_UL_BWP_t *ul_bwp)
{
int bwp_id = ul_bwp->bwp_id; int bwp_id = ul_bwp->bwp_id;
nr_dci_format_t dci_format = ul_bwp->dci_format; nr_dci_format_t dci_format = ul_bwp->dci_format;
@@ -710,7 +710,7 @@ void config_uldci(const NR_UE_ServingCell_Info_t *sc_info,
LOG_D(NR_MAC,"Configuring DCI Format 0_1\n"); LOG_D(NR_MAC,"Configuring DCI Format 0_1\n");
dci_pdu_rel15->dai[0].val = 0; //TODO dci_pdu_rel15->dai[0].val = 0; //TODO
// bwp indicator as per table 7.3.1.1.2-1 in 38.212 // bwp indicator as per table 7.3.1.1.2-1 in 38.212
dci_pdu_rel15->bwp_indicator.val = ul_bwp->n_ul_bwp < 4 ? bwp_id : bwp_id - 1; dci_pdu_rel15->bwp_indicator.val = sc_info->n_ul_bwp < 4 ? bwp_id : bwp_id - 1;
// SRS resource indicator // SRS resource indicator
if (pusch_Config && if (pusch_Config &&
pusch_Config->txConfig != NULL) { pusch_Config->txConfig != NULL) {
@@ -1150,8 +1150,8 @@ void fill_dci_pdu_rel15(const NR_UE_ServingCell_Info_t *servingCellInfo,
cset0_bwp_size, cset0_bwp_size,
current_UL_BWP->BWPSize, current_UL_BWP->BWPSize,
current_DL_BWP->BWPSize, current_DL_BWP->BWPSize,
current_UL_BWP->initial_BWPSize, servingCellInfo->initial_ul_BWPSize,
current_DL_BWP->initial_BWPSize); servingCellInfo->initial_dl_BWPSize);
// computing alternative size for padding // computing alternative size for padding
dci_pdu_rel15_t temp_pdu; dci_pdu_rel15_t temp_pdu;
@@ -2067,6 +2067,7 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
AssertFatal((ra != NULL && UE == NULL) || (ra == NULL && UE != NULL), "RA and UE structures are mutually exlusive in BWP configuration\n"); AssertFatal((ra != NULL && UE == NULL) || (ra == NULL && UE != NULL), "RA and UE structures are mutually exlusive in BWP configuration\n");
NR_CellGroupConfig_t *CellGroup; NR_CellGroupConfig_t *CellGroup;
NR_UE_ServingCell_Info_t *sc_info;
NR_UE_DL_BWP_t *DL_BWP; NR_UE_DL_BWP_t *DL_BWP;
NR_UE_UL_BWP_t *UL_BWP; NR_UE_UL_BWP_t *UL_BWP;
@@ -2074,19 +2075,21 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
DL_BWP = &ra->DL_BWP; DL_BWP = &ra->DL_BWP;
UL_BWP = &ra->UL_BWP; UL_BWP = &ra->UL_BWP;
CellGroup = ra->CellGroup; CellGroup = ra->CellGroup;
sc_info = &ra->sc_info;
} }
else { else {
DL_BWP = &UE->current_DL_BWP; DL_BWP = &UE->current_DL_BWP;
UL_BWP = &UE->current_UL_BWP; UL_BWP = &UE->current_UL_BWP;
CellGroup = UE->CellGroup; CellGroup = UE->CellGroup;
sc_info = &UE->sc_info;
} }
NR_BWP_Downlink_t *dl_bwp = NULL; NR_BWP_Downlink_t *dl_bwp = NULL;
NR_BWP_Uplink_t *ul_bwp = NULL; NR_BWP_Uplink_t *ul_bwp = NULL;
NR_BWP_DownlinkDedicated_t *bwpd = NULL; NR_BWP_DownlinkDedicated_t *bwpd = NULL;
NR_BWP_UplinkDedicated_t *ubwpd = NULL; NR_BWP_UplinkDedicated_t *ubwpd = NULL;
// number of additional BWPs (excluding initial BWP) // number of additional BWPs (excluding initial BWP)
DL_BWP->n_dl_bwp = 0; sc_info->n_dl_bwp = 0;
UL_BWP->n_ul_bwp = 0; sc_info->n_ul_bwp = 0;
int old_dl_bwp_id = DL_BWP->bwp_id; int old_dl_bwp_id = DL_BWP->bwp_id;
int old_ul_bwp_id = UL_BWP->bwp_id; int old_ul_bwp_id = UL_BWP->bwp_id;
@@ -2117,7 +2120,7 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
const struct NR_ServingCellConfig__downlinkBWP_ToAddModList *bwpList = servingCellConfig->downlinkBWP_ToAddModList; const struct NR_ServingCellConfig__downlinkBWP_ToAddModList *bwpList = servingCellConfig->downlinkBWP_ToAddModList;
if(bwpList) if(bwpList)
DL_BWP->n_dl_bwp = bwpList->list.count; sc_info->n_dl_bwp = bwpList->list.count;
if (DL_BWP->bwp_id>0) { if (DL_BWP->bwp_id>0) {
for (int i=0; i<bwpList->list.count; i++) { for (int i=0; i<bwpList->list.count; i++) {
dl_bwp = bwpList->list.array[i]; dl_bwp = bwpList->list.array[i];
@@ -2129,7 +2132,7 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
const struct NR_UplinkConfig__uplinkBWP_ToAddModList *ubwpList = servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList; const struct NR_UplinkConfig__uplinkBWP_ToAddModList *ubwpList = servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList;
if(ubwpList) if(ubwpList)
UL_BWP->n_ul_bwp = ubwpList->list.count; sc_info->n_ul_bwp = ubwpList->list.count;
if (UL_BWP->bwp_id>0) { if (UL_BWP->bwp_id>0) {
for (int i=0; i<ubwpList->list.count; i++) { for (int i=0; i<ubwpList->list.count; i++) {
ul_bwp = ubwpList->list.array[i]; ul_bwp = ubwpList->list.array[i];
@@ -2190,8 +2193,8 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
DL_BWP->cyclicprefix = dl_genericParameters.cyclicPrefix; DL_BWP->cyclicprefix = dl_genericParameters.cyclicPrefix;
DL_BWP->BWPSize = NRRIV2BW(dl_genericParameters.locationAndBandwidth, MAX_BWP_SIZE); DL_BWP->BWPSize = NRRIV2BW(dl_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
DL_BWP->BWPStart = NRRIV2PRBOFFSET(dl_genericParameters.locationAndBandwidth, MAX_BWP_SIZE); DL_BWP->BWPStart = NRRIV2PRBOFFSET(dl_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
DL_BWP->initial_BWPSize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); sc_info->initial_dl_BWPSize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
DL_BWP->initial_BWPStart = NRRIV2PRBOFFSET(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); sc_info->initial_dl_BWPStart = NRRIV2PRBOFFSET(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
NR_BWP_t ul_genericParameters = (UL_BWP->bwp_id > 0 && ul_bwp) ? NR_BWP_t ul_genericParameters = (UL_BWP->bwp_id > 0 && ul_bwp) ?
ul_bwp->bwp_Common->genericParameters: ul_bwp->bwp_Common->genericParameters:
@@ -2201,11 +2204,11 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
UL_BWP->cyclicprefix = ul_genericParameters.cyclicPrefix; UL_BWP->cyclicprefix = ul_genericParameters.cyclicPrefix;
UL_BWP->BWPSize = NRRIV2BW(ul_genericParameters.locationAndBandwidth, MAX_BWP_SIZE); UL_BWP->BWPSize = NRRIV2BW(ul_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
UL_BWP->BWPStart = NRRIV2PRBOFFSET(ul_genericParameters.locationAndBandwidth, MAX_BWP_SIZE); UL_BWP->BWPStart = NRRIV2PRBOFFSET(ul_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
UL_BWP->initial_BWPSize = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); sc_info->initial_ul_BWPSize = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
UL_BWP->initial_BWPStart = NRRIV2PRBOFFSET(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); sc_info->initial_ul_BWPStart = NRRIV2PRBOFFSET(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
DL_BWP->bw_tbslbrm = get_dlbw_tbslbrm(DL_BWP->initial_BWPSize, servingCellConfig); sc_info->dl_bw_tbslbrm = get_dlbw_tbslbrm(sc_info->initial_dl_BWPSize, servingCellConfig);
UL_BWP->bw_tbslbrm = get_ulbw_tbslbrm(UL_BWP->initial_BWPSize, servingCellConfig); sc_info->dl_bw_tbslbrm = get_ulbw_tbslbrm(sc_info->initial_ul_BWPSize, servingCellConfig);
if (UL_BWP->bwp_id > 0) { if (UL_BWP->bwp_id > 0) {
UL_BWP->pucch_ConfigCommon = ul_bwp->bwp_Common->pucch_ConfigCommon ? ul_bwp->bwp_Common->pucch_ConfigCommon->choice.setup : NULL; UL_BWP->pucch_ConfigCommon = ul_bwp->bwp_Common->pucch_ConfigCommon ? ul_bwp->bwp_Common->pucch_ConfigCommon->choice.setup : NULL;
@@ -2216,7 +2219,6 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
} }
if(UE) { if(UE) {
NR_UE_ServingCell_Info_t *sc_info = &UE->sc_info;
if (servingCellConfig) { if (servingCellConfig) {
if(servingCellConfig->csi_MeasConfig) { if(servingCellConfig->csi_MeasConfig) {
sc_info->csi_MeasConfig = servingCellConfig->csi_MeasConfig->choice.setup; sc_info->csi_MeasConfig = servingCellConfig->csi_MeasConfig->choice.setup;
@@ -2360,7 +2362,7 @@ NR_UE_info_t *add_new_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rntiP, NR_CellGroupConf
// We will attach at the end, to mitigate race conditions // We will attach at the end, to mitigate race conditions
// This is not good, but we will fix it progressively // This is not good, but we will fix it progressively
NR_UE_info_t *UE=calloc(1,sizeof(NR_UE_info_t)); NR_UE_info_t *UE = calloc(1,sizeof(NR_UE_info_t));
if(!UE) { if(!UE) {
LOG_E(NR_MAC,"want to add UE %04x but the fixed allocated size is full\n",rntiP); LOG_E(NR_MAC,"want to add UE %04x but the fixed allocated size is full\n",rntiP);
return NULL; return NULL;
@@ -2394,9 +2396,9 @@ NR_UE_info_t *add_new_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rntiP, NR_CellGroupConf
sched_ctrl->sched_pusch.time_domain_allocation = -1; sched_ctrl->sched_pusch.time_domain_allocation = -1;
/* Set default BWPs */ /* Set default BWPs */
AssertFatal(ul_bwp->n_ul_bwp <= NR_MAX_NUM_BWP, AssertFatal(UE->sc_info.n_ul_bwp <= NR_MAX_NUM_BWP,
"uplinkBWP_ToAddModList has %d BWP!\n", "uplinkBWP_ToAddModList has %d BWP!\n",
ul_bwp->n_ul_bwp); UE->sc_info.n_ul_bwp);
if (get_softmodem_params()->phy_test == 0) { if (get_softmodem_params()->phy_test == 0) {
UE->ra_timer = 12000 << UE->current_DL_BWP.scs; // 12000 ms is arbitrary and found to be a good timeout from experiments UE->ra_timer = 12000 << UE->current_DL_BWP.scs; // 12000 ms is arbitrary and found to be a good timeout from experiments
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c
+1 -1
View File
@@ -497,7 +497,7 @@ static void tci_handling(NR_UE_info_t *UE, frame_t frame, slot_t slot)
uint8_t i, j; uint8_t i, j;
//bwp indicator //bwp indicator
int n_dl_bwp = dl_bwp->n_dl_bwp; int n_dl_bwp = UE->sc_info.n_dl_bwp;
const int bwp_id = dl_bwp->bwp_id; const int bwp_id = dl_bwp->bwp_id;
if (n_dl_bwp < 4) if (n_dl_bwp < 4)
pdsch_bwp_id = bwp_id; pdsch_bwp_id = bwp_id;
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+1 -1
View File
@@ -2288,7 +2288,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot, n
maxMIMO_Layers = current_BWP->pusch_Config->maxRank; maxMIMO_Layers = current_BWP->pusch_Config->maxRank;
AssertFatal (maxMIMO_Layers != NULL,"Option with max MIMO layers not configured is not supported\n"); AssertFatal (maxMIMO_Layers != NULL,"Option with max MIMO layers not configured is not supported\n");
pusch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(current_BWP->mcs_table, pusch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(current_BWP->mcs_table,
current_BWP->bw_tbslbrm, sc_info->ul_bw_tbslbrm,
*maxMIMO_Layers); *maxMIMO_Layers);
} }
else else
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+1
View File
@@ -228,6 +228,7 @@ typedef struct {
// BWP for RA // BWP for RA
NR_UE_DL_BWP_t DL_BWP; NR_UE_DL_BWP_t DL_BWP;
NR_UE_UL_BWP_t UL_BWP; NR_UE_UL_BWP_t UL_BWP;
NR_UE_ServingCell_Info_t sc_info;
} NR_RA_t; } NR_RA_t;
/*! \brief gNB common channels */ /*! \brief gNB common channels */