From e64516d22217f187a0d00198e67591d4236226e5 Mon Sep 17 00:00:00 2001 From: francescomani Date: Wed, 4 Jun 2025 14:24:02 +0200 Subject: [PATCH] common function to generate FAPI PDSCH payload --- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 57 ++---- .../LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c | 71 ++------ .../LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 171 ++++++++++-------- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 12 +- 4 files changed, 134 insertions(+), 177 deletions(-) diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 048fa29457..c1ba7b57f9 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -1348,7 +1348,6 @@ static void prepare_dl_pdus(gNB_MAC_INST *nr_mac, nr_rnti_type_t rnti_type, int aggregation_level, int CCEIndex, - int tb_size, int ndi, int tpc, int delta_PRI, @@ -1384,51 +1383,21 @@ static void prepare_dl_pdus(gNB_MAC_INST *nr_mac, dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE; dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2 + sizeof(nfapi_nr_dl_tti_pdsch_pdu)); dl_req->nPDUs += 1; - nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id]; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP; - int mcsTableIdx = dl_bwp->mcsTableIdx; - - pdsch_pdu_rel15->pduBitmap = 0; - pdsch_pdu_rel15->rnti = rnti; - pdsch_pdu_rel15->pduIndex = pduindex; - pdsch_pdu_rel15->BWPSize = BWPSize; - pdsch_pdu_rel15->BWPStart = BWPStart; - pdsch_pdu_rel15->SubcarrierSpacing = dl_bwp->scs; - pdsch_pdu_rel15->CyclicPrefix = 0; - pdsch_pdu_rel15->NrOfCodewords = 1; - pdsch_pdu_rel15->targetCodeRate[0] = sched_pdsch->R; - pdsch_pdu_rel15->qamModOrder[0] = sched_pdsch->Qm; - pdsch_pdu_rel15->TBSize[0] = tb_size; - pdsch_pdu_rel15->mcsIndex[0] = sched_pdsch->mcs; - pdsch_pdu_rel15->mcsTable[0] = mcsTableIdx; - pdsch_pdu_rel15->rvIndex[0] = nr_get_rv(round % 4); - pdsch_pdu_rel15->dataScramblingId = *scc->physCellId; - pdsch_pdu_rel15->nrOfLayers = 1; - pdsch_pdu_rel15->transmissionScheme = 0; - pdsch_pdu_rel15->refPoint = 0; - pdsch_pdu_rel15->dmrsConfigType = sched_pdsch->dmrs_parms.dmrsConfigType; - pdsch_pdu_rel15->dlDmrsScramblingId = sched_pdsch->dmrs_parms.scrambling_id; - pdsch_pdu_rel15->SCID = sched_pdsch->dmrs_parms.n_scid; - pdsch_pdu_rel15->numDmrsCdmGrpsNoData = sched_pdsch->dmrs_parms.numDmrsCdmGrpsNoData; - pdsch_pdu_rel15->dmrsPorts = 1; - pdsch_pdu_rel15->resourceAlloc = 1; - pdsch_pdu_rel15->rbStart = sched_pdsch->rbStart; - pdsch_pdu_rel15->rbSize = sched_pdsch->rbSize; - pdsch_pdu_rel15->VRBtoPRBMapping = 0; - pdsch_pdu_rel15->StartSymbolIndex = sched_pdsch->tda_info.startSymbolIndex; - pdsch_pdu_rel15->NrOfSymbols = sched_pdsch->tda_info.nrOfSymbols; - pdsch_pdu_rel15->dlDmrsSymbPos = sched_pdsch->dmrs_parms.dl_dmrs_symb_pos; - pdsch_pdu_rel15->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(mcsTableIdx, UE->sc_info.dl_bw_tbslbrm, 1); - pdsch_pdu_rel15->maintenance_parms_v3.ldpcBaseGraph = get_BG(tb_size << 3, sched_pdsch->R); - - pdsch_pdu_rel15->precodingAndBeamforming.num_prgs = 1; - pdsch_pdu_rel15->precodingAndBeamforming.prg_size = 275; - pdsch_pdu_rel15->precodingAndBeamforming.dig_bf_interfaces = 1; - pdsch_pdu_rel15->precodingAndBeamforming.prgs_list[0].pm_idx = 0; - pdsch_pdu_rel15->precodingAndBeamforming.prgs_list[0].dig_bf_interface_list[0].beam_idx = UE->UE_beam_index; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = prepare_pdsch_pdu(dl_tti_pdsch_pdu, + nr_mac, + UE, + sched_pdsch, + dl_bwp->pdsch_Config, + false, + round, + rnti, + UE->UE_beam_index, + 1, + pduindex); /* Fill PDCCH DL DCI PDU */ nfapi_nr_dl_dci_pdu_t *dci_pdu = &pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci]; @@ -1703,6 +1672,7 @@ static void nr_generate_Msg2(module_id_t module_idP, .dmrs_parms = dmrs_parms, .tda_info = tda_info, .pm_index = 0, + .tb_size = TBS, .rbStart = rbStart, .rbSize = rbSize }; @@ -1714,7 +1684,6 @@ static void nr_generate_Msg2(module_id_t module_idP, TYPE_RA_RNTI_, aggregation_level, CCEIndex, - TBS, 0, 0, 0, @@ -2011,6 +1980,7 @@ static void nr_generate_Msg4_MsgB(module_id_t module_idP, .dmrs_parms = dmrs_info, .tda_info = msg4_tda, .pm_index = 0, + .tb_size = tb_size, .rbStart = rbStart, .rbSize = rbSize }; @@ -2023,7 +1993,6 @@ static void nr_generate_Msg4_MsgB(module_id_t module_idP, TYPE_TC_RNTI_, aggregation_level, CCEIndex, - tb_size, harq->ndi, sched_ctrl->tpc1, delta_PRI, diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c index b89def219b..79f601362c 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c @@ -414,7 +414,6 @@ static void nr_fill_nfapi_dl_SIB_pdu(gNB_MAC_INST *gNB_mac, nfapi_nr_dl_tti_request_body_t *dl_req, int pdu_index, NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config, - uint32_t TBS, bool is_sib1, int beam_index) { @@ -434,50 +433,18 @@ static void nr_fill_nfapi_dl_SIB_pdu(gNB_MAC_INST *gNB_mac, dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE; dl_tti_pdsch_pdu->PDUSize = (uint16_t)(4+sizeof(nfapi_nr_dl_tti_pdsch_pdu)); dl_req->nPDUs += 1; - nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; - - pdsch_pdu_rel15->precodingAndBeamforming.num_prgs = 0; - pdsch_pdu_rel15->precodingAndBeamforming.prg_size = 0; - pdsch_pdu_rel15->precodingAndBeamforming.dig_bf_interfaces = 1; - pdsch_pdu_rel15->precodingAndBeamforming.prgs_list[0].pm_idx = 0; - pdsch_pdu_rel15->precodingAndBeamforming.prgs_list[0].dig_bf_interface_list[0].beam_idx = beam_index; - - pdcch_pdu_rel15->CoreSetType = NFAPI_NR_CSET_CONFIG_MIB_SIB1; - - pdsch_pdu_rel15->pduBitmap = 0; - pdsch_pdu_rel15->rnti = SI_RNTI; - pdsch_pdu_rel15->pduIndex = pdu_index; - - pdsch_pdu_rel15->BWPSize = type0_PDCCH_CSS_config->num_rbs; - pdsch_pdu_rel15->BWPStart = type0_PDCCH_CSS_config->cset_start_rb; - - pdsch_pdu_rel15->SubcarrierSpacing = type0_PDCCH_CSS_config->scs_pdcch; - pdsch_pdu_rel15->CyclicPrefix = 0; - - pdsch_pdu_rel15->NrOfCodewords = 1; - pdsch_pdu_rel15->targetCodeRate[0] = pdsch->R; - pdsch_pdu_rel15->qamModOrder[0] = pdsch->Qm; - pdsch_pdu_rel15->mcsIndex[0] = pdsch->mcs; - pdsch_pdu_rel15->mcsTable[0] = 0; - pdsch_pdu_rel15->rvIndex[0] = nr_get_rv(0); - pdsch_pdu_rel15->dataScramblingId = *scc->physCellId; - pdsch_pdu_rel15->nrOfLayers = 1; - pdsch_pdu_rel15->transmissionScheme = 0; - pdsch_pdu_rel15->refPoint = is_sib1; - pdsch_pdu_rel15->dmrsConfigType = 0; - pdsch_pdu_rel15->dlDmrsScramblingId = pdsch->dmrs_parms.scrambling_id; - pdsch_pdu_rel15->SCID = pdsch->dmrs_parms.n_scid; - pdsch_pdu_rel15->numDmrsCdmGrpsNoData = pdsch->dmrs_parms.numDmrsCdmGrpsNoData; - pdsch_pdu_rel15->dmrsPorts = 1; - pdsch_pdu_rel15->resourceAlloc = 1; - pdsch_pdu_rel15->rbStart = pdsch->rbStart; - pdsch_pdu_rel15->rbSize = pdsch->rbSize; - pdsch_pdu_rel15->VRBtoPRBMapping = 0; - pdsch_pdu_rel15->TBSize[0] = TBS; - pdsch_pdu_rel15->StartSymbolIndex = pdsch->tda_info.startSymbolIndex; - pdsch_pdu_rel15->NrOfSymbols = pdsch->tda_info.nrOfSymbols; - pdsch_pdu_rel15->dlDmrsSymbPos = pdsch->dmrs_parms.dl_dmrs_symb_pos; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = prepare_pdsch_pdu(dl_tti_pdsch_pdu, + gNB_mac, + NULL, + pdsch, + NULL, + is_sib1, + 0, + SI_RNTI, + beam_index, + 1, + pdu_index); LOG_D(NR_MAC, "OtherSI:bwpStart %d, bwpSize %d, rbStart %d, rbSize %d, dlDmrsSymbPos = 0x%x\n", pdsch_pdu_rel15->BWPStart, @@ -486,11 +453,6 @@ static void nr_fill_nfapi_dl_SIB_pdu(gNB_MAC_INST *gNB_mac, pdsch_pdu_rel15->rbSize, pdsch_pdu_rel15->dlDmrsSymbPos); - pdsch_pdu_rel15->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(0, - pdsch_pdu_rel15->BWPSize, - 1); - pdsch_pdu_rel15->maintenance_parms_v3.ldpcBaseGraph = get_BG(TBS<<3,pdsch_pdu_rel15->targetCodeRate[0]); - /* Fill PDCCH DL DCI PDU */ nfapi_nr_dl_dci_pdu_t *dci_pdu = &pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci]; pdcch_pdu_rel15->numDlDci++; @@ -646,6 +608,7 @@ void schedule_nr_sib1(module_id_t module_idP, beam.idx, cc->sib1_bcch_length); + gNB_mac->sched_ctrlCommon->sched_pdsch.tb_size = TBS; nfapi_nr_dl_tti_request_body_t *dl_req = &DL_req->dl_tti_request_body; int pdu_index = gNB_mac->pdu_index[0]++; nr_fill_nfapi_dl_SIB_pdu(gNB_mac, @@ -658,7 +621,6 @@ void schedule_nr_sib1(module_id_t module_idP, dl_req, pdu_index, type0_PDCCH_CSS_config, - TBS, true, beam_index); @@ -773,7 +735,7 @@ static void other_sib_sched_control(module_id_t module_idP, uint16_t *vrb_map = cc->vrb_map[beam.idx]; uint8_t *sib_bcch_pdu = cc->other_sib_bcch_pdu[payload_idx]; int num_total_bytes = cc->other_sib_bcch_length[payload_idx]; - uint32_t TBS = get_tbs_bch(type0_PDCCH_CSS_config, &sched_pdsch_otherSI, num_total_bytes, vrb_map); + sched_pdsch_otherSI.tb_size = get_tbs_bch(type0_PDCCH_CSS_config, &sched_pdsch_otherSI, num_total_bytes, vrb_map); sched_pdsch_otherSI.R = nr_get_code_rate_dl(sched_pdsch_otherSI.mcs, 0); sched_pdsch_otherSI.Qm = nr_get_Qm_dl(sched_pdsch_otherSI.mcs, 0); @@ -793,7 +755,6 @@ static void other_sib_sched_control(module_id_t module_idP, dl_req, pdu_index, type0_PDCCH_CSS_config, - TBS, false, beam_index); @@ -801,12 +762,12 @@ static void other_sib_sched_control(module_id_t module_idP, nfapi_nr_pdu_t *tx_req = &TX_req->pdu_list[ntx_req]; // Data to be transmitted - memcpy(tx_req->TLVs[0].value.direct, sib_bcch_pdu, TBS); + memcpy(tx_req->TLVs[0].value.direct, sib_bcch_pdu, sched_pdsch_otherSI.tb_size); - tx_req->PDU_length = TBS; + tx_req->PDU_length = sched_pdsch_otherSI.tb_size; tx_req->PDU_index = pdu_index; tx_req->num_TLV = 1; - tx_req->TLVs[0].length = TBS + 2; + tx_req->TLVs[0].length = sched_pdsch_otherSI.tb_size + 2; TX_req->Number_of_PDUs++; TX_req->SFN = frame; TX_req->Slot = slot; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index c887aaae88..9e0b9dfbd7 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -923,6 +923,85 @@ nr_pp_impl_dl nr_init_dlsch_preprocessor(int CC_id) { return nr_dlsch_preprocessor; } +nfapi_nr_dl_tti_pdsch_pdu_rel15_t *prepare_pdsch_pdu(nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu, + const gNB_MAC_INST *mac, + const NR_UE_info_t *UE, + const NR_sched_pdsch_t *sched_pdsch, + const NR_PDSCH_Config_t *pdsch_Config, + bool is_sib1, + int harq_round, + int rnti, + int beam_index, + int nl_tbslbrm, + int pdu_index) +{ + const NR_UE_DL_BWP_t *dl_bwp = UE ? &UE->current_DL_BWP : NULL; + const NR_ServingCellConfigCommon_t *scc = mac->common_channels[0].ServingCellConfigCommon; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; + pdsch_pdu->pduBitmap = 0; + pdsch_pdu->rnti = rnti; + pdsch_pdu->pduIndex = pdu_index; + bwp_info_t bwp_info = get_pdsch_bwp_start_size(mac, UE); + pdsch_pdu->BWPSize = bwp_info.bwpSize; + pdsch_pdu->BWPStart = bwp_info.bwpStart; + pdsch_pdu->SubcarrierSpacing = dl_bwp ? dl_bwp->scs : *scc->ssbSubcarrierSpacing; + pdsch_pdu->CyclicPrefix = dl_bwp && dl_bwp->cyclicprefix ? *dl_bwp->cyclicprefix : 0; + // Codeword information + pdsch_pdu->NrOfCodewords = 1; + pdsch_pdu->targetCodeRate[0] = sched_pdsch->R; + pdsch_pdu->qamModOrder[0] = sched_pdsch->Qm; + pdsch_pdu->mcsIndex[0] = sched_pdsch->mcs; + pdsch_pdu->mcsTable[0] = dl_bwp ? dl_bwp->mcsTableIdx : 0; + pdsch_pdu->rvIndex[0] = nr_get_rv(harq_round % 4); + pdsch_pdu->TBSize[0] = sched_pdsch->tb_size; + pdsch_pdu->dataScramblingId = pdsch_Config && pdsch_Config->dataScramblingIdentityPDSCH ? *pdsch_Config->dataScramblingIdentityPDSCH : *scc->physCellId; + pdsch_pdu->nrOfLayers = sched_pdsch->nrOfLayers; + pdsch_pdu->transmissionScheme = 0; + pdsch_pdu->refPoint = is_sib1; + // DMRS + const NR_pdsch_dmrs_t *dmrs_parms = &sched_pdsch->dmrs_parms; + pdsch_pdu->dlDmrsSymbPos = dmrs_parms->dl_dmrs_symb_pos; + pdsch_pdu->dmrsConfigType = dmrs_parms->dmrsConfigType; + pdsch_pdu->SCID = dmrs_parms->n_scid; + pdsch_pdu->dlDmrsScramblingId = dmrs_parms->scrambling_id; + pdsch_pdu->numDmrsCdmGrpsNoData = dmrs_parms->numDmrsCdmGrpsNoData; + pdsch_pdu->dmrsPorts = (1 << sched_pdsch->nrOfLayers) - 1; // FIXME with a better implementation + // Pdsch Allocation in frequency domain + pdsch_pdu->resourceAlloc = 1; + pdsch_pdu->rbStart = sched_pdsch->rbStart; + pdsch_pdu->rbSize = sched_pdsch->rbSize; + pdsch_pdu->VRBtoPRBMapping = 0; // non-interleaved + // Resource Allocation in time domain + const NR_tda_info_t *tda_info = &sched_pdsch->tda_info; + pdsch_pdu->StartSymbolIndex = tda_info->startSymbolIndex; + pdsch_pdu->NrOfSymbols = tda_info->nrOfSymbols; + /* Check and validate PTRS values */ + if (dmrs_parms->phaseTrackingRS) { + bool valid_ptrs_setup = set_dl_ptrs_values(dmrs_parms->phaseTrackingRS, + pdsch_pdu->rbSize, + pdsch_pdu->mcsIndex[0], + pdsch_pdu->mcsTable[0], + &pdsch_pdu->PTRSFreqDensity, + &pdsch_pdu->PTRSTimeDensity, + &pdsch_pdu->PTRSPortIndex, + &pdsch_pdu->nEpreRatioOfPDSCHToPTRS, + &pdsch_pdu->PTRSReOffset, + pdsch_pdu->NrOfSymbols); + if (valid_ptrs_setup) + pdsch_pdu->pduBitmap |= 0x1; // Bit 0: pdschPtrs - Indicates PTRS included (FR2) + } + int dl_bw_tbslbrm = UE ? UE->sc_info.dl_bw_tbslbrm : bwp_info.bwpSize; + pdsch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(pdsch_pdu->mcsTable[0], dl_bw_tbslbrm, nl_tbslbrm); + pdsch_pdu->maintenance_parms_v3.ldpcBaseGraph = get_BG(sched_pdsch->tb_size << 3, sched_pdsch->R); + // Precoding and beamforming + pdsch_pdu->precodingAndBeamforming.num_prgs = 0; + pdsch_pdu->precodingAndBeamforming.prg_size = pdsch_pdu->rbSize; + pdsch_pdu->precodingAndBeamforming.dig_bf_interfaces = 0; + pdsch_pdu->precodingAndBeamforming.prgs_list[0].pm_idx = sched_pdsch->pm_index; + pdsch_pdu->precodingAndBeamforming.prgs_list[0].dig_bf_interface_list[0].beam_idx = beam_index; + return pdsch_pdu; +} + void nr_schedule_ue_spec(module_id_t module_id, frame_t frame, slot_t slot, @@ -974,8 +1053,6 @@ void nr_schedule_ue_spec(module_id_t module_id, /* POST processing */ const uint8_t nrOfLayers = sched_pdsch->nrOfLayers; - const uint16_t R = sched_pdsch->R; - const uint8_t Qm = sched_pdsch->Qm; const uint32_t TBS = sched_pdsch->tb_size; int8_t current_harq_pid = sched_pdsch->dl_harq_pid; @@ -1059,91 +1136,29 @@ void nr_schedule_ue_spec(module_id_t module_id, nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; memset(dl_tti_pdsch_pdu, 0, sizeof(nfapi_nr_dl_tti_request_pdu_t)); dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE; - dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdsch_pdu)); + dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2 + sizeof(nfapi_nr_dl_tti_pdsch_pdu)); dl_req->nPDUs += 1; - nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; - pdsch_pdu->pduBitmap = 0; - pdsch_pdu->rnti = rnti; /* SCF222: PDU index incremented for each PDSCH PDU sent in TX control * message. This is used to associate control information to data and is * reset every slot. */ const int pduindex = gNB_mac->pdu_index[CC_id]++; - pdsch_pdu->pduIndex = pduindex; - - bwp_info_t bwp_info = get_pdsch_bwp_start_size(gNB_mac, UE); - pdsch_pdu->BWPSize = bwp_info.bwpSize; - pdsch_pdu->BWPStart = bwp_info.bwpStart; - - pdsch_pdu->SubcarrierSpacing = current_BWP->scs; - pdsch_pdu->CyclicPrefix = current_BWP->cyclicprefix ? *current_BWP->cyclicprefix : 0; - // Codeword information - pdsch_pdu->NrOfCodewords = 1; - //number of information bits per 1024 coded bits expressed in 0.1 bit units - pdsch_pdu->targetCodeRate[0] = R; - pdsch_pdu->qamModOrder[0] = Qm; - pdsch_pdu->mcsIndex[0] = sched_pdsch->mcs; - pdsch_pdu->mcsTable[0] = current_BWP->mcsTableIdx; - // NVIDIA: Workaround for MCSTableIdx mismatch error - if (nr_get_code_rate_dl(sched_pdsch->mcs, current_BWP->mcsTableIdx) != R) { - pdsch_pdu->mcsTable[0] = 0; - } - AssertFatal(harq->round < gNB_mac->dl_bler.harq_round_max,"%d", harq->round); - pdsch_pdu->rvIndex[0] = nr_get_rv(harq->round % 4); - pdsch_pdu->TBSize[0] = TBS; - pdsch_pdu->dataScramblingId = *scc->physCellId; - pdsch_pdu->nrOfLayers = nrOfLayers; - pdsch_pdu->transmissionScheme = 0; - pdsch_pdu->refPoint = 0; // Point A - // DMRS - pdsch_pdu->dlDmrsSymbPos = dmrs_parms->dl_dmrs_symb_pos; - pdsch_pdu->dmrsConfigType = dmrs_parms->dmrsConfigType; - pdsch_pdu->dlDmrsScramblingId = dmrs_parms->scrambling_id; - pdsch_pdu->SCID = dmrs_parms->n_scid; - pdsch_pdu->numDmrsCdmGrpsNoData = dmrs_parms->numDmrsCdmGrpsNoData; - pdsch_pdu->dmrsPorts = (1<resourceAlloc = 1; - pdsch_pdu->rbStart = sched_pdsch->rbStart; - pdsch_pdu->rbSize = sched_pdsch->rbSize; - pdsch_pdu->VRBtoPRBMapping = 1; // non-interleaved, check if this is ok for initialBWP - // Resource Allocation in time domain - pdsch_pdu->StartSymbolIndex = tda_info->startSymbolIndex; - pdsch_pdu->NrOfSymbols = tda_info->nrOfSymbols; - // Precoding - pdsch_pdu->precodingAndBeamforming.num_prgs = 0; - pdsch_pdu->precodingAndBeamforming.prg_size = pdsch_pdu->rbSize; - pdsch_pdu->precodingAndBeamforming.dig_bf_interfaces = 0; - pdsch_pdu->precodingAndBeamforming.prgs_list[0].pm_idx = sched_pdsch->pm_index; - pdsch_pdu->precodingAndBeamforming.prgs_list[0].dig_bf_interface_list[0].beam_idx = UE->UE_beam_index; - // TBS_LBRM according to section 5.4.2.1 of 38.212 // TODO: verify the case where maxMIMO_Layers is NULL, in which case // in principle maxMIMO_layers should be given by the maximum number of layers // for PDSCH supported by the UE for the serving cell (5.4.2.1 of 38.212) long maxMIMO_Layers = UE->sc_info.maxMIMO_Layers_PDSCH ? *UE->sc_info.maxMIMO_Layers_PDSCH : 1; const int nl_tbslbrm = min(maxMIMO_Layers, 4); - // Maximum number of PRBs across all configured DL BWPs - pdsch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = - nr_compute_tbslbrm(current_BWP->mcsTableIdx, UE->sc_info.dl_bw_tbslbrm, nl_tbslbrm); - pdsch_pdu->maintenance_parms_v3.ldpcBaseGraph = get_BG(TBS<<3,R); + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu = prepare_pdsch_pdu(dl_tti_pdsch_pdu, + gNB_mac, + UE, + sched_pdsch, + current_BWP->pdsch_Config, + false, + harq->round, + rnti, + UE->UE_beam_index, + nl_tbslbrm, + pduindex); - NR_PDSCH_Config_t *pdsch_Config = current_BWP->pdsch_Config; - - /* Check and validate PTRS values */ - if (dmrs_parms->phaseTrackingRS) { - bool valid_ptrs_setup = set_dl_ptrs_values(dmrs_parms->phaseTrackingRS, - pdsch_pdu->rbSize, - pdsch_pdu->mcsIndex[0], - pdsch_pdu->mcsTable[0], - &pdsch_pdu->PTRSFreqDensity, - &pdsch_pdu->PTRSTimeDensity, - &pdsch_pdu->PTRSPortIndex, - &pdsch_pdu->nEpreRatioOfPDSCHToPTRS, - &pdsch_pdu->PTRSReOffset, - pdsch_pdu->NrOfSymbols); - - if (valid_ptrs_setup) - pdsch_pdu->pduBitmap |= 0x1; // Bit 0: pdschPtrs - Indicates PTRS included (FR2) - } LOG_D(NR_MAC,"Configuring DCI/PDCCH in %d.%d at CCE %d, rnti %x\n", frame,slot,sched_ctrl->cce_index,rnti); /* Fill PDCCH DL DCI PDU */ @@ -1180,7 +1195,9 @@ void nr_schedule_ue_spec(module_id_t module_id, // as per table 7.3.1.1.2-1 in 38.212 dci_payload.bwp_indicator.val = UE->sc_info.n_dl_bwp < 4 ? bwp_id : bwp_id - 1; - AssertFatal(pdsch_Config == NULL || pdsch_Config->resourceAllocation == NR_PDSCH_Config__resourceAllocation_resourceAllocationType1, + NR_PDSCH_Config_t *pdsch_Config = current_BWP->pdsch_Config; + AssertFatal(pdsch_Config == NULL + || pdsch_Config->resourceAllocation == NR_PDSCH_Config__resourceAllocation_resourceAllocationType1, "Only frequency resource allocation type 1 is currently supported\n"); // 3GPP TS 38.214 Section 5.1.2.2.2 Downlink resource allocation type 1 diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 6acf4ae1d8..527b733c02 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -323,7 +323,17 @@ void nr_check_Msg4_MsgB_Ack(module_id_t module_id, frame_t frame, slot_t slot, N void mac_remove_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rnti); NR_UE_info_t *get_new_nr_ue_inst(uid_allocator_t *uia, rnti_t rnti, NR_CellGroupConfig_t *CellGroup); int nr_get_default_pucch_res(int pucch_ResourceCommon); - +nfapi_nr_dl_tti_pdsch_pdu_rel15_t *prepare_pdsch_pdu(nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu, + const gNB_MAC_INST *mac, + const NR_UE_info_t *UE, + const NR_sched_pdsch_t *sched_pdsch, + const NR_PDSCH_Config_t *pdsch_Config, + bool is_sib1, + int harq_round, + int rnti, + int beam_index, + int nl_tbslbrm, + int pdu_index); int nr_write_ce_dlsch_pdu(module_id_t module_idP, const NR_UE_sched_ctrl_t *ue_sched_ctl, unsigned char *mac_pdu,