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Merge remote-tracking branch 'origin/NR_UE_MAC_scheduler' into integration_2020_wk46

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hardy
2020-11-10 17:23:36 +01:00
parent 122e18d088 6056de78b3
commit e9fff748c6
13 changed files with 313 additions and 200 deletions
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openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
+10 -1
View File
@@ -242,6 +242,10 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
dlsch0_harq->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table);
dlsch0_harq->R = nr_get_code_rate_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table);
if (dlsch0_harq->Qm == 0 || dlsch0_harq->R == 0) {
LOG_W(MAC, "Invalid code rate or Mod order, likely due to unexpected DL DCI.\n");
return -1;
}
#ifdef DEBUG_HARQ
printf("[DEMOD] MIMO mode = %d\n", dlsch0_harq->mimo_mode);
@@ -981,7 +985,12 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
}
if (dlsch1_harq) {
switch (nr_get_Qm_dl(dlsch1_harq->mcs,dlsch1_harq->mcs_table)) {
uint8_t Qm = nr_get_Qm_dl(dlsch1_harq->mcs,dlsch1_harq->mcs_table);
if (Qm == 0){
LOG_W(MAC, "Invalid code rate or Mod order, likely due to unexpected DL DCI.\n");
return -1;
}
switch (Qm) {
case 2 :
if (rx_type==rx_standard) {
nr_dlsch_qpsk_llr(frame_parms,
openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
+2 -2
View File
@@ -154,8 +154,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH;
if (scheduled_response->tx_request){ // TBR todo here it should loop through the number of tx pdus
fapi_nr_tx_request_body_t *tx_req_body = scheduled_response->tx_request->tx_request_body;
if (scheduled_response->tx_request){
fapi_nr_tx_request_body_t *tx_req_body = &scheduled_response->tx_request->tx_request_body[i];
memcpy(harq_process_ul_ue->a, tx_req_body->pdu, tx_req_body->pdu_length);
openair1/SIMULATION/NR_PHY/ulsim.c
+5 -7
View File
@@ -671,8 +671,7 @@ int main(int argc, char **argv)
nr_scheduled_response_t scheduled_response;
fapi_nr_ul_config_request_t ul_config;
fapi_nr_tx_request_t tx_req;
fapi_nr_tx_request_body_t tx_req_body;
uint8_t ptrs_mcs1 = 2;
uint8_t ptrs_mcs2 = 4;
uint8_t ptrs_mcs3 = 10;
@@ -908,16 +907,15 @@ int main(int argc, char **argv)
scheduled_response.dl_config = NULL;
scheduled_response.ul_config = &ul_config;
scheduled_response.tx_request = &tx_req;
scheduled_response.tx_request->tx_request_body = &tx_req_body;
// Config UL TX PDU
tx_req.slot = slot;
tx_req.sfn = frame;
// tx_req->tx_config // TbD
tx_req.number_of_pdus = 1;
tx_req_body.pdu_length = TBS/8;
tx_req_body.pdu_index = 0;
tx_req_body.pdu = &ulsch_input_buffer[0];
tx_req.tx_request_body[0].pdu_length = TBS/8;
tx_req.tx_request_body[0].pdu_index = 0;
tx_req.tx_request_body[0].pdu = &ulsch_input_buffer[0];
ul_config.slot = slot;
ul_config.number_pdus = 1;