separating MAC and PHY procedures for TA

This commit is contained in:
francescomani
2023-04-12 10:32:35 +02:00
parent 98f4d038d4
commit eb09a63001
21 changed files with 201 additions and 283 deletions
@@ -50,7 +50,7 @@
// when PDSCH DM-RS position l1 for the additional DM-RS is != 1,2
*/
int8_t pdsch_N_1_capability_1[4][4] = {
static const int8_t pdsch_N_1_capability_1[4][4] = {
/* mu A B C */
{ 0, 8, 14, 13 },
{ 1, 10, 13, 13 },
@@ -69,7 +69,7 @@ int8_t pdsch_N_1_capability_1[4][4] = {
// dmrs-DownlinkForPDSCH-MappingTypeA and dmrs-DownlinkForPDSCH-MappingTypeB
// mu == 2 is for FR1 only
*/
float pdsch_N_1_capability_2[3][2] = {
static const float pdsch_N_1_capability_2[3][2] = {
/* mu A */
{ 0, 3 },
{ 1, 4.5 },
@@ -84,7 +84,7 @@ float pdsch_N_1_capability_2[3][2] = {
// carrying the DCI scheduling the PUSCH was transmitted
// mu_UL is the SCS of the UL channel with which PUSCH to be transmitted
*/
int8_t pusch_N_2_timing_capability_1[4][2] = {
static const int8_t pusch_N_2_timing_capability_1[4][2] = {
/* mu N_2 */
{ 0, 10 },
{ 1, 12 },
@@ -101,7 +101,7 @@ int8_t pusch_N_2_timing_capability_1[4][2] = {
// mu_UL is the SCS of the UL channel with which PUSCH to be transmitted
// mu == 2 is for FR1 only
*/
float pusch_N_2_timing_capability_2[3][2] = {
static const float pusch_N_2_timing_capability_2[3][2] = {
/* mu N_2 */
{ 0, 5 },
{ 1, 5.5 },
@@ -116,7 +116,7 @@ float pusch_N_2_timing_capability_2[3][2] = {
// carrying the DCI scheduling the PUSCH was transmitted
// mu_UL is the SCS of the UL channel with which PUSCH to be transmitted
*/
float pusch_d_2_2_timing_capability_1[4][2] = {
static const float pusch_d_2_2_timing_capability_1[4][2] = {
/* mu d_2_2 */
{ 0, 1 },
{ 1, 2 },
@@ -132,7 +132,7 @@ float pusch_d_2_2_timing_capability_1[4][2] = {
// carrying the DCI scheduling the PUSCH was transmitted
// mu_UL is the SCS of the UL channel with which PUSCH to be transmitted
*/
float pusch_d_2_2_timing_capability_2[4][2] = {
static const float pusch_d_2_2_timing_capability_2[4][2] = {
/* mu d_2_2 */
{ 0, 3 },
{ 1, 5 },