CPPCHECK: fixes
Signed-off-by: Raphael Defosseux <raphael.defosseux@eurecom.fr>
This commit is contained in:
@@ -37,6 +37,7 @@ memleak:openair2/UTIL/OMG/omg_hashtable.c
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// _emm_as_encode function creates the encoded buffer
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// _emm_as_encode function creates the encoded buffer
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//
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//
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memleak:openair3/NAS/UE/EMM/SAP/emm_as.c
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memleak:openair3/NAS/UE/EMM/SAP/emm_as.c
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memleak:openair1/PHY/INIT/nr_init_ue.c
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//*****************************************************************************
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//*****************************************************************************
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// section for files not used in oai exec's included in CI.
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// section for files not used in oai exec's included in CI.
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@@ -180,7 +180,7 @@ int config_libconfig_get(paramdef_t *cfgoptions,int numoptions, char *prefix ) {
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printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long unsigned)(*(cfgoptions[i].u64ptr)) );
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printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long unsigned)(*(cfgoptions[i].u64ptr)) );
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} else {
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} else {
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*(cfgoptions[i].i64ptr) = llu;
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*(cfgoptions[i].i64ptr) = llu;
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printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long)(*(cfgoptions[i].i64ptr)) );
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printf_params("[LIBCONFIG] %s: %lld\n", cfgpath,(long long)(*(cfgoptions[i].i64ptr)) );
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}
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}
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} else {
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} else {
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defval=config_setdefault_int64(&(cfgoptions[i]),prefix);
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defval=config_setdefault_int64(&(cfgoptions[i]),prefix);
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@@ -563,9 +563,6 @@ void rx_nr_prach(PHY_VARS_gNB *gNB,
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int16_t prach_ifft_tmp[2048*2] __attribute__((aligned(32)));
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int16_t prach_ifft_tmp[2048*2] __attribute__((aligned(32)));
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int32_t *prach_ifft=(int32_t*)NULL;
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int32_t *prach_ifft=(int32_t*)NULL;
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AssertFatal(gNB!=NULL,"gNB is null\n");
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fp = &gNB->frame_parms;
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fp = &gNB->frame_parms;
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nb_rx = gNB->gNB_config.carrier_config.num_rx_ant.value;
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nb_rx = gNB->gNB_config.carrier_config.num_rx_ant.value;
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@@ -1456,7 +1456,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB,
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// non-coherent LLR computation on groups of 4 REs (half-PRBs)
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// non-coherent LLR computation on groups of 4 REs (half-PRBs)
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int32_t corr_re,corr_im,corr_tmp;
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int32_t corr_re,corr_im,corr_tmp;
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__m128i corr16,llr_num,llr_den;
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__m128i corr16,llr_num,llr_den;
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uint64_t corr;
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uint64_t corr = 0;
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for (int half_prb=0;half_prb<(2*pucch_pdu->prb_size);half_prb++) {
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for (int half_prb=0;half_prb<(2*pucch_pdu->prb_size);half_prb++) {
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llr_num=_mm_set1_epi16(0);llr_den=_mm_set1_epi16(0);
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llr_num=_mm_set1_epi16(0);llr_den=_mm_set1_epi16(0);
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@@ -211,7 +211,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
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dlsch1_harq = dlsch[1]->harq_processes[codeword_TB1];
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dlsch1_harq = dlsch[1]->harq_processes[codeword_TB1];
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#ifdef DEBUG_HARQ
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#ifdef DEBUG_HARQ
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printf("[DEMOD] I am assuming only TB1 is active, it is in cw %d\n", dlsch0_harq->codeword);
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printf("[DEMOD] I am assuming only TB1 is active, it is in cw %d\n", dlsch1_harq->codeword);
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#endif
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#endif
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AssertFatal(1 == 0, "[UE][FATAL] DLSCH: TB0 not active and TB1 active case is not supported %d\n");
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AssertFatal(1 == 0, "[UE][FATAL] DLSCH: TB0 not active and TB1 active case is not supported %d\n");
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@@ -230,6 +230,9 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
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}
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}
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if (dlsch0_harq = NULL)
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AssertFatal(1 == 0, "Done\n");
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dlsch0_harq->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table);
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dlsch0_harq->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table);
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dlsch0_harq->R = nr_get_code_rate_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table);
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dlsch0_harq->R = nr_get_code_rate_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table);
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@@ -286,6 +286,8 @@ static void puschIQ (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_var
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fl_set_xyplot_data(graph,I,Q,sz,"","","");
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fl_set_xyplot_data(graph,I,Q,sz,"","","");
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// PUSCH I/Q of MF Output
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// PUSCH I/Q of MF Output
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// Code to fixed, disabled for cppcheck
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#if 0
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if (NULL) {
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if (NULL) {
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int32_t *pucch1ab_comp = (int32_t *) NULL; //phy_vars_gnb->pucch1ab_stats[UE_id];
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int32_t *pucch1ab_comp = (int32_t *) NULL; //phy_vars_gnb->pucch1ab_stats[UE_id];
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int32_t *pucch1_comp = (int32_t *) NULL; //phy_vars_gnb->pucch1_stats[UE_id];
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int32_t *pucch1_comp = (int32_t *) NULL; //phy_vars_gnb->pucch1_stats[UE_id];
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@@ -307,6 +309,7 @@ static void puschIQ (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_var
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fl_set_xyplot_xbounds(graph,-5000,5000);
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fl_set_xyplot_xbounds(graph,-5000,5000);
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fl_set_xyplot_ybounds(graph,0,80);
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fl_set_xyplot_ybounds(graph,0,80);
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}
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}
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#endif
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}
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}
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static void pucchEnergy (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) {
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static void pucchEnergy (FL_OBJECT *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id) {
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@@ -4111,12 +4111,13 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
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LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n", ue->Mod_id, frame_rx, nr_tti_rx, dci_cnt);
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LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n", ue->Mod_id, frame_rx, nr_tti_rx, dci_cnt);
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NR_UE_DLSCH_t *dlsch;
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NR_UE_DLSCH_t *dlsch = NULL;
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if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1){
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if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1){
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dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0];
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dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0];
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} else if (ue->dlsch_ra[0]->active == 1){
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} else if (ue->dlsch_ra[0]->active == 1){
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dlsch = ue->dlsch_ra[0];
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dlsch = ue->dlsch_ra[0];
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}
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}
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AssertFatal(dlsch != NULL, "Unsupported mode\n");
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uint8_t harq_pid = dlsch->current_harq_pid;
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uint8_t harq_pid = dlsch->current_harq_pid;
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NR_DL_UE_HARQ_t *dlsch0_harq = dlsch->harq_processes[harq_pid];
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NR_DL_UE_HARQ_t *dlsch0_harq = dlsch->harq_processes[harq_pid];
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uint16_t nb_symb_sch = dlsch0_harq->nb_symbols;
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uint16_t nb_symb_sch = dlsch0_harq->nb_symbols;
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@@ -91,7 +91,7 @@ void nr_get_prach_resources(module_id_t mod_id,
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NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon;
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NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon;
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// NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo
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// NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo
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int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3;
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int messagePowerOffsetGroupB = 0, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3 = 0;
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uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size;
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uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size;
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// NR_RSRP_Range_t rsrp_ThresholdSSB; // todo
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// NR_RSRP_Range_t rsrp_ThresholdSSB; // todo
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@@ -88,7 +88,7 @@ void nr_get_prach_resources(module_id_t mod_id,
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// NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo
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// NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo
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int messagePowerOffsetGroupB, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3;
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int messagePowerOffsetGroupB = 0, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3 = 0;
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uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, prach_ConfigIndex, SFN_nbr, Msg3_size;
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uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, prach_ConfigIndex, SFN_nbr, Msg3_size;
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AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id);
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AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id);
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@@ -934,7 +934,7 @@ void nr_ue_msg2_scheduler(module_id_t mod_id,
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// and if the slot is not among the PDCCH monitored ones (38.213 10.1)
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// and if the slot is not among the PDCCH monitored ones (38.213 10.1)
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while ((*msg2_slot > slot_limit) || ((*msg2_frame*nr_slots_per_frame[mu] + *msg2_slot - monitoring_offset) % monitoring_slot_period != 0)) {
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while ((*msg2_slot > slot_limit) || ((*msg2_frame*nr_slots_per_frame[mu] + *msg2_slot - monitoring_offset) % monitoring_slot_period != 0)) {
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if((*msg2_slot % tdd_period_slot) > 0)
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if((*msg2_slot % tdd_period_slot) > 0)
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*msg2_slot--;
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(*msg2_slot)--;
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else
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else
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AssertFatal(1 == 0, "No available DL slot to schedule reception of msg2 has been found");
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AssertFatal(1 == 0, "No available DL slot to schedule reception of msg2 has been found");
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}
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}
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@@ -225,7 +225,7 @@ void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot,
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// and if the slot is not among the PDCCH monitored ones (38.213 10.1)
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// and if the slot is not among the PDCCH monitored ones (38.213 10.1)
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while ((*msg2_slot>slot_limit) || ((*msg2_frame*nr_slots_per_frame[mu]+*msg2_slot-monitoring_offset)%monitoring_slot_period !=0)) {
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while ((*msg2_slot>slot_limit) || ((*msg2_frame*nr_slots_per_frame[mu]+*msg2_slot-monitoring_offset)%monitoring_slot_period !=0)) {
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if((*msg2_slot%tdd_period_slot) > 0)
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if((*msg2_slot%tdd_period_slot) > 0)
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*msg2_slot--;
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(*msg2_slot)--;
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else
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else
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AssertFatal(1==0,"No available DL slot to schedule msg2 has been found");
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AssertFatal(1==0,"No available DL slot to schedule msg2 has been found");
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}
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}
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