PUSCH DMRS generation is implemented
This commit is contained in:
committed by
Thomas Schlichter
parent
9b58180c88
commit
f3ebd69477
@@ -662,11 +662,14 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue,
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int i,j,k,l;
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int i,j,k,l,slot,symb,q;
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int eNB_id;
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int eNB_id;
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int th_id;
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int th_id;
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int n_ssb_crb=(fp->N_RB_DL-20);
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int n_ssb_crb=(fp->N_RB_DL-20);
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int k_ssb=0;
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int k_ssb=0;
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uint32_t ****pusch_dmrs;
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int N_n_scid[2] = {0,1}; // [HOTFIX] This is a temporary implementation of scramblingID0 and scramblingID1 which are given by DMRS-UplinkConfig
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int n_scid;
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abstraction_flag = 0;
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abstraction_flag = 0;
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fp->nb_antennas_tx = 1;
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fp->nb_antennas_tx = 1;
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fp->nb_antennas_rx=1;
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fp->nb_antennas_rx=1;
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@@ -698,6 +701,37 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue,
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ue->total_received_bits[eNB_id] = 0;
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ue->total_received_bits[eNB_id] = 0;
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}
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}
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/////////////////////////PUSCH DMRS init/////////////////////////
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///////////
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// default values until overwritten by RRCConnectionReconfiguration
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//------------- config DMRS parameters--------------//
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ue->dmrs_UplinkConfig.pusch_dmrs_type = pusch_dmrs_type1;
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ue->dmrs_UplinkConfig.pusch_dmrs_AdditionalPosition = pusch_dmrs_pos0;
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ue->dmrs_UplinkConfig.pusch_maxLength = pusch_len1;
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//-------------------------------------------------//
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ue->nr_gold_pusch_dmrs = (uint32_t ****)malloc16(fp->slots_per_frame*sizeof(uint32_t***));
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pusch_dmrs = ue->nr_gold_pusch_dmrs;
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n_scid = 0; // This quantity is indicated by higher layer parameter dmrs-SeqInitialization
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for (slot=0; slot<fp->slots_per_frame; slot++) {
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pusch_dmrs[slot] = (uint32_t ***)malloc16(fp->symbols_per_slot*sizeof(uint32_t**));
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AssertFatal(pusch_dmrs[slot]!=NULL, "init_nr_ue_signal: pusch_dmrs for slot %d - malloc failed\n", slot);
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for (symb=0; symb<fp->symbols_per_slot; symb++){
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pusch_dmrs[slot][symb] = (uint32_t **)malloc16(NR_MAX_NB_CODEWORDS*sizeof(uint32_t*));
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AssertFatal(pusch_dmrs[slot][symb]!=NULL, "init_nr_ue_signal: pusch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb);
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for (q=0; q<NR_MAX_NB_CODEWORDS; q++) {
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pusch_dmrs[slot][symb][q] = (uint32_t*)malloc16(NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD*sizeof(uint32_t));
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AssertFatal(pusch_dmrs[slot][symb][q]!=NULL, "init_nr_ue_signal: pusch_dmrs for slot %d symbol %d codeword %d - malloc failed\n", slot, symb, q);
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}
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}
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}
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nr_init_pusch_dmrs(ue, N_n_scid, n_scid);
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///////////
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////////////////////////////////////////////////////////////////////////////////////////////
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for (i=0;i<10;i++)
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for (i=0;i<10;i++)
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ue->tx_power_dBm[i]=-127;
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ue->tx_power_dBm[i]=-127;
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@@ -895,6 +929,7 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue,
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ue->pdsch_config_dedicated->p_a = dBm3;
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ue->pdsch_config_dedicated->p_a = dBm3;
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else
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else
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ue->pdsch_config_dedicated->p_a = dB0;
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ue->pdsch_config_dedicated->p_a = dB0;
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// set channel estimation to do linear interpolation in time
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// set channel estimation to do linear interpolation in time
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ue->high_speed_flag = 1;
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ue->high_speed_flag = 1;
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@@ -102,3 +102,32 @@ void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid)
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}
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}
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}
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}
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void nr_init_pusch_dmrs(PHY_VARS_NR_UE* ue, uint16_t *N_n_scid, uint8_t n_scid)
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{
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uint32_t x1, x2, n;
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uint8_t reset, slot, symb, q;
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NR_DL_FRAME_PARMS *fp = &ue->frame_parms;
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uint32_t ****pusch_dmrs = ue->nr_gold_pusch_dmrs;
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for (slot=0; slot<fp->slots_per_frame; slot++) {
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for (symb=0; symb<fp->symbols_per_slot; symb++) {
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for (q=0; q<NR_MAX_NB_CODEWORDS; q++) {
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reset = 1;
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x2 = ((1<<17) * (fp->symbols_per_slot*slot+symb+1) * ((N_n_scid[n_scid]<<1)+1) +((N_n_scid[n_scid]<<1)+n_scid));
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for (n=0; n<NR_MAX_PUSCH_DMRS_INIT_LENGTH_DWORD; n++) {
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pusch_dmrs[slot][symb][q][n] = lte_gold_generic(&x1, &x2, reset);
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reset = 0;
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}
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}
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}
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}
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}
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@@ -25,6 +25,7 @@
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#define __NR_REFSIG__H__
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#define __NR_REFSIG__H__
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#include "PHY/defs_gNB.h"
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#include "PHY/defs_gNB.h"
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#include "PHY/defs_nr_UE.h"
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#include "PHY/LTE_REFSIG/lte_refsig.h"
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#include "PHY/LTE_REFSIG/lte_refsig.h"
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@@ -38,5 +39,6 @@ void nr_init_pbch_dmrs(PHY_VARS_gNB* gNB);
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*/
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*/
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void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid);
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void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid);
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void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid);
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void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid);
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void nr_init_pusch_dmrs(PHY_VARS_NR_UE* ue, uint16_t *N_n_scid, uint8_t n_scid);
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#endif
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#endif
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@@ -294,8 +294,11 @@ for (int l=0; l<rel15->nb_layers; l++)
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uint16_t n_dmrs = (rel15->n_prb*rel15->nb_re_dmrs)<<1;
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uint16_t n_dmrs = (rel15->n_prb*rel15->nb_re_dmrs)<<1;
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int16_t mod_dmrs[n_dmrs<<1];
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int16_t mod_dmrs[n_dmrs<<1];
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uint8_t dmrs_type = config.pdsch_config.dmrs_type.value;
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uint8_t dmrs_type = config.pdsch_config.dmrs_type.value;
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l0 = get_l0(dmrs_type, 2);//config.pdsch_config.dmrs_typeA_position.value);
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uint8_t mapping_type = config.pdsch_config.mapping_type.value;
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l0 = get_l0(mapping_type, 2);//config.pdsch_config.dmrs_typeA_position.value);
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nr_modulation(pdsch_dmrs[l0][0], n_dmrs, MOD_QPSK, mod_dmrs); // currently only codeword 0 is modulated
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nr_modulation(pdsch_dmrs[l0][0], n_dmrs, MOD_QPSK, mod_dmrs); // currently only codeword 0 is modulated
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#ifdef DEBUG_DLSCH
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#ifdef DEBUG_DLSCH
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printf("DMRS modulation (single symbol %d, %d symbols, type %d):\n", l0, n_dmrs>>1, dmrs_type);
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printf("DMRS modulation (single symbol %d, %d symbols, type %d):\n", l0, n_dmrs>>1, dmrs_type);
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for (int i=0; i<n_dmrs>>4; i++) {
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for (int i=0; i<n_dmrs>>4; i++) {
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@@ -84,6 +84,6 @@ uint8_t get_delta(uint8_t ap, uint8_t config) {
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return ((config==NFAPI_NR_DMRS_TYPE1)?(pdsch_dmrs_1[ap][2]):(pdsch_dmrs_2[ap][2]));
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return ((config==NFAPI_NR_DMRS_TYPE1)?(pdsch_dmrs_1[ap][2]):(pdsch_dmrs_2[ap][2]));
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}
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}
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uint8_t get_l0(uint8_t config, uint8_t dmrs_typeA_position) {
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uint8_t get_l0(uint8_t mapping_type, uint8_t dmrs_typeA_position) {
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return ((config==NFAPI_NR_DMRS_TYPE1)?dmrs_typeA_position:0);
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return ((mapping_type==NFAPI_NR_PDSCH_MAPPING_TYPE_A)?dmrs_typeA_position:0);
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}
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}
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@@ -45,4 +45,4 @@ void get_Wf(int8_t *Wf, uint8_t ap, uint8_t config);
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uint8_t get_delta(uint8_t ap, uint8_t config);
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uint8_t get_delta(uint8_t ap, uint8_t config);
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uint8_t get_l0(uint8_t config, uint8_t dmrs_typeA_position);
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uint8_t get_l0(uint8_t mapping_type, uint8_t dmrs_typeA_position);
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@@ -983,6 +983,9 @@ typedef struct {
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/// PDCCH DMRS
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/// PDCCH DMRS
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uint32_t nr_gold_pdcch[7][20][3][52];
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uint32_t nr_gold_pdcch[7][20][3][52];
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/// PUSCH DMRS sequence
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uint32_t ****nr_gold_pusch_dmrs;
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uint32_t X_u[64][839];
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uint32_t X_u[64][839];
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uint32_t high_speed_flag;
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uint32_t high_speed_flag;
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@@ -74,9 +74,12 @@
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/*used for the resource mapping*/
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/*used for the resource mapping*/
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#define NR_MAX_PDCCH_DMRS_LENGTH 576 // 16(L)*2(QPSK)*3(3 DMRS symbs per REG)*6(REG per CCE)
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#define NR_MAX_PDCCH_DMRS_LENGTH 576 // 16(L)*2(QPSK)*3(3 DMRS symbs per REG)*6(REG per CCE)
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#define NR_MAX_PDSCH_DMRS_LENGTH 3300 //275*6(k)*2(QPSK)
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#define NR_MAX_PDSCH_DMRS_LENGTH 3300 //275*6(k)*2(QPSK real+imag)
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#define NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD 104 // ceil(NR_MAX_PDSCH_DMRS_LENGTH/32)
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#define NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD 104 // ceil(NR_MAX_PDSCH_DMRS_LENGTH/32)
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#define NR_MAX_PUSCH_DMRS_LENGTH NR_MAX_PDSCH_DMRS_LENGTH
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#define NR_MAX_PUSCH_DMRS_INIT_LENGTH_DWORD NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD
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#define NR_MAX_DCI_PAYLOAD_SIZE 64
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#define NR_MAX_DCI_PAYLOAD_SIZE 64
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#define NR_MAX_DCI_SIZE 1728 //16(L)*2(QPSK)*9(12 RE per REG - 3(DMRS))*6(REG per CCE)
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#define NR_MAX_DCI_SIZE 1728 //16(L)*2(QPSK)*9(12 RE per REG - 3(DMRS))*6(REG per CCE)
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#define NR_MAX_DCI_SIZE_DWORD 54 // ceil(NR_MAX_DCI_SIZE/32)
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#define NR_MAX_DCI_SIZE_DWORD 54 // ceil(NR_MAX_DCI_SIZE/32)
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@@ -145,7 +145,7 @@ int main(int argc, char **argv) {
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uint16_t N_RB_DL = 106, N_RB_UL = 106, mu = 1;
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uint16_t N_RB_DL = 106, N_RB_UL = 106, mu = 1;
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//unsigned char frame_type = 0;
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//unsigned char frame_type = 0;
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unsigned char pbch_phase = 0;
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unsigned char pbch_phase = 0;
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int frame = 0, subframe = 0;
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int frame = 0, subframe = 0, slot = 1;
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int frame_length_complex_samples;
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int frame_length_complex_samples;
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NR_DL_FRAME_PARMS *frame_parms;
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NR_DL_FRAME_PARMS *frame_parms;
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uint32_t Nsoft = 0;
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uint32_t Nsoft = 0;
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@@ -158,6 +158,12 @@ int main(int argc, char **argv) {
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uint16_t nb_symb_sch = 12;
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uint16_t nb_symb_sch = 12;
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uint16_t nb_rb = 50;
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uint16_t nb_rb = 50;
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uint8_t Imcs = 9;
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uint8_t Imcs = 9;
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uint16_t n_dmrs;
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uint8_t dmrs_TypeA_Position;
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int l0;
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uint32_t ***pusch_dmrs;
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PUSCH_TimeDomainResourceAllocation_t pusch_time_alloc;
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cpuf = get_cpu_freq_GHz();
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cpuf = get_cpu_freq_GHz();
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@@ -453,6 +459,12 @@ int main(int argc, char **argv) {
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TBS = nr_compute_tbs(Imcs, nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, Nl);
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TBS = nr_compute_tbs(Imcs, nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, Nl);
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printf("available bits %d TBS %d mod_order %d\n", available_bits, TBS, mod_order);
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printf("available bits %d TBS %d mod_order %d\n", available_bits, TBS, mod_order);
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/////////// setting PUSCH_TimeDomainResourceAllocation_t parameters ///////////
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pusch_time_alloc.mappingType = typeA;
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///////////////////////////////////////////////////
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/////////// setting rel15_ul parameters ///////////
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/////////// setting rel15_ul parameters ///////////
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rel15_ul->number_rbs = nb_rb;
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rel15_ul->number_rbs = nb_rb;
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rel15_ul->number_symbols = nb_symb_sch;
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rel15_ul->number_symbols = nb_symb_sch;
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@@ -565,9 +577,23 @@ int main(int argc, char **argv) {
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///////////
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///////////
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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for (SNR = snr0; SNR < snr1; SNR += snr_step) {
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/////////////////////////PUSCH DMRS/////////////////////////
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n_errors = 0;
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///////////
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n_false_positive = 0;
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pusch_dmrs = UE->nr_gold_pusch_dmrs[slot];
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dmrs_TypeA_Position = 2; // This parameter is given by dmrs_TypeA_Position which is located in MIB.
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n_dmrs = nb_re_dmrs<<1;
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int16_t mod_dmrs[n_dmrs<<1];
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l0 = get_l0(pusch_time_alloc.mappingType, dmrs_TypeA_Position);//config.pdsch_config.dmrs_typeA_position.value);
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nr_modulation(pusch_dmrs[l0][0], n_dmrs, MOD_QPSK, mod_dmrs); // currently only codeword 0 is modulated
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///////////
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////////////////////////////////////////////////////////////////////////
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for (SNR = snr0; SNR < snr1; SNR += snr_step) {
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n_errors = 0;
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n_false_positive = 0;
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for (trial = 0; trial < n_trials; trial++) {
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for (trial = 0; trial < n_trials; trial++) {
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