added hotfix for DCCH bad size limitation (to be checked after merge with develop). Changed UL idle scheduling to improve 5MHz performance, changed DCI aggregation for ue-specific DCIs (reduces contention with SI and RA in subframe 5 for 5 MHz). Added RRC timer for UE release which cleans L1. Still issues in 10 MHz throughput with TCP. 5 MHz seems almost fine.

This commit is contained in:
gauthier
2016-03-23 21:15:49 +01:00
parent 26f5d0d93d
commit f79b0e7d9b
7 changed files with 18 additions and 7 deletions
+2 -1
View File
@@ -2980,8 +2980,9 @@ void prach_procedures(PHY_VARS_eNB *phy_vars_eNB,uint8_t sched_subframe,uint8_t
mac_xface->macphy_exit("Exiting for PRACH debug\n");
*/
UE_id = find_next_ue_index(phy_vars_eNB);
UE_id = find_next_ue_index(phy_vars_eNB);
if (UE_id>=0) {
phy_vars_eNB->eNB_UE_stats[(uint32_t)UE_id].UE_timing_offset = preamble_delay_list[preamble_max]&0x1FFF; //limit to 13 (=11+2) bits
//phy_vars_eNb->eNB_UE_stats[(uint32_t)UE_id].mode = PRACH;