added hotfix for DCCH bad size limitation (to be checked after merge with develop). Changed UL idle scheduling to improve 5MHz performance, changed DCI aggregation for ue-specific DCIs (reduces contention with SI and RA in subframe 5 for 5 MHz). Added RRC timer for UE release which cleans L1. Still issues in 10 MHz throughput with TCP. 5 MHz seems almost fine.
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@@ -2980,8 +2980,9 @@ void prach_procedures(PHY_VARS_eNB *phy_vars_eNB,uint8_t sched_subframe,uint8_t
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mac_xface->macphy_exit("Exiting for PRACH debug\n");
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*/
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UE_id = find_next_ue_index(phy_vars_eNB);
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UE_id = find_next_ue_index(phy_vars_eNB);
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if (UE_id>=0) {
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phy_vars_eNB->eNB_UE_stats[(uint32_t)UE_id].UE_timing_offset = preamble_delay_list[preamble_max]&0x1FFF; //limit to 13 (=11+2) bits
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//phy_vars_eNb->eNB_UE_stats[(uint32_t)UE_id].mode = PRACH;
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