PreProc IF: Freq domain allocation per UE
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@@ -427,6 +427,7 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_list->UE_sched_ctrl[UE_id];
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_list->UE_sched_ctrl[UE_id];
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// TODO: reset per UE-info
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// TODO: reset per UE-info
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sched_ctrl->rbSize = 0;
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/* Retrieve amount of data to send for this UE */
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/* Retrieve amount of data to send for this UE */
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sched_ctrl->num_total_bytes = 0;
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sched_ctrl->num_total_bytes = 0;
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@@ -480,6 +481,11 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
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// Time-domain allocation
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// Time-domain allocation
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sched_ctrl->time_domain_allocation = 2;
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sched_ctrl->time_domain_allocation = 2;
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// Freq-demain allocation
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const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
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sched_ctrl->rbSize = bwpSize;
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sched_ctrl->rbStart = 0;
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}
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}
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void nr_schedule_ue_spec(module_id_t module_id,
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void nr_schedule_ue_spec(module_id_t module_id,
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@@ -499,14 +505,9 @@ void nr_schedule_ue_spec(module_id_t module_id,
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const int CC_id = 0;
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const int CC_id = 0;
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_list->UE_sched_ctrl[UE_id];
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_list->UE_sched_ctrl[UE_id];
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if (sched_ctrl->num_total_bytes == 0 && !get_softmodem_params()->phy_test)
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if (sched_ctrl->rbSize < 0 && !get_softmodem_params()->phy_test)
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return;
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return;
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//if (sched_ctrl->rbSize < 0 && !get_softmodem_params()->phy_test)
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// return;
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const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth,275);
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const uint8_t mcs = 9;
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const uint8_t mcs = 9;
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const int nrOfLayers = 1;
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const int nrOfLayers = 1;
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const uint8_t numDmrsCdmGrpsNoData = 1;
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const uint8_t numDmrsCdmGrpsNoData = 1;
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@@ -535,14 +536,13 @@ void nr_schedule_ue_spec(module_id_t module_id,
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}
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}
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const uint8_t N_sh_symb = nrOfSymbols;
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const uint8_t N_sh_symb = nrOfSymbols;
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const uint16_t rbSize = bwpSize;
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const uint8_t table_idx = 0;
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const uint8_t table_idx = 0;
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const uint16_t R = nr_get_code_rate_dl(mcs, table_idx);
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const uint16_t R = nr_get_code_rate_dl(mcs, table_idx);
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const uint8_t Qm = nr_get_Qm_dl(mcs, table_idx);
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const uint8_t Qm = nr_get_Qm_dl(mcs, table_idx);
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const uint32_t TBS =
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const uint32_t TBS =
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nr_compute_tbs(Qm,
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nr_compute_tbs(Qm,
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R,
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R,
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rbSize,
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sched_ctrl->rbSize,
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N_sh_symb,
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N_sh_symb,
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N_PRB_DMRS, // FIXME // This should be multiplied by the
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N_PRB_DMRS, // FIXME // This should be multiplied by the
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// number of dmrs symbols
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// number of dmrs symbols
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@@ -550,7 +550,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
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0 /* tb_scaling */,
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0 /* tb_scaling */,
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nrOfLayers)
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nrOfLayers)
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>> 3;
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>> 3;
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AssertFatal(TBS != 0, "TBS is zero but requested %d RBs!\n", rbSize);
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AssertFatal(TBS != 0, "TBS is zero but requested %d RBs!\n", sched_ctrl->rbSize);
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LOG_D(MAC,
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LOG_D(MAC,
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"TBS %d bytes: N_PRB_DMRS %d N_sh_symb %d N_PRB_oh %d R %d Qm %d table %d",
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"TBS %d bytes: N_PRB_DMRS %d N_sh_symb %d N_PRB_oh %d R %d Qm %d table %d",
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TBS,
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TBS,
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@@ -670,8 +670,8 @@ void nr_schedule_ue_spec(module_id_t module_id,
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pucch,
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pucch,
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nrOfLayers,
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nrOfLayers,
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mcs,
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mcs,
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rbSize,
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sched_ctrl->rbSize,
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0 /* bwpStart */,
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sched_ctrl->rbStart,
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numDmrsCdmGrpsNoData,
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numDmrsCdmGrpsNoData,
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dmrsConfigType,
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dmrsConfigType,
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table_idx,
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table_idx,
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@@ -301,6 +301,10 @@ typedef struct {
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int cce_index;
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int cce_index;
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uint8_t aggregation_level;
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uint8_t aggregation_level;
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/// RB allocation within active BWP
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uint16_t rbSize;
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uint16_t rbStart;
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// time-domain allocation for scheduled RBs
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// time-domain allocation for scheduled RBs
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int time_domain_allocation;
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int time_domain_allocation;
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