merge develop
This commit is contained in:
Laurent Thomas
@@ -77,6 +77,7 @@
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#define CONFIG_HLP_UE "Set the lte softmodem as a UE\n"
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#define CONFIG_HLP_L2MONW "Enable L2 wireshark messages on localhost \n"
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#define CONFIG_HLP_L2MONP "Enable L2 pcap messages on localhost \n"
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#define CONFIG_HLP_MAC "Disable the MAC procedures at UE side (default is enabled)\n"
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#define CONFIG_HLP_VCD "Enable VCD (generated file will is named openair_dump_eNB.vcd, read it with target/RT/USER/eNB.gtkw\n"
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#define CONFIG_HLP_TQFS "Apply three-quarter of sampling frequency, 23.04 Msps to reduce the data rate on USB/PCIe transfers (only valid for 20 MHz)\n"
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#define CONFIG_HLP_TPORT "tracer port\n"
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+9
-72
@@ -18,49 +18,16 @@
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* For more information about the OpenAirInterface (OAI) Software Alliance:
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* contact@openairinterface.org
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*/
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#include "executables/thread-common.h"
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#include "executables/nr-uesoftmodem.h"
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#include "NR_MAC_UE/mac.h"
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//#include "RRC/LTE/rrc_extern.h"
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#include "PHY_INTERFACE/phy_interface_extern.h"
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#undef MALLOC //there are two conflicting definitions, so we better make sure we don't use it at all
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//#undef FRAME_LENGTH_COMPLEX_SAMPLES //there are two conflicting definitions, so we better make sure we don't use it at all
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#include "fapi_nr_ue_l1.h"
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#include "PHY/phy_extern_nr_ue.h"
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#include "PHY/INIT/phy_init.h"
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#include "PHY/MODULATION/modulation_UE.h"
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#include "NR_MAC_UE/mac_proto.h"
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#include "RRC/NR_UE/rrc_proto.h"
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#include "SCHED_NR_UE/phy_frame_config_nr.h"
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#include "SCHED_NR_UE/defs.h"
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#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
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#include "common/utils/LOG/log.h"
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#include "common/utils/system.h"
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#include "common/utils/LOG/vcd_signal_dumper.h"
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#include "executables/nr-softmodem.h"
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#include "T.h"
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#ifdef XFORMS
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#include "PHY/TOOLS/nr_phy_scope.h"
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extern char do_forms;
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#endif
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// Missing stuff?
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int next_ra_frame = 0;
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module_id_t next_Mod_id = 0;
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extern double cpuf;
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//static nfapi_nr_config_request_t config_t;
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//static nfapi_nr_config_request_t* config =&config_t;
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/*
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* NR SLOT PROCESSING SEQUENCE
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*
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@@ -124,16 +91,12 @@ extern double cpuf;
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#define DURATION_RX_TO_TX (6) /* For LTE, this duration is fixed to 4 and it is linked to LTE standard for both modes FDD/TDD */
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#endif
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#define FRAME_PERIOD 100000000ULL
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#define DAQ_PERIOD 66667ULL
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typedef enum {
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pss=0,
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pbch=1,
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si=2
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pss = 0,
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pbch = 1,
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si = 2
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} sync_mode_t;
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void init_nr_ue_vars(PHY_VARS_NR_UE *ue,
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uint8_t UE_id,
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uint8_t abstraction_flag)
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@@ -258,7 +221,7 @@ static void UE_synch(void *arg) {
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double rx_gain_off = 0;
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nr_get_carrier_frequencies(&UE->frame_parms, &dl_carrier, &ul_carrier);
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if (nr_initial_sync( &syncD->proc, UE, UE->mode,2) == 0) {
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if (nr_initial_sync(&syncD->proc, UE, 2) == 0) {
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freq_offset = UE->common_vars.freq_offset; // frequency offset computed with pss in initial sync
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hw_slot_offset = ((UE->rx_offset<<1) / UE->frame_parms.samples_per_subframe * UE->frame_parms.slots_per_subframe) +
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round((float)((UE->rx_offset<<1) % UE->frame_parms.samples_per_subframe)/UE->frame_parms.samples_per_slot0);
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@@ -394,26 +357,17 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
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if(UE->if_inst != NULL && UE->if_inst->dl_indication != NULL) {
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nr_downlink_indication_t dl_indication;
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memset((void*)&dl_indication, 0, sizeof(dl_indication));
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dl_indication.module_id = UE->Mod_id;
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dl_indication.gNB_index = gNB_id;
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dl_indication.cc_id = UE->CC_id;
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dl_indication.frame = proc->frame_rx;
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dl_indication.slot = proc->nr_slot_rx;
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dl_indication.thread_id = proc->thread_id;
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nr_fill_dl_indication(&dl_indication, NULL, NULL, proc, UE, gNB_id);
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UE->if_inst->dl_indication(&dl_indication, NULL);
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}
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// Process Rx data for one sub-frame
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#ifdef UE_SLOT_PARALLELISATION
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phy_procedures_slot_parallelization_nrUE_RX( UE, proc, 0, 0, 1, UE->mode, no_relay, NULL );
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phy_procedures_slot_parallelization_nrUE_RX( UE, proc, 0, 0, 1, no_relay, NULL );
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#else
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uint64_t a=rdtsc();
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phy_procedures_nrUE_RX( UE, proc, 0, UE->mode,get_nrUE_params()->nr_dlsch_parallel);
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LOG_D(PHY,"phy_procedures_nrUE_RX: slot:%d, time %lu\n", proc->nr_slot_rx, (rdtsc()-a)/3500);
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//printf(">>> nr_ue_pdcch_procedures ended\n");
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phy_procedures_nrUE_RX(UE, proc, gNB_id, get_nrUE_params()->nr_dlsch_parallel);
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LOG_D(PHY, "In %s: slot %d, time %lu\n", __FUNCTION__, proc->nr_slot_rx, (rdtsc()-a)/3500);
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#endif
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if(IS_SOFTMODEM_NOS1){
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@@ -424,23 +378,6 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
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}
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}
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// no UL for now
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/*
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if (UE->mac_enabled==1) {
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// trigger L2 to run ue_scheduler thru IF module
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// [TODO] mapping right after NR initial sync
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if(UE->if_inst != NULL && UE->if_inst->ul_indication != NULL) {
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UE->ul_indication.module_id = 0;
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UE->ul_indication.gNB_index = 0;
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UE->ul_indication.cc_id = 0;
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UE->ul_indication.frame = proc->frame_rx;
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UE->ul_indication.slot = proc->nr_slot_rx;
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UE->ul_indication.thread_id = proc->thread_id;
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UE->if_inst->ul_indication(&UE->ul_indication);
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}
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}
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*/
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}
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/*!
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@@ -283,7 +283,6 @@ void set_options(int CC_id, PHY_VARS_NR_UE *UE){
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tx_gain[0][CC_id] = tx_gain[0][0];
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// Set UE variables
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UE->rx_total_gain_dB = (int)rx_gain[CC_id][0] + rx_gain_off;
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UE->tx_total_gain_dB = (int)tx_gain[CC_id][0];
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UE->tx_power_max_dBm = tx_max_power[CC_id];
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@@ -50,15 +50,15 @@
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{"ue-rxgain", CONFIG_HLP_UERXG, 0, dblptr:&(rx_gain[0][0]), defdblval:0, TYPE_DOUBLE, 0}, \
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{"ue-rxgain-off", CONFIG_HLP_UERXGOFF, 0, dblptr:&rx_gain_off, defdblval:0, TYPE_DOUBLE, 0}, \
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{"ue-txgain", CONFIG_HLP_UETXG, 0, dblptr:&(tx_gain[0][0]), defdblval:0, TYPE_DOUBLE, 0}, \
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{"ue-nb-ant-rx", CONFIG_HLP_UENANTR, 0, u8ptr:&(fp->nb_antennas_rx), defuintval:1, TYPE_UINT8, 0}, \
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{"ue-nb-ant-tx", CONFIG_HLP_UENANTT, 0, u8ptr:&(fp->nb_antennas_tx), defuintval:1, TYPE_UINT8, 0}, \
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{"ue-nb-ant-rx", CONFIG_HLP_UENANTR, 0, u8ptr:&(fp->nb_antennas_rx), defuintval:1, TYPE_UINT8, 0}, \
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{"ue-nb-ant-tx", CONFIG_HLP_UENANTT, 0, u8ptr:&(fp->nb_antennas_tx), defuintval:1, TYPE_UINT8, 0}, \
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{"ue-scan-carrier", CONFIG_HLP_UESCAN, PARAMFLAG_BOOL, iptr:&(UE->UE_scan_carrier), defintval:0, TYPE_INT, 0}, \
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{"ue-fo-compensation", CONFIG_HLP_UEFO, PARAMFLAG_BOOL, iptr:&(UE->UE_fo_compensation), defintval:0, TYPE_INT, 0}, \
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{"ue-max-power", NULL, 0, iptr:&(tx_max_power[0]), defintval:90, TYPE_INT, 0}, \
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{"r" , CONFIG_HLP_PRB, 0, iptr:&(fp->N_RB_DL), defintval:25, TYPE_UINT, 0}, \
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{"A" , CONFIG_HLP_TADV, 0, iptr:&(UE->timing_advance), defintval:0, TYPE_INT, 0}, \
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{"A" , CONFIG_HLP_TADV, 0, iptr:&(UE->timing_advance), defintval:0, TYPE_INT, 0}, \
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{"E" , CONFIG_HLP_TQFS, PARAMFLAG_BOOL, u8ptr:&(fp->threequarter_fs), defintval:0, TYPE_UINT8, 0}, \
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{"T" , CONFIG_HLP_TDD, PARAMFLAG_BOOL, iptr:&tddflag, defintval:0, TYPE_INT, 0}, \
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{"T" , CONFIG_HLP_TDD, PARAMFLAG_BOOL, iptr:&tddflag, defintval:0, TYPE_INT, 0}, \
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{"ue-timing-correction-disable", CONFIG_HLP_DISABLETIMECORR, PARAMFLAG_BOOL, iptr:&(UE->no_timing_correction), defintval:0, TYPE_INT, 0}, \
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}
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