From fa7c143b70515d6a860cff19ff97d2276aa81d38 Mon Sep 17 00:00:00 2001 From: Raymond Knopp Date: Tue, 3 Dec 2019 22:32:29 +0100 Subject: [PATCH] nr=softmodem compiles. --- nfapi/oai_integration/nfapi_vnf.c | 8 +- .../nfapi/public_inc/nfapi_nr_interface.h | 253 +----------- .../nfapi/public_inc/nfapi_nr_interface_scf.h | 389 ++++++++++++++---- .../vnf/public_inc/nfapi_vnf_interface.h | 5 +- nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_dci.c | 4 +- openair1/PHY/NR_TRANSPORT/nr_dci.h | 4 +- openair1/PHY/NR_TRANSPORT/nr_dci_tools.c | 11 +- openair1/PHY/NR_TRANSPORT/nr_dlsch.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_dlsch.h | 8 +- openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c | 2 +- openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c | 6 +- openair1/PHY/NR_TRANSPORT/nr_pbch.c | 4 +- openair1/PHY/NR_TRANSPORT/nr_transport.h | 2 +- .../PHY/NR_UE_TRANSPORT/nr_transport_ue.h | 2 +- openair1/PHY/defs_gNB.h | 8 +- openair1/PHY/defs_nr_common.h | 1 + openair1/SCHED_NR/fapi_nr_l1.c | 90 ++-- openair1/SCHED_NR/fapi_nr_l1.h | 5 +- openair1/SCHED_NR/phy_procedures_nr_gNB.c | 15 +- openair1/SCHED_NR/sched_nr.h | 12 - openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c | 41 +- .../LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c | 85 ++-- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 159 ++++--- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 133 +++--- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 15 +- openair2/LAYER2/NR_MAC_gNB/main.c | 10 - openair2/LAYER2/NR_MAC_gNB/nr_mac_common.c | 4 +- openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h | 12 +- openair2/NR_PHY_INTERFACE/NR_IF_Module.c | 9 +- openair2/NR_PHY_INTERFACE/NR_IF_Module.h | 8 +- 31 files changed, 634 insertions(+), 675 deletions(-) diff --git a/nfapi/oai_integration/nfapi_vnf.c b/nfapi/oai_integration/nfapi_vnf.c index a0574221f5..64cd47dcd2 100644 --- a/nfapi/oai_integration/nfapi_vnf.c +++ b/nfapi/oai_integration/nfapi_vnf.c @@ -1169,7 +1169,7 @@ int oai_nfapi_dl_config_req(nfapi_dl_config_request_t *dl_config_req) { return retval; } -int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req) +int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_tti_request_t *dl_config_req) { nfapi_vnf_p7_config_t *p7_config = vnf.p7_vnfs[0].config; @@ -1177,9 +1177,9 @@ int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req) int retval = nfapi_vnf_p7_nr_dl_config_req(p7_config, dl_config_req); - dl_config_req->dl_config_request_body.number_dci = 0; - dl_config_req->dl_config_request_body.number_pdu = 0; - dl_config_req->dl_config_request_body.number_pdsch_rnti = 0; + dl_config_req->dl_tti_request_body.nPDUs = 0; + dl_config_req->dl_tti_request_body.nGroup = 0; + if (retval!=0) { LOG_E(PHY, "%s() Problem sending retval:%d\n", __FUNCTION__, retval); diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h index c55ce3b119..13a46ebbc0 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h @@ -11,7 +11,6 @@ #include "nfapi_interface.h" - #define NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS 5 #define NFAPI_NR_MAX_NB_TCI_STATES_PDCCH 64 #define NFAPI_NR_MAX_NB_CORESETS 12 @@ -39,12 +38,7 @@ typedef struct { } nfapi_uint64_tlv_t; // nFAPI enums -typedef enum { - NFAPI_NR_DL_CONFIG_PDCCH_PDU_TYPE = 0, - NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE, - NFAPI_NR_DL_CONFIG_PDSCH_PDU_TYPE, - NFAPI_NR_DL_CONFIG_PCH_PDU_TYPE, -} nfapi_nr_dl_config_pdu_type_e; + //These TLVs are used exclusively by nFAPI @@ -104,37 +98,6 @@ typedef struct // P5 Message Structures -typedef struct{ - nfapi_tl_t tl; - uint16_t corset_ID; ///// L1 parameter 'CORESET-ID' - uint16_t freq_dom; ///// L1 parameter 'CORESET-freq-dom' - uint16_t duration; ///// L1 parameter 'CORESET-time-duration' - uint16_t reg_type; ///// L1 parameter 'CORESET-CCE-REG-mapping-type' - uint16_t reg_bundlesize; ///// L1 parameter 'CORESET-REG-bundle-size' - uint16_t interleaversize; ///// L1 parameter 'CORESET-interleaver-size' - uint16_t shiftindex; ///// L1 parameter 'CORESET-shift-index' - uint16_t precodergranularity; ///// L1 parameter 'CORESET-precoder-granuality' - uint16_t tci_stateId; ///// L1 parameter 'TCI-StatesPDCCH' - uint16_t tci_present; ///// L1 parameter 'TCI-PresentInDCI' - uint16_t dmrs_scramblingID; ///// L1 parameter 'PDCCH-DMRS-Scrambling-ID' -} nfapi_nr_ControlResourcesSet_t; - -typedef struct{ - nfapi_tl_t tl; - nfapi_nr_ControlResourcesSet_t coreset; - uint16_t monitoringSlotPeriodicityAndOffset; ///// L1 parameters 'Montoring-periodicity-PDCCH-slot' - uint16_t monitoringSymbolsWithinSlot; ///// L1 parameter 'Montoring-symbols-PDCCH-within-slot' - uint16_t nrofCand_aggLevel1; ///// L1 parameter 'Aggregation-level-1' - uint16_t nrofCand_aggLevel2; ///// L1 parameter 'Aggregation-level-2' - uint16_t nrofCand_aggLevel4; ///// L1 parameter 'Aggregation-level-4' - uint16_t nrofCand_aggLevel8; ///// L1 parameter 'Aggregation-level-8' - uint16_t nrofCand_aggLevel16; ///// L1 parameter 'Aggregation-level-16' - uint16_t sfi_agg_fmt2_0; ///// L1 parameters 'SFI-Num-PDCCH-cand' and 'SFI-Aggregation-Level' - uint16_t monitoringperiodicity_fmt2_3; ///// L1 parameter 'SRS-monitoring-periodicity' - uint16_t nrof_candidates_fmt_2_3; ///// L1 parameter 'SRS-Num-PDCCH-cand' -} nfapi_nr_SearchSpace_t; - - typedef struct { nfapi_uint16_tlv_t numerology_index_mu; nfapi_uint16_tlv_t duplex_mode; @@ -523,16 +486,7 @@ uint16_t padding; */ //#define NFAPI_NR_DL_CONFIG_REQUEST_DCI_DL_PDU_REL15_TAG 0x???? -typedef struct { - /// Number of PRGs spanning this allocation. Value : 1->275 - uint16_t numPRGs; - /// Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275 - uint16_t prgSize; - /// Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255 - uint8_t digBFInterfaces; - uint16_t PMIdx[275]; - uint16_t *beamIdx[275]; -} nr_beamforming_t; + /* typedef struct{ @@ -568,7 +522,7 @@ typedef struct{ uint32_t monitoring_symbols_in_slot; uint16_t number_of_candidates[NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS]; } nfapi_nr_search_space_t; -*/ + typedef struct { nfapi_tl_t tl; @@ -600,206 +554,7 @@ typedef struct { nfapi_bf_vector_t bf_vector; } nfapi_nr_dl_config_pdcch_parameters_rel15_t; -#define MAX_DCI_CORESET 8 -#define DCI_PAYLOAD_BYTE_LEN 8 - -typedef struct { - ///Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP,Value: 1->275 - uint16_t BWPSize; - ///bandwidth part start RB index from reference CRB, [TS38.213 sec 12], Value: 0->274 - uint16_t BWPStart; - ///subcarrierSpacing [TS38.211 sec 4.2], Value:0->4 - uint8_t SubcarrierSpacing; - ///Cyclic prefix type [TS38.211 sec 4.2], 0: Normal; 1: Extended - uint8_t CyclicPrefix; - ///Starting OFDM symbol for the CORESET, Value: 0->13 - uint8_t StartSymbolIndex; -///Contiguous time duration of the CORESET in number of symbols. Corresponds to L1 parameter π‘π‘ π‘¦π‘šπ‘_𝐢𝑂𝑅𝐸𝑆𝐸𝑇 [TS38.211 sec 7.3.2.2] Value: 1,2,3 - uint8_t DurationSymbols; - ///Frequency domain resources. This is a bitmap defining non-overlapping groups of 6 PRBs in ascending order. [TS38.213 10.1]. Also, corresponds to L1 parameter CORE SET RB N [TS38.211 sec 7.3.2.2] Bitmap of uint8 array. 45 bits. - uint8_t FreqDomainResource[6]; - ///CORESET-CCE-to-REG-mapping-type [TS38.211 sec 7.3.2.2] 0: non-interleaved 1: interleaved - uint8_t CceRegMappingType; - ///The number of REGs in a bundle. Must be 6 for cceRegMappingType = nonInterleaved. For cceRegMappingType = interleaved, must belong to {2,6} if duration = 1,2 and must belong to {3,6} if duration = 3. Corresponds to parameter L. [TS38.211 sec 7.3.2.2] Value: 2,3,6 - uint8_t RegBundleSize; - ///The interleaver size. For interleaved mapping belongs to {2,3,6} and for non-interleaved mapping is NA. Corresponds to parameter R. [TS38.211 sec 7.3.2.2] Value: 2,3,6 CoreSetType - uint8_t InterleaverSize; - ///[TS38.211 sec 7.3.2.2 and sec 7.4.1.3.2] 0: CORESET is configured by the PBCH or SIB1 (subcarrier 0 of CRB0 for DMRS mapping) 1: otherwise (subcarrier 0 of CORESET) - uint8_t CoreSetType; - ///[TS38.211 sec 7.3.2.2] Not applicable for non-interleaved mapping. For interleaved mapping and a PDCCH transmitted in a CORESET configured by the PBCH or SIB1 this should be set to phy cell ID. Value: 10 bits Otherwise, for interleaved mapping this is set to 0-> max num of PRBs. Value 0-> 275 - uint16_t ShiftIndex; - ///Granularity of precoding [TS38.211 sec 7.3.2.2] Field Type Description 0: sameAsRegBundle 1: allContiguousRBs - uint8_t precoderGranularity; - ///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot - uint16_t numDlDci; - ///The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535. - uint16_t RNTI[MAX_DCI_CORESET]; - ///For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535 - uint16_t ScramblingId[MAX_DCI_CORESET]; - ///For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535 - uint16_t ScramblingRNTI[MAX_DCI_CORESET]; - ///CCE start Index used to send the DCI Value: 0->135 - uint8_t CceIndex[MAX_DCI_CORESET]; - ///Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16 - uint8_t AggregationLevel[MAX_DCI_CORESET]; - ///Precoding and Beamforming structure See Table 3-43 - nr_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET]; - ///PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps - uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET]; - ///PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB - uint8_t powerControlOffsetSS[MAX_DCI_CORESET]; -///The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BTYE_LEN*8 - uint16_t PayloadSizeBits[MAX_DCI_CORESET]; - ///DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB - uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN]; -} nfapi_nr_dl_config_pdcch_pdu_rel15_t; - -typedef struct { - nfapi_tl_t tl; - uint16_t length; - int16_t pdu_index; - uint16_t transmission_power; -} nfapi_nr_dl_config_bch_pdu_rel15_t; -#define NFAPI_NR_DL_CONFIG_REQUEST_BCH_PDU_REL15_TAG 0x5025 - -typedef struct { - nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15; -} nfapi_nr_dl_config_bch_pdu; - - - -typedef struct { - nfapi_tl_t tl; - uint16_t pduBitmap; - uint16_t rnti; - uint16_t pduIndex; - // BWP [TS38.213 sec 12] - /// Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP, Value: 1->275 - uint16_t BWPSize; - /// bandwidth part start RB index from reference CRB [TS38.213 sec 12],Value: 0->274 - uint16_t BWPStart; - /// subcarrierSpacing [TS38.211 sec 4.2], Value:0->4 - uint8_t SubcarrierSpacing; - /// Cyclic prefix type [TS38.211 sec 4.2], 0: Normal; 1: Extended - uint8_t CyclicPrefix; - // Codeword information - /// Number of code words for this RNTI (UE), Value: 1 -> 2 - uint8_t NrOfCodewords; - /// Target coding rate [TS38.212 sec 5.4.2.1 and 38.214 sec 5.1.3.1]. This is the number of information bits per 1024 coded bits expressed in 0.1 bit units - uint16_t targetCodeRate[2]; - /// QAM modulation [TS38.212 sec 5.4.2.1 and 38.214 sec 5.1.3.1], Value: 2,4,6,8 - uint8_t qamModOrder[2]; - /// MCS index [TS38.214, sec 5.1.3.1], should match value sent in DCI Value : 0->31 - uint8_t mcsIndex[2]; - /// MCS-Table-PDSCH [TS38.214, sec 5.1.3.1] 0: notqam256, 1: qam256, 2: qam64LowSE - uint8_t mcsTable[2]; - /// Redundancy version index [TS38.212, Table 5.4.2.1-2 and 38.214, Table 5.1.2.1-2], should match value sent in DCI Value : 0->3 - uint8_t rvIndex[2]; - /// Transmit block size (in bytes) [TS38.214 sec 5.1.3.2], Value: 0->65535 - uint32_t TBSize[2]; - /// dataScramblingIdentityPdsch [TS38.211, sec 7.3.1.1], It equals the higher-layer parameter Datascrambling-Identity if configured and the RNTI equals the C-RNTI, otherwise L2 needs to set it to physical cell id. Value: 0->65535 - uint16_t dataScramblingId; - /// Number of layers [TS38.211, sec 7.3.1.3]. Value : 1->8 - uint8_t nrOfLayers; - /// PDSCH transmission schemes [TS38.214, sec5.1.1] 0: Up to 8 transmission layers - uint8_t transmissionScheme; - /// Reference point for PDSCH DMRS "k" - used for tone mapping [TS38.211, sec 7.4.1.1.2] Resource block bundles [TS38.211, sec 7.3.1.6] Value: 0 -> 1 If 0, the 0 reference point for PDSCH DMRS is at Point A [TS38.211 sec 4.4.4.2]. Resource block bundles generated per sub-bullets 2 and 3 in [TS38.211, sec 7.3.1.6]. For sub-bullet 2, the start of bandwidth part must be set to the start of actual bandwidth part +NstartCORESET and the bandwidth of the bandwidth part must be set to the bandwidth of the initial bandwidth part. If 1, the DMRS reference point is at the lowest VRB/PRB of the allocation. Resource block bundles generated per sub-bullets 1 [TS38.211, sec 7.3.1.6] - uint8_t refPoint; - // DMRS [TS38.211 sec 7.4.1.1] - /// DMRS symbol positions [TS38.211, sec 7.4.1.1.2 and Tables 7.4.1.1.2-3 and 7.4.1.1.2-4] Bitmap occupying the 14 LSBs with: bit 0: first symbol and for each bit 0: no DMRS 1: DMRS - uint16_t dlDmrsSymbPos; - /// DL DMRS config type [TS38.211, sec 7.4.1.1.2] 0: type 1, 1: type 2 - uint8_t dmrsConfigType; - /// DL-DMRS-Scrambling-ID [TS38.211, sec 7.4.1.1.2 ] If provided by the higher-layer and the PDSCH is scheduled by PDCCH with CRC scrambled by CRNTI or CS-RNTI, otherwise, L2 should set this to physical cell id. Value: 0->65535 - uint16_t dlDmrsScramblingId; - /// DMRS sequence initialization [TS38.211, sec 7.4.1.1.2]. Should match what is sent in DCI 1_1, otherwise set to 0. Value : 0->1 - uint8_t SCID; - /// Number of DM-RS CDM groups without data [TS38.212 sec 7.3.1.2.2] [TS38.214 Table 4.1-1] it determines the ratio of PDSCH EPRE to DM-RS EPRE. Value: 1->3 - uint8_t numDmrsCdmGrpsNoData; - /// DMRS ports. [TS38.212 7.3.1.2.2] provides description between DCI 1-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used - uint16_t dmrsPorts; - // Pdsch Allocation in frequency domain [TS38.214, sec 5.1.2.2] - /// Resource Allocation Type [TS38.214, sec 5.1.2.2] 0: Type 0, 1: Type 1 - uint8_t resourceAlloc; - /// For resource alloc type 0. TS 38.212 V15.0.x, 7.3.1.2.2 bitmap of RBs, 273 rounded up to multiple of 32. This bitmap is in units of VRBs. LSB of byte 0 of the bitmap represents the first RB of the bwp - uint8_t rbBitmap[36]; - /// For resource allocation type 1. [TS38.214, sec 5.1.2.2.2] The starting resource block within the BWP for this PDSCH. Value: 0->274 - uint16_t rbStart; - /// For resource allocation type 1. [TS38.214, sec 5.1.2.2.2] The number of resource block within for this PDSCH. Value: 1->275 - uint16_t rbSize; - /// VRB-to-PRB-mapping [TS38.211, sec 7.3.1.6] 0: non-interleaved 1: interleaved with RB size 2 2: Interleaved with RB size 4 - uint8_t VRBtoPRBMapping; - // Resource Allocation in time domain [TS38.214, sec 5.1.2.1] - /// Start symbol index of PDSCH mapping from the start of the slot, S. [TS38.214, Table 5.1.2.1-1] Value: 0->13 - uint8_t StartSymbolIndex; - /// PDSCH duration in symbols, L [TS38.214, Table 5.1.2.1-1] Value: 1->14 - uint8_t NrOfSymbols; - // PTRS [TS38.214, sec 5.1.6.3] - /// PT-RS antenna ports [TS38.214, sec 5.1.6.3] [TS38.211, table 7.4.1.2.2-1] Bitmap occupying the 6 LSBs with: bit 0: antenna port 1000 bit 5: antenna port 1005 and for each bit 0: PTRS port not used 1: PTRS port used - uint8_t PTRSPortIndex ; - /// PT-RS time density [TS38.214, table 5.1.6.3-1] 0: 1 1: 2 2: 4 - uint8_t PTRSTimeDensity; - /// PT-RS frequency density [TS38.214, table 5.1.6.3-2] 0: 2 1: 4 - uint8_t PTRSFreqDensity; - /// PT-RS resource element offset [TS38.211, table 7.4.1.2.2-1] Value: 0->3 - uint8_t PTRSReOffset; - /// PT-RS-to-PDSCH EPRE ratio [TS38.214, table 4.1-2] Value :0->3 - uint8_t nEpreRatioOfPDSCHToPTRS; - // Beamforming - nr_beamforming_t precodingAndBeamforming; -}nfapi_nr_dl_config_pdsch_pdu_rel15_t; -#define NFAPI_NR_DL_CONFIG_REQUEST_PDSCH_PDU_REL15_TAG - -typedef struct { - nfapi_nr_dl_config_pdsch_pdu_rel15_t pdsch_pdu_rel15; -} nfapi_nr_dl_config_pdsch_pdu; - -typedef struct { - nfapi_tl_t tl; - // nfapi_nr_search_space_t pagingSearchSpace; - // nfapi_nr_coreset_t pagingControlResourceSets; -}nfapi_nr_dl_config_pch_pdu_rel15_t; - -typedef struct { - nfapi_nr_dl_config_pch_pdu_rel15_t pch_pdu_rel15; -} nfapi_nr_dl_config_pch_pdu; - -/*typedef struct { - nfapi_nr_dl_config_dci_dl_pdu_rel15_t dci_dl_pdu_rel15; - nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params_rel15; - } nfapi_nr_dl_config_dci_dl_pdu;*/ - -typedef struct { - nfapi_nr_dl_config_pdcch_pdu_rel15_t pdcch_pdu_rel15; -} nfapi_nr_dl_config_pdcch_pdu; - -typedef struct { - uint8_t pdu_type; - uint8_t pdu_size; - - union { - nfapi_nr_dl_config_pdcch_pdu pdcch_pdu; - nfapi_nr_dl_config_bch_pdu bch_pdu; - nfapi_nr_dl_config_pdsch_pdu pdsch_pdu; - nfapi_nr_dl_config_pch_pdu pch_pdu; - }; -} nfapi_nr_dl_config_request_pdu_t; - - -typedef struct { - nfapi_tl_t tl; - uint8_t number_dci; - uint8_t number_pdu; - uint8_t number_pdsch_rnti; - nfapi_nr_dl_config_request_pdu_t *dl_config_pdu_list; -} nfapi_nr_dl_config_request_body_t; - -typedef struct { - nfapi_p7_message_header_t header; - uint16_t sfn_sf; - nfapi_nr_dl_config_request_body_t dl_config_request_body; - nfapi_vendor_extension_tlv_t vendor_extension; -} nfapi_nr_dl_config_request_t; +*/ typedef enum {nr_pusch_freq_hopping_disabled = 0 , diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h index 1eea6474f3..bb410791fe 100644 --- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h +++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h @@ -22,18 +22,18 @@ #define NFAPI_MAX_NUM_GROUPS 8 #define NFAPI_MAX_NUM_CB 8 -/* -// Extension to the generic structures for single tlv values -typedef struct { - nfapi_tl_t tl; - int32_t value; -} nfapi_int32_tlv_t; typedef struct { - nfapi_tl_t tl; - uint32_t value; -} nfapi_uint32_tlv_t; -*/ + /// Value: 0 -> 1, 0: Payload is carried directly in the value field, 1: Pointer to payload is in the value field + uint16_t tag; + /// Length of the actual payload in bytes, without the padding bytes Value: 0 β†’ 65535 + uint16_t length; + union { + uint32_t *ptr; + uint32_t direct[16384]; + } value; +} nfapi_nr_tx_data_request_tlv_t; + // 2019.8 // SCF222_5G-FAPI_PHY_SPI_Specificayion.pdf Section 3.2 @@ -573,17 +573,29 @@ typedef struct }nfapi_nr_tx_precoding_and_beamforming_number_of_prgs_t; +/* //table 3-43 typedef struct { - uint16_t num_prgs;/*Number of PRGs spanning this allocation. -Value : 1->275 */ - uint16_t prg_size;/*Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275 */ + uint16_t num_prgs;//Number of PRGs spanning this allocation. Value : 1->275 + uint16_t prg_size;//Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275 //watchout: dig_bf_interfaces here, in table 3-53 it's dig_bf_interface uint8_t dig_bf_interfaces;//Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255 nfapi_nr_tx_precoding_and_beamforming_number_of_prgs_t* prgs_list;// }nfapi_nr_tx_precoding_and_beamforming_t; +*/ + +typedef struct { + /// Number of PRGs spanning this allocation. Value : 1->275 + uint16_t numPRGs; + /// Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275 + uint16_t prgSize; + /// Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255 + uint8_t digBFInterfaces; + uint16_t PMIdx[275]; + uint16_t *beamIdx[275]; +} nfapi_nr_tx_precoding_and_beamforming_t; //table 3-37 @@ -606,33 +618,154 @@ SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 */ } nfapi_nr_dl_dci_pdu_t; -//table 3-36 -typedef struct -{ - uint16_t bwp_size;//Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP Value: 1->275 - uint16_t bwp_start;//bandwidth part start RB index from reference CRB [TS38.213 sec 12] Value: 0->274 - uint8_t subcarrier_spacing;//subcarrierSpacing [TS38.211 sec 4.2] Value:0->4 - uint8_t cyclic_prefix;//Cyclic prefix type [TS38.211 sec 4.2] 0: Normal; 1: Extended - //Coreset [TS38.211 sec 7.3.2.2] - uint8_t start_symbol_index;//Starting OFDM symbol for the CORESET Value: 0->13 - uint8_t duration_symbols;/* Contiguous time duration of the CORESET in number of symbols. Corresponds to L1 parameter π‘π‘ π‘¦π‘šπ‘ 𝐢𝑂𝑅𝐸𝑆𝐸𝑇 [TS38.211 sec 7.3.2.2] Value: 1,2,3*/ - uint8_t freq_domain_resource[6];/* Frequency domain resources. This is a bitmap defining non-overlapping groups of 6 PRBs in ascending order. [TS38.213 10.1]. Also, corresponds to L1 parameter N^{CORESET}_{RB} [TS38.211 sec 7.3.2.2] - Bitmap of uint8 array. 45 bits.*/ - uint8_t cce_reg_mapping_type;/*CORESET-CCE-to-REG-mapping-type [TS38.211 sec 7.3.2.2] 0: non-interleaved 1: interleaved */ - uint8_t reg_bundle_size;/*The number of REGs in a bundle. Must be 6 for -cceRegMappingType = nonInterleaved. For cceRegMappingType = interleaved, must belong to {2,6} if duration = 1,2 and must belong to {3,6} if -duration = 3. Corresponds to parameter L. [TS38.211 sec 7.3.2.2] Value: 2,3,6 */ - uint8_t interleaver_size;//The interleaver size. For interleaved mapping belongs to {2,3,6} and for non-interleaved mapping is NA. Corresponds to parameter R. [TS38.211 sec 7.3.2.2] Value: 2,3,6 - uint8_t core_set_type;//[TS38.211 sec 7.3.2.2 and sec 7.4.1.3.2] 0: CORESET is configured by the PBCH or SIB1 (subcarrier 0 of CRB0 for DMRS mapping) 1: otherwise (subcarrier 0 of CORESET) - uint16_t shift_index;//[TS38.211 sec 7.3.2.2] Not applicable for non-interleaved mapping. For interleaved mapping and a PDCCH transmitted in a CORESET configured by the PBCH or SIB1 this should be set to phy cell ID. Value: 10 bits Otherwise, for interleaved mapping this is set to 0-> max num of PRBs. Value 0-> 275 - uint8_t precoder_granularity;//Granularity of precoding [TS38.211 sec 7.3.2.2] 0: sameAsRegBundle 1: allContiguousRBs - uint16_t num_dl_dci;//Number of DCIs in this CORESET. Value: 0->MaxDciPerSlot - nfapi_nr_dl_dci_pdu_t* dl_dci_list; +typedef struct { + /// Number of PRGs spanning this allocation. Value : 1->275 + uint16_t numPRGs; + /// Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275 + uint16_t prgSize; + /// Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255 + uint8_t digBFInterfaces; + uint16_t PMIdx[275]; + uint16_t *beamIdx[275]; +} nr_beamforming_t; + +#define MAX_DCI_CORESET 8 +#define DCI_PAYLOAD_BYTE_LEN 8 + +typedef struct { + ///Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP,Value: 1->275 + uint16_t BWPSize; + ///bandwidth part start RB index from reference CRB, [TS38.213 sec 12], Value: 0->274 + uint16_t BWPStart; + ///subcarrierSpacing [TS38.211 sec 4.2], Value:0->4 + uint8_t SubcarrierSpacing; + ///Cyclic prefix type [TS38.211 sec 4.2], 0: Normal; 1: Extended + uint8_t CyclicPrefix; + ///Starting OFDM symbol for the CORESET, Value: 0->13 + uint8_t StartSymbolIndex; +///Contiguous time duration of the CORESET in number of symbols. Corresponds to L1 parameter π‘π‘ π‘¦π‘šπ‘_𝐢𝑂𝑅𝐸𝑆𝐸𝑇 [TS38.211 sec 7.3.2.2] Value: 1,2,3 + uint8_t DurationSymbols; + ///Frequency domain resources. This is a bitmap defining non-overlapping groups of 6 PRBs in ascending order. [TS38.213 10.1]. Also, corresponds to L1 parameter CORE SET RB N [TS38.211 sec 7.3.2.2] Bitmap of uint8 array. 45 bits. + uint8_t FreqDomainResource[6]; + ///CORESET-CCE-to-REG-mapping-type [TS38.211 sec 7.3.2.2] 0: non-interleaved 1: interleaved + uint8_t CceRegMappingType; + ///The number of REGs in a bundle. Must be 6 for cceRegMappingType = nonInterleaved. For cceRegMappingType = interleaved, must belong to {2,6} if duration = 1,2 and must belong to {3,6} if duration = 3. Corresponds to parameter L. [TS38.211 sec 7.3.2.2] Value: 2,3,6 + uint8_t RegBundleSize; + ///The interleaver size. For interleaved mapping belongs to {2,3,6} and for non-interleaved mapping is NA. Corresponds to parameter R. [TS38.211 sec 7.3.2.2] Value: 2,3,6 CoreSetType + uint8_t InterleaverSize; + ///[TS38.211 sec 7.3.2.2 and sec 7.4.1.3.2] 0: CORESET is configured by the PBCH or SIB1 (subcarrier 0 of CRB0 for DMRS mapping) 1: otherwise (subcarrier 0 of CORESET) + uint8_t CoreSetType; + ///[TS38.211 sec 7.3.2.2] Not applicable for non-interleaved mapping. For interleaved mapping and a PDCCH transmitted in a CORESET configured by the PBCH or SIB1 this should be set to phy cell ID. Value: 10 bits Otherwise, for interleaved mapping this is set to 0-> max num of PRBs. Value 0-> 275 + uint16_t ShiftIndex; + ///Granularity of precoding [TS38.211 sec 7.3.2.2] Field Type Description 0: sameAsRegBundle 1: allContiguousRBs + uint8_t precoderGranularity; + ///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot + uint16_t numDlDci; + ///The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535. + uint16_t RNTI[MAX_DCI_CORESET]; + ///For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535 + uint16_t ScramblingId[MAX_DCI_CORESET]; + ///For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535 + uint16_t ScramblingRNTI[MAX_DCI_CORESET]; + ///CCE start Index used to send the DCI Value: 0->135 + uint8_t CceIndex[MAX_DCI_CORESET]; + ///Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16 + uint8_t AggregationLevel[MAX_DCI_CORESET]; + ///Precoding and Beamforming structure See Table 3-43 + nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET]; + ///PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps + uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET]; + ///PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB + uint8_t powerControlOffsetSS[MAX_DCI_CORESET]; +///The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BTYE_LEN*8 + uint16_t PayloadSizeBits[MAX_DCI_CORESET]; + ///DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB + uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN]; +} nfapi_nr_dl_tti_pdcch_pdu_rel15_t; + +typedef struct { + uint16_t pduBitmap; + uint16_t rnti; + uint16_t pduIndex; + // BWP [TS38.213 sec 12] + /// Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP, Value: 1->275 + uint16_t BWPSize; + /// bandwidth part start RB index from reference CRB [TS38.213 sec 12],Value: 0->274 + uint16_t BWPStart; + /// subcarrierSpacing [TS38.211 sec 4.2], Value:0->4 + uint8_t SubcarrierSpacing; + /// Cyclic prefix type [TS38.211 sec 4.2], 0: Normal; 1: Extended + uint8_t CyclicPrefix; + // Codeword information + /// Number of code words for this RNTI (UE), Value: 1 -> 2 + uint8_t NrOfCodewords; + /// Target coding rate [TS38.212 sec 5.4.2.1 and 38.214 sec 5.1.3.1]. This is the number of information bits per 1024 coded bits expressed in 0.1 bit units + uint16_t targetCodeRate[2]; + /// QAM modulation [TS38.212 sec 5.4.2.1 and 38.214 sec 5.1.3.1], Value: 2,4,6,8 + uint8_t qamModOrder[2]; + /// MCS index [TS38.214, sec 5.1.3.1], should match value sent in DCI Value : 0->31 + uint8_t mcsIndex[2]; + /// MCS-Table-PDSCH [TS38.214, sec 5.1.3.1] 0: notqam256, 1: qam256, 2: qam64LowSE + uint8_t mcsTable[2]; + /// Redundancy version index [TS38.212, Table 5.4.2.1-2 and 38.214, Table 5.1.2.1-2], should match value sent in DCI Value : 0->3 + uint8_t rvIndex[2]; + /// Transmit block size (in bytes) [TS38.214 sec 5.1.3.2], Value: 0->65535 + uint32_t TBSize[2]; + /// dataScramblingIdentityPdsch [TS38.211, sec 7.3.1.1], It equals the higher-layer parameter Datascrambling-Identity if configured and the RNTI equals the C-RNTI, otherwise L2 needs to set it to physical cell id. Value: 0->65535 + uint16_t dataScramblingId; + /// Number of layers [TS38.211, sec 7.3.1.3]. Value : 1->8 + uint8_t nrOfLayers; + /// PDSCH transmission schemes [TS38.214, sec5.1.1] 0: Up to 8 transmission layers + uint8_t transmissionScheme; + /// Reference point for PDSCH DMRS "k" - used for tone mapping [TS38.211, sec 7.4.1.1.2] Resource block bundles [TS38.211, sec 7.3.1.6] Value: 0 -> 1 If 0, the 0 reference point for PDSCH DMRS is at Point A [TS38.211 sec 4.4.4.2]. Resource block bundles generated per sub-bullets 2 and 3 in [TS38.211, sec 7.3.1.6]. For sub-bullet 2, the start of bandwidth part must be set to the start of actual bandwidth part +NstartCORESET and the bandwidth of the bandwidth part must be set to the bandwidth of the initial bandwidth part. If 1, the DMRS reference point is at the lowest VRB/PRB of the allocation. Resource block bundles generated per sub-bullets 1 [TS38.211, sec 7.3.1.6] + uint8_t refPoint; + // DMRS [TS38.211 sec 7.4.1.1] + /// DMRS symbol positions [TS38.211, sec 7.4.1.1.2 and Tables 7.4.1.1.2-3 and 7.4.1.1.2-4] Bitmap occupying the 14 LSBs with: bit 0: first symbol and for each bit 0: no DMRS 1: DMRS + uint16_t dlDmrsSymbPos; + /// DL DMRS config type [TS38.211, sec 7.4.1.1.2] 0: type 1, 1: type 2 + uint8_t dmrsConfigType; + /// DL-DMRS-Scrambling-ID [TS38.211, sec 7.4.1.1.2 ] If provided by the higher-layer and the PDSCH is scheduled by PDCCH with CRC scrambled by CRNTI or CS-RNTI, otherwise, L2 should set this to physical cell id. Value: 0->65535 + uint16_t dlDmrsScramblingId; + /// DMRS sequence initialization [TS38.211, sec 7.4.1.1.2]. Should match what is sent in DCI 1_1, otherwise set to 0. Value : 0->1 + uint8_t SCID; + /// Number of DM-RS CDM groups without data [TS38.212 sec 7.3.1.2.2] [TS38.214 Table 4.1-1] it determines the ratio of PDSCH EPRE to DM-RS EPRE. Value: 1->3 + uint8_t numDmrsCdmGrpsNoData; + /// DMRS ports. [TS38.212 7.3.1.2.2] provides description between DCI 1-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used + uint16_t dmrsPorts; + // Pdsch Allocation in frequency domain [TS38.214, sec 5.1.2.2] + /// Resource Allocation Type [TS38.214, sec 5.1.2.2] 0: Type 0, 1: Type 1 + uint8_t resourceAlloc; + /// For resource alloc type 0. TS 38.212 V15.0.x, 7.3.1.2.2 bitmap of RBs, 273 rounded up to multiple of 32. This bitmap is in units of VRBs. LSB of byte 0 of the bitmap represents the first RB of the bwp + uint8_t rbBitmap[36]; + /// For resource allocation type 1. [TS38.214, sec 5.1.2.2.2] The starting resource block within the BWP for this PDSCH. Value: 0->274 + uint16_t rbStart; + /// For resource allocation type 1. [TS38.214, sec 5.1.2.2.2] The number of resource block within for this PDSCH. Value: 1->275 + uint16_t rbSize; + /// VRB-to-PRB-mapping [TS38.211, sec 7.3.1.6] 0: non-interleaved 1: interleaved with RB size 2 2: Interleaved with RB size 4 + uint8_t VRBtoPRBMapping; + // Resource Allocation in time domain [TS38.214, sec 5.1.2.1] + /// Start symbol index of PDSCH mapping from the start of the slot, S. [TS38.214, Table 5.1.2.1-1] Value: 0->13 + uint8_t StartSymbolIndex; + /// PDSCH duration in symbols, L [TS38.214, Table 5.1.2.1-1] Value: 1->14 + uint8_t NrOfSymbols; + // PTRS [TS38.214, sec 5.1.6.3] + /// PT-RS antenna ports [TS38.214, sec 5.1.6.3] [TS38.211, table 7.4.1.2.2-1] Bitmap occupying the 6 LSBs with: bit 0: antenna port 1000 bit 5: antenna port 1005 and for each bit 0: PTRS port not used 1: PTRS port used + uint8_t PTRSPortIndex ; + /// PT-RS time density [TS38.214, table 5.1.6.3-1] 0: 1 1: 2 2: 4 + uint8_t PTRSTimeDensity; + /// PT-RS frequency density [TS38.214, table 5.1.6.3-2] 0: 2 1: 4 + uint8_t PTRSFreqDensity; + /// PT-RS resource element offset [TS38.211, table 7.4.1.2.2-1] Value: 0->3 + uint8_t PTRSReOffset; + /// PT-RS-to-PDSCH EPRE ratio [TS38.214, table 4.1-2] Value :0->3 + uint8_t nEpreRatioOfPDSCHToPTRS; + // Beamforming + nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming; +}nfapi_nr_dl_tti_pdsch_pdu_rel15_t; -} nfapi_nr_pdcch_pdu_t; //for pdsch_pdu: - +/* typedef struct { uint16_t target_code_rate;// @@ -692,31 +825,32 @@ typedef struct uint32_t dl_tb_crc;//TB CRC: to be used in the last CB, applicable only if last CB is present } nfapi_nr_dlsch_pdu_t; +*/ //for csi-rs_pdu: //table 3-39 typedef struct { -uint16_t bwp_size;// -uint16_t bwp_start;// -uint8_t subcarrier_spacing;// -uint8_t cyclic_prefix;// -uint16_t start_rb; -uint16_t nr_of_rbs; -uint8_t csi_type;//Value: 0:TRS 1:CSI-RS NZP 2:CSI-RS ZP -uint8_t row;//Row entry into the CSI Resource location table. [TS38.211, sec 7.4.1.5.3 and table 7.4.1.5.3-1] Value: 1-18 -uint16_t freq_domain;//Value: Up to the 12 LSBs, actual size is determined by the Row parameter -uint8_t symb_l0;//The time domain location l0 and firstOFDMSymbolInTimeDomain Value: 0->13 -uint8_t symb_l1;// -uint8_t cdm_type; -uint8_t freq_density;//The density field, p and comb offset (for dot5).0: dot5 (even RB), 1: dot5 (odd RB), 2: one, 3: three -uint16_t scramb_id;//ScramblingID of the CSI-RS [TS38.214, sec 5.2.2.3.1] Value: 0->1023 -//tx power info -uint8_t power_control_offset;//Ratio of PDSCH EPRE to NZP CSI-RSEPRE Value :0->23 representing -8 to 15 dB in 1dB steps -uint8_t power_control_offset_ss;//Ratio of SSB/PBCH block EPRE to NZP CSI-RS EPRES 0: -3dB, 1: 0dB, 2: 3dB, 3: 6dB + uint16_t bwp_size;// + uint16_t bwp_start;// + uint8_t subcarrier_spacing;// + uint8_t cyclic_prefix;// + uint16_t start_rb; + uint16_t nr_of_rbs; + uint8_t csi_type;//Value: 0:TRS 1:CSI-RS NZP 2:CSI-RS ZP + uint8_t row;//Row entry into the CSI Resource location table. [TS38.211, sec 7.4.1.5.3 and table 7.4.1.5.3-1] Value: 1-18 + uint16_t freq_domain;//Value: Up to the 12 LSBs, actual size is determined by the Row parameter + uint8_t symb_l0;//The time domain location l0 and firstOFDMSymbolInTimeDomain Value: 0->13 + uint8_t symb_l1;// + uint8_t cdm_type; + uint8_t freq_density;//The density field, p and comb offset (for dot5).0: dot5 (even RB), 1: dot5 (odd RB), 2: one, 3: three + uint16_t scramb_id;//ScramblingID of the CSI-RS [TS38.214, sec 5.2.2.3.1] Value: 0->1023 + //tx power info + uint8_t power_control_offset;//Ratio of PDSCH EPRE to NZP CSI-RSEPRE Value :0->23 representing -8 to 15 dB in 1dB steps + uint8_t power_control_offset_ss;//Ratio of SSB/PBCH block EPRE to NZP CSI-RS EPRES 0: -3dB, 1: 0dB, 2: 3dB, 3: 6dB -} nfapi_nr_csi_rs_pdu_t; +} nfapi_nr_dl_tti_csi_rs_pdu_rel15_t; //for ssb_pdu: @@ -743,27 +877,85 @@ typedef struct } nfapi_nr_bch_payload_t; -typedef struct -{ - uint16_t phys_cell_id;//0~1007 - uint8_t beta_pss;//PSS EPRE to SSS EPRE in a SS/PBCH block 0 = 0dB 1 = 3dB - uint8_t ssb_block_index;//SS/PBCH block index within a SSB burst set. Required for PBCH DMRS scrambling. Value: 0->63 (Lmax) - uint8_t ssb_subcarrier_offset;// - uint16_t ssb_offset_point_a;//Offset of lowest subcarrier of lowest resource block used for SS/PBCH block. Value: 0->2199 - uint8_t bch_payload_flag;//A value indicating how the BCH payload is generated. This should match the PARAM/CONFIG TLVs. Value: 0: MAC generates the full PBCH payload, see Table 3-41, where bchPayload has 31 bits 1: PHY generates the timing PBCH bits, see Table 3-41, where the bchPayload has 24 bits 2: PHY generates the full PBCH payload - nfapi_nr_bch_payload_t bch_payload; +typedef struct { + /// Physical Cell ID Value 0~>1007 + uint16_t PhysCellId; + ///PSS EPRE to SSS EPRE in a SS/PBCH block 0 = 0dB 1 = 3dB + uint8_t BetaPss; + ///SS/PBCH block index within a SSB burst set. Required for PBCH DMRS scrambling. Value: 0->63 (Lmax) + uint8_t SsbBlockIndex; + /// ssbSubcarrierOffset or π‘˜π‘†π‘†π΅ (TS38.211, section 7.4.3.1) Value: 0->31 + uint8_t SsbSubcarrierOffset; + ///Offset of lowest subcarrier of lowest resource block used for SS/PBCH block. Value: 0->2199 + uint16_t ssbOffsetPointA; + /// A value indicating how the BCH payload is generated. This should match the PARAM/CONFIG TLVs. Value: 0: MAC generates the full PBCH payload, see Table 3-41, where bchPayload has 31 bits 1: PHY generates the timing PBCH bits, see Table 3-41, where the bchPayload has 24 bits 2: PHY generates the full PBCH payload + uint8_t bchPayloadFlag; + uint32_t bchPayload; nfapi_nr_tx_precoding_and_beamforming_t precoding_and_beamforming; +} nfapi_nr_dl_tti_ssb_pdu_rel15_t; -} nfapi_nr_ssb_pdu_t; +typedef struct { + nfapi_nr_dl_tti_ssb_pdu_rel15_t ssb_pdu_rel15; +} nfapi_nr_dl_tti_ssb_pdu; +typedef struct { + nfapi_nr_dl_tti_csi_rs_pdu_rel15_t csi_rs_pdu_rel15; +} nfapi_nr_dl_tti_csi_rs_pdu; + +typedef struct { + nfapi_nr_dl_tti_pdsch_pdu_rel15_t pdsch_pdu_rel15; +} nfapi_nr_dl_tti_pdsch_pdu; + +typedef struct { + nfapi_nr_dl_tti_pdcch_pdu_rel15_t pdcch_pdu_rel15; +} nfapi_nr_dl_tti_pdcch_pdu; + +typedef struct { + uint16_t PDUType; + uint16_t PDUSize; + + union { + nfapi_nr_dl_tti_pdcch_pdu pdcch_pdu; + nfapi_nr_dl_tti_pdsch_pdu pdsch_pdu; + nfapi_nr_dl_tti_csi_rs_pdu csi_rs_pdu; + nfapi_nr_dl_tti_ssb_pdu ssb_pdu; + }; +} nfapi_nr_dl_tti_request_pdu_t; + +#define NFAPI_NR_MAX_DL_TTI_PDUS 32 +typedef struct { + /// Number of PDUs that are included in this message. All PDUs in the message are numbered in order. Value 0 -> 255 + uint8_t nPDUs; + /// Number of UEs in the Group included in this message. Value 0 -> 255 + uint8_t nGroup; + /// List containing PDUs + nfapi_nr_dl_tti_request_pdu_t dl_tti_pdu_list[NFAPI_NR_MAX_DL_TTI_PDUS]; + /// Number of UE in this group. For SU-MIMO, one group includes one UE only. For MU-MIMO, one group includes up to 12 UEs. Value 1 -> 12 + uint8_t nUe[256]; + /// This value is an index for number of PDU identified by nPDU in this message Value: 0 -> 255 + uint8_t PduIdx[256][12]; +} nfapi_nr_dl_tti_request_body_t; + +typedef struct { + nfapi_p7_message_header_t header; + /// System Frame Number (0-1023) + uint16_t SFN; + /// Slot number (0-319) + uint16_t Slot; + nfapi_nr_dl_tti_request_body_t dl_tti_request_body; + nfapi_vendor_extension_tlv_t vendor_extension; +} nfapi_nr_dl_tti_request_t; + +/* typedef struct { - nfapi_nr_pdcch_pdu_t* pdcch_pdu; - nfapi_nr_dlsch_pdu_t* dlsch_pdu;//pdsch_pdu; - nfapi_nr_csi_rs_pdu_t* csi_rs_pdu; - nfapi_nr_ssb_pdu_t* ssb_pdu; + nfapi_nr_dl_tti_pdcch_pdu* pdcch_pdu; + nfapi_nr_dl_tti_pdsch_pdu* pdsch_pdu; + nfapi_nr_dl_tti_csi_rs_pdu_t* csi_rs_pdu; + nfapi_nr_dl_tti_ssb_pdu_t* ssb_pdu; } nfapi_nr_dl_pdu_configuration_t; - +*/ + /* typedef struct { uint16_t pdu_type;//0: PDCCH PDU 1: PDSCH PDU 2: CSI-RS PDU 3: SSB PDU, @@ -771,6 +963,7 @@ typedef struct nfapi_nr_dl_pdu_configuration_t* dl_pdu_configuration; } nfapi_nr_dl_tti_request_number_of_pdus_t; + typedef struct { @@ -795,9 +988,10 @@ typedef struct { nfapi_nr_dl_tti_request_number_of_groups_t* groups_list; } nfapi_nr_dl_tti_request_t; +*/ // Section 3.4.3 ul_tti_request - + //for prach_pdu: typedef struct { @@ -1015,6 +1209,13 @@ typedef struct // +typedef enum { + NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE = 0, + NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE = 1, + NFAPI_NR_DL_TTI_CSI_RS_PDU_TYPE = 2, + NFAPI_NR_DL_TTI_SSB_PDU_TYPE = 3, +} nfapi_nr_dl_tti_pdu_type_e; + typedef enum { NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE=0, NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE, @@ -1050,8 +1251,8 @@ typedef struct } nfapi_nr_ul_tti_request_number_of_groups_t; typedef struct { - uint16_t sfn; //0->1023 - uint16_t slot;//0->319 + uint16_t SFN; //0->1023 + uint16_t Slot;//0->319 uint8_t n_pdus;//Number of PDUs that are included in this message. All PDUs in the message are numbered in order. Value 0 -> 255 uint8_t rach_present;//Indicates if a RACH PDU will be included in this message. 0: no RACH in this slot 1: RACH in this slot uint8_t n_ulsch;//Number of ULSCH PDUs that are included in this message. @@ -1059,13 +1260,13 @@ typedef struct { uint8_t n_group;//Number of UE Groups included in this message. Value 0 -> 8 nfapi_nr_ul_tti_request_number_of_pdus_t pdus_list[NFAPI_MAX_NUM_UL_PDU]; nfapi_nr_ul_tti_request_number_of_groups_t groups_list[NFAPI_MAX_NUM_GROUPS]; - } nfapi_nr_ul_tti_request_t; //3.4.4 ul_dci_request //table 3-54 +/* typedef struct { uint16_t pdu_type;//0: PDCCH PDU @@ -1082,6 +1283,25 @@ typedef struct nfapi_nr_ul_dci_request_number_of_pdus_t* pdu_list; } nfapi_nr_ul_dci_request_t; +*/ + + // normally one PDU per coreset per BWP +#define NFAPI_NR_MAX_UL_DCI_PDUS 4 + +typedef struct { + /// only possible value 0: PDCCH PDU + uint16_t PDUType; + ///Size of the PDU control information (in bytes). This length value includes the 4 bytes required for the PDU type and PDU size parameters. Value 0 -> 65535 + uint16_t PDUSize; + nfapi_nr_dl_tti_pdcch_pdu pdcch_pdu; +} nfapi_nr_ul_dci_request_pdus_t; + +typedef struct { + uint16_t SFN; + uint16_t Slot; + uint8_t numPdus; + nfapi_nr_ul_dci_request_pdus_t ul_dci_pdu_list[NFAPI_NR_MAX_UL_DCI_PDUS]; +} nfapi_nr_ul_dci_request_t; //3.4.5 slot_errors typedef enum { @@ -1098,6 +1318,7 @@ typedef enum { } nfapi_nr_slot_errors_dl_tti_e; + typedef enum { NFAPI_NR_SLOT_UL_DCI_MSG_INVALID_STATE, NFAPI_NR_SLOT_UL_DCI_MSG_INVALID_SFN, @@ -1108,23 +1329,23 @@ typedef enum { //3.4.6 tx_data_request //table 3-58 - +#define NFAPI_NR_MAX_TX_REQUEST_TLV 2 typedef struct { - uint16_t pdu_length; - uint16_t pdu_index; - uint32_t num_tlv; - //! fixme - nfapi_int32_tlv_t* tlvs; //nfapi_int32_tlv_t tlvs[num_tlv] + uint16_t PDU_length; + uint16_t PDU_index; + uint32_t num_TLV; + nfapi_nr_tx_data_request_tlv_t TLVs[NFAPI_NR_MAX_TX_REQUEST_TLV]; } nfapi_nr_pdu_t; +#define NFAPI_NR_MAX_TX_REQUEST_PDUS 16 typedef struct { - uint16_t sfn; - uint16_t slot; - uint16_t number_of_pdus; - nfapi_nr_pdu_t* pdu_list; + uint16_t SFN; + uint16_t Slot; + uint16_t Number_of_PDUs; + nfapi_nr_pdu_t pdu_list[NFAPI_NR_MAX_TX_REQUEST_PDUS]; } nfapi_nr_tx_data_request_t; diff --git a/nfapi/open-nFAPI/vnf/public_inc/nfapi_vnf_interface.h b/nfapi/open-nFAPI/vnf/public_inc/nfapi_vnf_interface.h index 5d463afdae..5abf6b75c3 100644 --- a/nfapi/open-nFAPI/vnf/public_inc/nfapi_vnf_interface.h +++ b/nfapi/open-nFAPI/vnf/public_inc/nfapi_vnf_interface.h @@ -18,7 +18,8 @@ #define _NFAPI_VNF_INTERFACE_H_ #include "nfapi_interface.h" -#include "nfapi_nr_interface.h" +#include "nfapi_nr_interface_scf.h" + #include "debug.h" #include "netinet/in.h" @@ -938,7 +939,7 @@ int nfapi_vnf_p7_del_pnf(nfapi_vnf_p7_config_t* config, int phy_id); * may be released after this function call has returned or at a later pointer */ int nfapi_vnf_p7_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_dl_config_request_t* req); -int nfapi_vnf_p7_nr_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_nr_dl_config_request_t* req); +int nfapi_vnf_p7_nr_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_nr_dl_tti_request_t* req); /*! Send the UL_CONFIG.request * \param config A pointer to the vnf p7 configuration diff --git a/nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c b/nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c index 8b60122483..35bd5e4c1b 100644 --- a/nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c +++ b/nfapi/open-nFAPI/vnf/src/vnf_p7_interface.c @@ -482,7 +482,7 @@ int nfapi_vnf_p7_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_dl_config_re return vnf_p7_pack_and_send_p7_msg(vnf_p7, &req->header); } -int nfapi_vnf_p7_nr_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_nr_dl_config_request_t* req) +int nfapi_vnf_p7_nr_dl_config_req(nfapi_vnf_p7_config_t* config, nfapi_nr_dl_tti_request_t* req) { //NFAPI_TRACE(NFAPI_TRACE_INFO, "%s(config:%p req:%p)\n", __FUNCTION__, config, req); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c index 542e88cd18..1d03be5472 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c @@ -155,7 +155,7 @@ void nr_pdcch_scrambling(uint32_t *in, } } -uint8_t nr_generate_dci_top(nfapi_nr_dl_config_pdcch_pdu *pdcch_pdu, +uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu, uint32_t **gold_pdcch_dmrs, int32_t *txdataF, int16_t amp, @@ -170,7 +170,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_config_pdcch_pdu *pdcch_pdu, nr_reg_t reg_mapping_list[NR_MAX_PDCCH_AGG_LEVEL*NR_NB_REG_PER_CCE]; /*First iteration: single DCI*/ - nfapi_nr_dl_config_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &pdcch_pdu->pdcch_pdu_rel15; + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &pdcch_pdu->pdcch_pdu_rel15; // find coreset descriptor diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.h b/openair1/PHY/NR_TRANSPORT/nr_dci.h index ffcaa8695a..2f6b0a33c1 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci.h +++ b/openair1/PHY/NR_TRANSPORT/nr_dci.h @@ -30,7 +30,7 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format, uint16_t N_RB, nfapi_nr_config_request_t *config); -uint8_t nr_generate_dci_top(nfapi_nr_dl_config_pdcch_pdu *pdcch_vars, +uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_vars, uint32_t **gold_pdcch_dmrs, int32_t *txdataF, int16_t amp, @@ -47,7 +47,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, int frame, int slot); -void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint16_t n_shift, uint8_t m); +void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m); void get_coreset_rballoc(uint8_t *FreqDomainResource,int *n_rb,int *rb_offset); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c index 6eb1a2ffce..aacbf393fa 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c @@ -141,14 +141,14 @@ void get_coreset_rballoc(uint8_t *FreqDomainResource,int *n_rb,int *rb_offset) { *n_rb = 6*count; } -void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint16_t n_shift, uint8_t m) { +void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m) { nr_cce_t* cce; nr_reg_t* reg; - nfapi_nr_dl_config_pdcch_pdu_rel15_t* pdcch_pdu_rel15 = &gNB->pdcch_pdu->pdcch_pdu_rel15; + nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu_rel15 = &gNB->pdcch_pdu->pdcch_pdu_rel15; int bsize = pdcch_pdu_rel15->RegBundleSize; int R = pdcch_pdu_rel15->InterleaverSize; - + int n_shift = pdcch_pdu_rel15->ShiftIndex; //Max number of candidates per aggregation level -- SIB1 configured search space only @@ -158,6 +158,7 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint16_t n_shift, uint8_t m) { get_coreset_rballoc(pdcch_pdu_rel15->FreqDomainResource,&n_rb,&rb_offset); + int N_reg = n_rb * pdcch_pdu_rel15->DurationSymbols; int C; @@ -227,7 +228,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, int frame, int slot) { - nfapi_nr_dl_config_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &gNB->pdcch_pdu->pdcch_pdu_rel15; + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &gNB->pdcch_pdu->pdcch_pdu_rel15; NR_gNB_DLSCH_t *dlsch; for (int i=0;inumDlDci;i++) { @@ -252,7 +253,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, dlsch->harq_mask |= (1<rnti = pdcch_pdu_rel15->RNTI[i]; - nr_fill_cce_list(gNB,pdcch_pdu_rel15->ShiftIndex,0); + nr_fill_cce_list(gNB,0); /* LOG_D(PHY, "DCI PDU: [0]->0x%lx \t [1]->0x%lx \n",dci_pdu[0], dci_pdu[1]); LOG_D(PHY, "DCI type %d payload (size %d) generated on candidate %d\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size, cand_idx); diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c index 5120bbce1e..5596e9fc48 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c @@ -81,7 +81,7 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, int harq_pid = 0; NR_DL_gNB_HARQ_t *harq = dlsch->harq_processes[harq_pid]; - nfapi_nr_dl_config_pdsch_pdu_rel15_t *rel15 = &harq->pdsch_pdu.pdsch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &harq->pdsch_pdu.pdsch_pdu_rel15; uint32_t scrambled_output[NR_MAX_NB_CODEWORDS][NR_MAX_PDSCH_ENCODED_LENGTH>>5]; int16_t **mod_symbs = (int16_t**)dlsch->mod_symbs; int16_t **tx_layers = (int16_t**)dlsch->txdataF; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h index 2dbb8bf0df..1ac603dca2 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h @@ -36,10 +36,10 @@ #include "PHY/defs_gNB.h" void nr_get_time_domain_allocation_type(nfapi_nr_config_request_t config, - nfapi_nr_dl_config_pdcch_pdu dci_pdu, - nfapi_nr_dl_config_pdsch_pdu *pdsch_pdu); + nfapi_nr_dl_tti_pdcch_pdu dci_pdu, + nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu); -void nr_check_time_alloc(uint8_t S, uint8_t L,nfapi_nr_dl_config_pdsch_pdu_rel15_t *rel15,nfapi_nr_config_request_t *cfg); +void nr_check_time_alloc(uint8_t S, uint8_t L,nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15,nfapi_nr_config_request_t *cfg); uint16_t get_RIV(uint16_t rb_start, uint16_t L, uint16_t N_RB); @@ -66,7 +66,7 @@ void nr_pdsch_codeword_scrambling(uint8_t *in, void nr_fill_dlsch(PHY_VARS_gNB *gNB, int frame, int slot, - nfapi_nr_dl_config_pdsch_pdu *pdsch_pdu, + nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, unsigned char *sdu); uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch, diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c index 1aca4bfd46..f156916dd2 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c @@ -280,7 +280,7 @@ int nr_dlsch_encoding(unsigned char *a, unsigned int crc=1; uint8_t harq_pid = dlsch->harq_ids[frame&2][slot]; AssertFatal(harq_pid<8 && harq_pid>=0,"illegal harq_pid %d\b",harq_pid); - nfapi_nr_dl_config_pdsch_pdu_rel15_t *rel15 = &dlsch->harq_processes[harq_pid]->pdsch_pdu.pdsch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->harq_processes[harq_pid]->pdsch_pdu.pdsch_pdu_rel15; uint16_t nb_rb = rel15->rbSize; uint8_t nb_symb_sch = rel15->NrOfSymbols; uint32_t A, Z, Kb, F=0; diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c index 6692dacda3..ff1f841e47 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c +++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c @@ -297,10 +297,10 @@ int16_t find_nr_ulsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type) { void nr_fill_dlsch(PHY_VARS_gNB *gNB, int frame, int slot, - nfapi_nr_dl_config_pdsch_pdu *pdsch_pdu, + nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, uint8_t *sdu) { - nfapi_nr_dl_config_pdsch_pdu_rel15_t *rel15 = &pdsch_pdu->pdsch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &pdsch_pdu->pdsch_pdu_rel15; int dlsch_id = find_nr_dlsch(rel15->rnti,gNB,SEARCH_EXIST); AssertFatal( (dlsch_id>=0) && (dlsch_iddlsch[dlsch_id][0]; NR_DL_gNB_HARQ_t **harq = dlsch->harq_processes; /// DLSCH struct - memcpy((void*)&harq[dlsch->harq_ids[frame%2][slot]]->pdsch_pdu, (void*)pdsch_pdu, sizeof(nfapi_nr_dl_config_pdsch_pdu)); + memcpy((void*)&harq[dlsch->harq_ids[frame%2][slot]]->pdsch_pdu, (void*)pdsch_pdu, sizeof(nfapi_nr_dl_tti_pdsch_pdu)); gNB->num_pdsch_rnti++; AssertFatal(sdu!=NULL,"sdu is null\n"); harq[dlsch->harq_ids[frame%2][slot]]->pdu = sdu; diff --git a/openair1/PHY/NR_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_TRANSPORT/nr_pbch.c index af83c17fc1..52797d1205 100644 --- a/openair1/PHY/NR_TRANSPORT/nr_pbch.c +++ b/openair1/PHY/NR_TRANSPORT/nr_pbch.c @@ -220,7 +220,7 @@ void nr_init_pbch_interleaver(uint8_t *interleaver) { } int nr_generate_pbch(NR_gNB_PBCH *pbch, - uint8_t *pbch_pdu, + nfapi_nr_dl_tti_ssb_pdu *ssb_pdu, uint8_t *interleaver, int32_t *txdataF, int16_t amp, @@ -243,7 +243,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch, ///Payload generation memset((void *)pbch, 0, sizeof(NR_gNB_PBCH)); pbch->pbch_a=0; - + uint8_t *pbch_pdu = (uint8_t*)&ssb_pdu->ssb_pdu_rel15.bchPayload; for (int i=0; ipbch_a |= ((pbch_pdu[2-(i>>3)]>>(7-(i&7)))&1)<bch_pdu.bch_pdu_rel15.length == 3, "BCH PDU has length %d != 3\n", - dl_config_pdu->bch_pdu.bch_pdu_rel15.length); + AssertFatal(dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag== 1, "bchPayloadFlat %d != 1\n", + dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag); - LOG_D(PHY,"pbch_pdu[0]: %x,pbch_pdu[1]: %x,gNB->pbch_pdu[2]: %x\n",sdu[0],sdu[1],sdu[2]); - gNB->pbch_pdu[0] = sdu[2]; - gNB->pbch_pdu[1] = sdu[1]; - gNB->pbch_pdu[2] = sdu[0]; - - // adjust transmit amplitude here based on NFAPI info + LOG_D(PHY,"pbch_pdu: %x\n",dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayload); + gNB->ssb_pdu = &dl_tti_pdu->ssb_pdu; } /*void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int subframe,gNB_L1_rxtx_proc_t *proc, @@ -86,7 +78,7 @@ void handle_nr_nfapi_bch_pdu(PHY_VARS_gNB *gNB, //AssertFatal(sdu!=NULL,"NFAPI: SFN/SF:%04d%d proc:TX:[frame %d subframe %d]: programming dlsch for round 0, rnti %x, UE_id %d, harq_pid %d : sdu is null for pdu_index %d dlsch0_harq[round:%d SFN/SF:%d%d pdu:%p mcs:%d ndi:%d pdschstart:%d]\n", // frame,subframe, // proc->frame_tx,proc->subframe_tx,rel8->rnti,UE_id,harq_pid, - // dl_config_pdu->pdsch_pdu.pdsch_pdu_rel8.pdu_index,dlsch0_harq->round,dlsch0_harq->frame,dlsch0_harq->subframe,dlsch0_harq->pdu,dlsch0_harq->mcs,dlsch0_harq->ndi,dlsch0_harq->pdsch_start); + // dl_tti_pdu->pdsch_pdu.pdsch_pdu_rel8.pdu_index,dlsch0_harq->round,dlsch0_harq->frame,dlsch0_harq->subframe,dlsch0_harq->pdu,dlsch0_harq->mcs,dlsch0_harq->ndi,dlsch0_harq->pdsch_start); if (codeword_index == 0) dlsch0_harq->pdu = sdu; else dlsch1_harq->pdu = sdu; LOG_I(PHY, "SFN/SF: %d/%d DLSCH PDU filled \n",frame, subframe); @@ -97,7 +89,7 @@ void handle_nr_nfapi_bch_pdu(PHY_VARS_gNB *gNB, void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB, int frame, int slot, - nfapi_nr_dl_config_pdcch_pdu *pdcch_pdu) { + nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu) { LOG_D(PHY,"Frame %d, Slot %d: DCI processing - proc:slot_tx:%d pdcch_pdu_rel15->numDlDci:%d\n",frame,slot, slot, pdcch_pdu->pdcch_pdu_rel15.numDlDci); @@ -112,7 +104,7 @@ void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB, void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot, - nfapi_nr_dl_config_pdsch_pdu *pdsch_pdu, + nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, uint8_t *sdu) { @@ -127,8 +119,8 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ // copy data from L2 interface into L1 structures module_id_t Mod_id = Sched_INFO->module_id; uint8_t CC_id = Sched_INFO->CC_id; - nfapi_nr_dl_config_request_t *DL_req = Sched_INFO->DL_req; - nfapi_tx_request_t *TX_req = Sched_INFO->TX_req; + nfapi_nr_dl_tti_request_t *DL_req = Sched_INFO->DL_req; + nfapi_nr_tx_data_request_t *TX_req = Sched_INFO->TX_req; nfapi_nr_ul_tti_request_t *UL_tti_req = Sched_INFO->UL_tti_req; frame_t frame = Sched_INFO->frame; sub_frame_t slot = Sched_INFO->slot; @@ -138,15 +130,14 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ gNB = RC.gNB[Mod_id]; - uint8_t number_dl_pdu = DL_req->dl_config_request_body.number_pdu; + uint8_t number_dl_pdu = DL_req->dl_tti_request_body.nPDUs; uint8_t number_ul_pdu = UL_tti_req->n_pdus; - - LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SF:%04d%d DL_req:SFN/SF:%04d%d:dl_pdu:%d tx_req:SFN/SF:%04d%d:pdus:%d \n", + LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SLOT:%04d%d DL_req:SFN/SLO:%04d%d:dl_pdu:%d tx_req:SFN/SLOT:%04d%d:pdus:%d \n", frame,slot, - NFAPI_SFNSF2SFN(DL_req->sfn_sf),NFAPI_SFNSF2SF(DL_req->sfn_sf),number_dl_pdu, - NFAPI_SFNSF2SFN(TX_req->sfn_sf),NFAPI_SFNSF2SF(TX_req->sfn_sf),TX_req->tx_request_body.number_of_pdus); + DL_req->SFN,DL_req->Slot,number_dl_pdu, + TX_req->SFN,TX_req->Slot,TX_req->Number_of_PDUs); int do_oai =0; int dont_send =0; @@ -155,41 +146,38 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ gNB->pdcch_pdu = NULL; for (int i=0;idl_config_request_body.dl_config_pdu_list[i]; - LOG_D(PHY,"NFAPI: dl_pdu %d : type %d\n",i,dl_config_pdu->pdu_type); - switch (dl_config_pdu->pdu_type) { - case NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE: - AssertFatal(dl_config_pdu->bch_pdu.bch_pdu_rel15.pdu_index < TX_req->tx_request_body.number_of_pdus, - "bch_pdu.bch_pdu_rel8.pdu_index>=TX_req->number_of_pdus (%d>%d)\n", - dl_config_pdu->bch_pdu.bch_pdu_rel15.pdu_index, - TX_req->tx_request_body.number_of_pdus); - gNB->pbch_configured=1; + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdu = &DL_req->dl_tti_request_body.dl_tti_pdu_list[i]; + LOG_D(PHY,"NFAPI: dl_pdu %d : type %d\n",i,dl_tti_pdu->PDUType); + switch (dl_tti_pdu->PDUType) { + case NFAPI_NR_DL_TTI_SSB_PDU_TYPE: + gNB->pbch_configured=1; do_oai=1; - handle_nr_nfapi_bch_pdu(gNB, - dl_config_pdu, - TX_req->tx_request_body.tx_pdu_list[dl_config_pdu->bch_pdu.bch_pdu_rel15.pdu_index].segments[0].segment_data); + handle_nr_nfapi_ssb_pdu(gNB, + dl_tti_pdu); + break; - case NFAPI_NR_DL_CONFIG_PDCCH_PDU_TYPE: + case NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE: AssertFatal(pdcch_received == 0, "pdcch_received is not 0, we can only handle one PDCCH PDU per slot\n"); handle_nfapi_nr_pdcch_pdu(gNB, frame, slot, - &dl_config_pdu->pdcch_pdu); - gNB->pdcch_pdu = &dl_config_pdu->pdcch_pdu; + &dl_tti_pdu->pdcch_pdu); + pdcch_received = 1; do_oai=1; break; - case NFAPI_NR_DL_CONFIG_PDSCH_PDU_TYPE: + case NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE: { - nfapi_nr_dl_config_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_config_pdu->pdsch_pdu.pdsch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdu->pdsch_pdu.pdsch_pdu_rel15; uint16_t pduIndex = pdsch_pdu_rel15->pduIndex; - uint16_t tx_pdus = TX_req->tx_request_body.number_of_pdus; - uint16_t invalid_pdu = pduIndex == -1; - uint8_t *sdu = invalid_pdu ? NULL : pduIndex >= tx_pdus ? NULL : TX_req->tx_request_body.tx_pdu_list[pduIndex].segments[0].segment_data; - AssertFatal(sdu!=NULL,"sdu is null, pduIndex %d, tx_pdus %d\n",pduIndex,tx_pdus); - handle_nr_nfapi_pdsch_pdu(gNB,frame,slot,&dl_config_pdu->pdsch_pdu, sdu); + uint16_t tx_pdus = TX_req->Number_of_PDUs; + AssertFatal(tx_pdus < pduIndex, "tx_pdus %d < pduIndex %d\n",tx_pdus, pduIndex); + AssertFatal(TX_req->pdu_list[pduIndex].num_TLV == 1, "TX_req->pdu_list[%d].num_TLV %d != 1\n", + pduIndex,TX_req->pdu_list[pduIndex].num_TLV); + uint8_t *sdu = TX_req->pdu_list[pduIndex].TLVs[0].value.direct; + handle_nr_nfapi_pdsch_pdu(gNB,frame,slot,&dl_tti_pdu->pdsch_pdu, sdu); do_oai=1; } } @@ -200,8 +188,8 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ /* // this is done in phy_procedures_gNB_uespec_RX now for (i=0;ipdus_list[i].pdu_type); - switch (UL_tti_req->pdus_list[i].pdu_type) { + LOG_D(PHY,"NFAPI: dl_pdu %d : type %d\n",i,UL_tti_req->pdus_list[i].PDUType); + switch (UL_tti_req->pdus_list[i].PDUType) { case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE: { nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu; @@ -210,10 +198,4 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ } } */ - - if (nfapi_mode && do_oai && !dont_send) { - oai_nfapi_tx_req(Sched_INFO->TX_req); - - oai_nfapi_nr_dl_config_req(Sched_INFO->DL_req); // DJP - .dl_config_request_body.dl_config_pdu_list[0]); // DJP - FIXME TODO - yuk - only copes with 1 pdu - } } diff --git a/openair1/SCHED_NR/fapi_nr_l1.h b/openair1/SCHED_NR/fapi_nr_l1.h index face0dd757..c35ae82c0b 100644 --- a/openair1/SCHED_NR/fapi_nr_l1.h +++ b/openair1/SCHED_NR/fapi_nr_l1.h @@ -34,15 +34,16 @@ #include "PHY/phy_extern.h" #include "SCHED_NR/sched_nr.h" #include "nfapi_nr_interface.h" +#include "nfapi_nr_interface_scf.h" void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO); void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB, int frame, int subframe, - nfapi_nr_dl_config_pdcch_pdu *dcl_dl_pdu); + nfapi_nr_dl_tti_pdcch_pdu *dcl_dl_pdu); void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot, - nfapi_nr_dl_config_pdsch_pdu *pdsch_pdu, + nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, uint8_t *sdu); void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int UE_id, uint8_t harq_pid); diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c index 02da848fbf..479036b22b 100644 --- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c +++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c @@ -93,7 +93,6 @@ void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame, int slot) { NR_DL_FRAME_PARMS *fp=&gNB->frame_parms; nfapi_nr_config_request_t *cfg = &gNB->gNB_config; int **txdataF = gNB->common_vars.txdataF; - uint8_t *pbch_pdu=&gNB->pbch_pdu[0]; uint8_t ssb_index, n_hf; int ssb_start_symbol, rel_slot; @@ -133,13 +132,13 @@ void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame, int slot) { nr_generate_pbch_dmrs(gNB->nr_gold_pbch_dmrs[0][ssb_index],txdataF[0], AMP, ssb_start_symbol, cfg, fp); nr_generate_pbch(&gNB->pbch, - pbch_pdu, - gNB->nr_pbch_interleaver, - txdataF[0], - AMP, - ssb_start_symbol, - n_hf,fp->Lmax,ssb_index, - frame, cfg, fp); + gNB->ssb_pdu, + gNB->nr_pbch_interleaver, + txdataF[0], + AMP, + ssb_start_symbol, + n_hf,fp->Lmax,ssb_index, + frame, cfg, fp); } } } diff --git a/openair1/SCHED_NR/sched_nr.h b/openair1/SCHED_NR/sched_nr.h index 7d8c4ef854..a65531ccd0 100644 --- a/openair1/SCHED_NR/sched_nr.h +++ b/openair1/SCHED_NR/sched_nr.h @@ -50,16 +50,4 @@ void nr_fep_full_2thread(RU_t *ru, int slot); void feptx_prec(RU_t *ru,int frame_tx,int tti_tx); int nr_phy_init_RU(RU_t *ru); -void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params, - nr_scs_e scs_common, - nr_scs_e pdcch_scs, - nr_frequency_range_e freq_range, - uint8_t rmsi_pdcch_config, - uint8_t ssb_idx, - uint8_t k_ssb, - uint16_t sfn_ssb, - uint8_t n_ssb, - uint16_t nb_slots_per_frame, - uint16_t N_RB); - #endif diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index 811703ea49..da53683bd6 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -75,30 +75,33 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB, frame_t frameP, sub_frame_t slotP){ - nfapi_nr_dl_config_request_t *DL_req = &gNB->DL_req[0]; - nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req[0]; - nfapi_hi_dci0_request_t * HI_DCI0_req = &gNB->HI_DCI0_req[0]; - nfapi_tx_request_t *TX_req = &gNB->TX_req[0]; + nfapi_nr_dl_tti_request_t *DL_req = &gNB->DL_req[0]; + nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req[0]; + nfapi_nr_ul_dci_request_t *ul_dci_req = &gNB->ul_dci_req[0]; + nfapi_nr_tx_data_request_t *TX_req = &gNB->TX_req[0]; gNB->pdu_index[CC_idP] = 0; if (nfapi_mode==0 || nfapi_mode == 1) { // monolithic or PNF - DL_req[CC_idP].dl_config_request_body.number_dci = 0; - DL_req[CC_idP].dl_config_request_body.number_pdu = 0; - DL_req[CC_idP].dl_config_request_body.number_pdsch_rnti = 0; - //DL_req[CC_idP].dl_config_request_body.transmission_power_pcfich = 6000; - - HI_DCI0_req[CC_idP].hi_dci0_request_body.sfnsf = slotP + (frameP<<7); - HI_DCI0_req[CC_idP].hi_dci0_request_body.number_of_dci = 0; + DL_req[CC_idP].SFN = frameP; + DL_req[CC_idP].Slot = slotP; + DL_req[CC_idP].dl_tti_request_body.nPDUs = 0; + DL_req[CC_idP].dl_tti_request_body.nGroup = 0; + //DL_req[CC_idP].dl_tti_request_body.transmission_power_pcfich = 6000; + ul_dci_req[CC_idP].SFN = frameP; + ul_dci_req[CC_idP].Slot = slotP; + ul_dci_req[CC_idP].numPdus = 0; + UL_tti_req[CC_idP].SFN = frameP; + UL_tti_req[CC_idP].Slot = slotP; UL_tti_req[CC_idP].n_pdus = 0; UL_tti_req[CC_idP].n_ulsch = 0; UL_tti_req[CC_idP].n_ulcch = 0; UL_tti_req[CC_idP].n_group = 0; - TX_req[CC_idP].tx_request_body.number_of_pdus = 0; + TX_req[CC_idP].Number_of_PDUs = 0; } } @@ -110,7 +113,7 @@ void check_nr_ul_failure(module_id_t module_idP, sub_frame_t slotP) { UE_list_t *UE_list = &RC.nrmac[module_idP]->UE_list; - nfapi_nr_dl_config_request_t *DL_req = &RC.nrmac[module_idP]->DL_req[0]; + nfapi_nr_dl_dci_request_t *DL_req = &RC.nrmac[module_idP]->DL_req[0]; uint16_t rnti = UE_RNTI(module_idP, UE_id); NR_COMMON_channels_t *cc = RC.nrmac[module_idP]->common_channels; @@ -123,11 +126,11 @@ void check_nr_ul_failure(module_id_t module_idP, UE_list->UE_sched_ctrl[UE_id].ra_pdcch_order_sent = 1; // add a format 1A dci for this UE to request an RA procedure (only one UE per subframe) - nfapi_nr_dl_config_request_pdu_t *dl_config_pdu = &DL_req[CC_id].dl_config_request_body.dl_config_pdu_list[DL_req[CC_id].dl_config_request_body.number_pdu]; - memset((void *) dl_config_pdu, 0,sizeof(nfapi_dl_config_request_pdu_t)); + nfapi_nr_dl_dci_request_pdu_t *dl_config_pdu = &DL_req[CC_id].dl_tti_request_body.dl_config_pdu_list[DL_req[CC_id].dl_tti_request_body.number_pdu]; + memset((void *) dl_config_pdu, 0,sizeof(nfapi_dl_dci_request_pdu_t)); dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE; dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dci_dl_pdu)); - dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG; + dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_DCI_REQUEST_DCI_DL_PDU_REL8_TAG; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = NFAPI_DL_DCI_FORMAT_1A; dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = get_aggregation(get_bw_index(module_idP, CC_id), UE_list->UE_sched_ctrl[UE_id]. @@ -140,9 +143,9 @@ void check_nr_ul_failure(module_id_t module_idP, "illegal dl_Bandwidth %d\n", (int) cc[CC_id].mib->message.dl_Bandwidth); dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = nr_pdcch_order_table[cc[CC_id].mib->message.dl_Bandwidth]; - DL_req[CC_id].dl_config_request_body.number_dci++; - DL_req[CC_id].dl_config_request_body.number_pdu++; - DL_req[CC_id].dl_config_request_body.tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; + DL_req[CC_id].dl_tti_request_body.number_dci++; + DL_req[CC_id].dl_tti_request_body.number_pdu++; + DL_req[CC_id].dl_tti_request_body.tl.tag = NFAPI_DL_TTI_REQUEST_BODY_TAG; LOG_I(MAC, "UE %d rnti %x: sending PDCCH order for RAPROC (failure timer %d), resource_block_coding %d \n", UE_id, rnti, diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c index ffa3c1b1d0..98e18ab992 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c @@ -62,23 +62,21 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ gNB_MAC_INST *gNB = RC.nrmac[module_idP]; NR_COMMON_channels_t *cc; - nfapi_nr_dl_config_request_t *dl_config_request; - nfapi_nr_dl_config_request_body_t *dl_req; - nfapi_nr_dl_config_request_pdu_t *dl_config_pdu; - nfapi_tx_request_pdu_t *TX_req; + nfapi_nr_dl_tti_request_t *dl_tti_request; + nfapi_nr_dl_tti_request_body_t *dl_req; + nfapi_nr_dl_tti_request_pdu_t *dl_config_pdu; int mib_sdu_length; int CC_id; - uint16_t sfn_sf = frameP << 7 | slotP; AssertFatal(slotP == 0, "Subframe must be 0\n"); AssertFatal((frameP & 7) == 0, "Frame must be a multiple of 8\n"); for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { - dl_config_request = &gNB->DL_req[CC_id]; - dl_req = &dl_config_request->dl_config_request_body; + dl_tti_request = &gNB->DL_req[CC_id]; + dl_req = &dl_tti_request->dl_tti_request_body; cc = &gNB->common_channels[CC_id]; mib_sdu_length = mac_rrc_nr_data_req(module_idP, CC_id, frameP, MIBCH, 1, &cc->MIB_pdu.payload[0]); // not used in this case @@ -87,38 +85,59 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ if (mib_sdu_length > 0) { - LOG_D(MAC, "Frame %d, slot %d: Adding BCH PDU in position %d (length %d)\n", frameP, slotP, dl_req->number_pdu, mib_sdu_length); + LOG_D(MAC, "Frame %d, slot %d: Adding BCH PDU in position %d (length %d)\n", frameP, slotP, dl_req->nPDUs, mib_sdu_length); if ((frameP & 1023) < 80){ LOG_D(MAC,"[gNB %d] Frame %d : MIB->BCH CC_id %d, Received %d bytes\n",module_idP, frameP, CC_id, mib_sdu_length); } - dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; - memset((void *) dl_config_pdu, 0,sizeof(nfapi_nr_dl_config_request_pdu_t)); - dl_config_pdu->pdu_type = NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE; - dl_config_pdu->pdu_size =2 + sizeof(nfapi_nr_dl_config_bch_pdu_rel15_t); - dl_config_pdu->bch_pdu.bch_pdu_rel15.tl.tag = NFAPI_NR_DL_CONFIG_REQUEST_BCH_PDU_REL15_TAG; - dl_config_pdu->bch_pdu.bch_pdu_rel15.length = mib_sdu_length; - dl_config_pdu->bch_pdu.bch_pdu_rel15.pdu_index = gNB->pdu_index[CC_id]; - dl_config_pdu->bch_pdu.bch_pdu_rel15.transmission_power = 6000; - dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG; - dl_req->number_pdu++; - dl_config_request->header.message_id = NFAPI_DL_CONFIG_REQUEST; - dl_config_request->sfn_sf = sfn_sf; + dl_config_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; + memset((void *) dl_config_pdu, 0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_config_pdu->PDUType = NFAPI_NR_DL_TTI_SSB_PDU_TYPE; + dl_config_pdu->PDUSize =2 + sizeof(nfapi_nr_dl_tti_ssb_pdu_rel15_t); - LOG_D(MAC, "gNB->DL_req[0].number_pdu %d (%p)\n", dl_req->number_pdu, &dl_req->number_pdu); - // DL request - - TX_req = &gNB->TX_req[CC_id].tx_request_body.tx_pdu_list[gNB->TX_req[CC_id].tx_request_body.number_of_pdus]; - TX_req->pdu_length = 3; - TX_req->pdu_index = gNB->pdu_index[CC_id]++; - TX_req->num_segments = 1; - TX_req->segments[0].segment_length = 3; - TX_req->segments[0].segment_data = cc[CC_id].MIB_pdu.payload; - gNB->TX_req[CC_id].tx_request_body.number_of_pdus++; - gNB->TX_req[CC_id].sfn_sf = sfn_sf; - gNB->TX_req[CC_id].tx_request_body.tl.tag = NFAPI_TX_REQUEST_BODY_TAG; - gNB->TX_req[CC_id].header.message_id = NFAPI_TX_REQUEST; + AssertFatal(cc->ServingCellConfigCommon->physCellId!=NULL,"cc->ServingCellConfigCommon->physCellId is null\n"); + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.PhysCellId = *cc->ServingCellConfigCommon->physCellId; + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.BetaPss = 0; + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.SsbBlockIndex = 0; + AssertFatal(cc->ServingCellConfigCommon->downlinkConfigCommon!=NULL,"scc->downlinkConfigCommonL is null\n"); + AssertFatal(cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL!=NULL,"scc->downlinkConfigCommon->frequencyInfoDL is null\n"); + AssertFatal(cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB!=NULL,"scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB is null\n"); + AssertFatal(cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.count!=1,"Frequency Band list does not have 1 element (%d)\n",cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.count); + AssertFatal(cc->ServingCellConfigCommon->ssbSubcarrierSpacing,"ssbSubcarrierSpacing is null\n"); + AssertFatal(cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0],"band is null\n"); + long band = *cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0]; + uint32_t ssb_offset0 = cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB - cc->ServingCellConfigCommon->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA; + int ratio; + switch (*cc->ServingCellConfigCommon->ssbSubcarrierSpacing) { + case NR_SubcarrierSpacing_kHz15: + AssertFatal(band <= 79, "Band %d is not possible for SSB with 15 kHz SCS\n",band); + if (band<77) // below 3GHz + ratio=3; // NRARFCN step is 5 kHz + else + ratio=1; // NRARFCN step is 15 kHz + break; + case NR_SubcarrierSpacing_kHz30: + AssertFatal(band <= 79, "Band %d is not possible for SSB with 15 kHz SCS\n",band); + if (band<77) // below 3GHz + ratio=6; // NRARFCN step is 5 kHz + else + ratio=2; // NRARFCN step is 15 kHz + break; + case NR_SubcarrierSpacing_kHz120: + AssertFatal(band >= 257, "Band %d is not possible for SSB with 120 kHz SCS\n",band); + ratio=8; // NRARFCN step is 15 kHz + break; + case NR_SubcarrierSpacing_kHz240: + AssertFatal(band >= 257, "Band %d is not possible for SSB with 240 kHz SCS\n",band); + ratio=16; // NRARFCN step is 15 kHz + break; + } + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.SsbSubcarrierOffset = 0; //kSSB + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.ssbOffsetPointA = ssb_offset0/ratio; + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag = 1; + dl_config_pdu->ssb_pdu.ssb_pdu_rel15.bchPayload = ((uint32_t)cc->MIB_pdu.payload[0]) & ((1<<24)-1); + dl_req->nPDUs++; } } } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 38ddf758dd..acaa7fa69d 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -62,17 +62,16 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, uint8_t CC_id; gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[0]; - nfapi_nr_dl_config_request_body_t *dl_req; - nfapi_nr_dl_config_request_pdu_t *dl_config_pdcch_pdu; - nfapi_nr_dl_config_request_pdu_t *dl_config_pdsch_pdu; - nfapi_tx_request_pdu_t *TX_req; + nfapi_nr_dl_tti_request_body_t *dl_req; + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu; + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu; + nfapi_nr_pdu_t *TX_req; uint16_t rnti = 0x1234; NR_ServingCellConfigCommon_t *scc=cc->ServingCellConfigCommon; - uint16_t sfn_sf = frameP << 7 | slotP; int dlBWP_carrier_bandwidth = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,275); // everything here is hard-coded to 30 kHz @@ -86,20 +85,20 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, NRRIV2PRBOFFSET(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,275)); - dl_req = &nr_mac->DL_req[CC_id].dl_config_request_body; - dl_config_pdcch_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; - memset((void*)dl_config_pdcch_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); - dl_config_pdcch_pdu->pdu_type = NFAPI_NR_DL_CONFIG_PDCCH_PDU_TYPE; - dl_config_pdcch_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_pdcch_pdu)); + dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body; + dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; + memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_tti_pdcch_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE; + dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu)); - dl_config_pdsch_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu+1]; - memset((void *)dl_config_pdsch_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); - dl_config_pdsch_pdu->pdu_type = NFAPI_NR_DL_CONFIG_PDSCH_PDU_TYPE; - dl_config_pdsch_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_pdsch_pdu)); + dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs+1]; + memset((void *)dl_tti_pdsch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE; + dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdsch_pdu)); - nfapi_nr_dl_config_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_config_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15; - nfapi_nr_dl_config_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_config_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; pdsch_pdu_rel15->pduBitmap = 0; pdsch_pdu_rel15->rnti = rnti; @@ -216,7 +215,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, params_rel15->nb_slots, params_rel15->sfn_mod2, params_rel15->first_slot); - nr_get_tbs_dl(&dl_config_pdsch_pdu->pdsch_pdu, dl_config_dci_pdu->dci_dl_pdu,0); + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, dl_tti_dci_pdu->dci_dl_pdu,0); LOG_D(MAC, "DLSCH PDU: start PRB %d n_PRB %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d\n", pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbSize, @@ -227,35 +226,31 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, pdsch_pdu_rel15->mcsIndex[0]); */ - dl_req->number_dci++; - dl_req->number_pdsch_rnti++; - dl_req->number_pdu+=2; - - TX_req = &nr_mac->TX_req[CC_id].tx_request_body.tx_pdu_list[nr_mac->TX_req[CC_id].tx_request_body.number_of_pdus]; - TX_req->pdu_length = 6; - TX_req->pdu_index = nr_mac->pdu_index[CC_id]++; - TX_req->num_segments = 1; - TX_req->segments[0].segment_length = 8; - TX_req->segments[0].segment_data = &cc[CC_id].RAR_pdu.payload[0]; - nr_mac->TX_req[CC_id].tx_request_body.number_of_pdus++; - nr_mac->TX_req[CC_id].sfn_sf = sfn_sf; - nr_mac->TX_req[CC_id].tx_request_body.tl.tag = NFAPI_TX_REQUEST_BODY_TAG; - nr_mac->TX_req[CC_id].header.message_id = NFAPI_TX_REQUEST; + dl_req->nPDUs+=2; + TX_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs]; + TX_req->PDU_length = 6; + TX_req->PDU_index = nr_mac->pdu_index[CC_id]++; + TX_req->num_TLV = 1; + TX_req->TLVs[0].length = 8; + memcpy((void*)&TX_req->TLVs[0].value.direct[0],(void*)&cc[CC_id].RAR_pdu.payload[0],TX_req->TLVs[0].length); + nr_mac->TX_req[CC_id].Number_of_PDUs++; + nr_mac->TX_req[CC_id].SFN=frameP; + nr_mac->TX_req[CC_id].Slot=slotP; } } int configure_fapi_dl_Tx(int Mod_idP, - nfapi_nr_dl_config_request_body_t *dl_req, - nfapi_tx_request_pdu_t *TX_req, - int16_t pdu_index) { + nfapi_nr_dl_tti_request_body_t *dl_req, + nfapi_nr_pdu_t *TX_req) { + gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP]; NR_COMMON_channels_t *cc = nr_mac->common_channels; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; - nfapi_nr_dl_config_request_pdu_t *dl_config_pdcch_pdu; - nfapi_nr_dl_config_request_pdu_t *dl_config_pdsch_pdu; + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu; + nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu; int TBS; @@ -280,18 +275,18 @@ int configure_fapi_dl_Tx(int Mod_idP, NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]; - dl_config_pdcch_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu]; - memset((void*)dl_config_pdcch_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); - dl_config_pdcch_pdu->pdu_type = NFAPI_NR_DL_CONFIG_PDCCH_PDU_TYPE; - dl_config_pdcch_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_pdcch_pdu)); + dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs]; + memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_tti_pdcch_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE; + dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu)); - dl_config_pdsch_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu+1]; - memset((void*)dl_config_pdsch_pdu,0,sizeof(nfapi_nr_dl_config_request_pdu_t)); - dl_config_pdsch_pdu->pdu_type = NFAPI_NR_DL_CONFIG_PDSCH_PDU_TYPE; - dl_config_pdsch_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_nr_dl_config_pdsch_pdu)); + dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs+1]; + memset((void*)dl_tti_pdsch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t)); + dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE; + dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdsch_pdu)); - nfapi_nr_dl_config_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_config_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15; - nfapi_nr_dl_config_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_config_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; + nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15; pdsch_pdu_rel15->pduBitmap = 0; @@ -403,10 +398,10 @@ int configure_fapi_dl_Tx(int Mod_idP, pdcch_pdu_rel15->DurationSymbols); int x_Overhead = 0; // should be 0 for initialBWP - nr_get_tbs_dl(&dl_config_pdsch_pdu->pdsch_pdu, + nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead); // Hardcode it for now - TBS = dl_config_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]; + TBS = dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]; LOG_I(MAC, "DLSCH PDU: start PRB %d n_PRB %d startSymbolAndLength %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS: %d\n", pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbSize, @@ -418,31 +413,32 @@ int configure_fapi_dl_Tx(int Mod_idP, pdsch_pdu_rel15->mcsIndex[0], TBS); - dl_req->number_dci++; - dl_req->number_pdsch_rnti++; - dl_req->number_pdu+=2; - - TX_req->pdu_length = pdsch_pdu_rel15->TBSize[0]; - TX_req->pdu_index = pdu_index++; - TX_req->num_segments = 1; + dl_req->nPDUs+=2; + + TX_req->PDU_length = pdsch_pdu_rel15->TBSize[0]; + TX_req->PDU_index = nr_mac->pdu_index[0]++; + + // TX_req->num_TLV = 1; + // TX_req->TLVs[0].length = 8; + // memcpy((void*)&TX_req->TLVs[0].value.direct[0],(void*)&cc[CC_id].RAR_pdu.payload[0],TX_req->TLVs[0].length); + return TBS/8; //Return TBS in bytes } void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, - nfapi_nr_dl_config_pdsch_pdu_rel15_t *dlsch_config) + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *dlsch_config) { LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest \n"); gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; //NR_COMMON_channels_t *cc = nr_mac->common_channels; //NR_ServingCellConfigCommon_t *scc=cc->ServingCellConfigCommon; - nfapi_nr_dl_config_request_body_t *dl_req; - nfapi_tx_request_pdu_t *TX_req; + nfapi_nr_dl_tti_request_body_t *dl_req; + nfapi_nr_pdu_t *TX_req; uint16_t rnti = 0x1234; - uint16_t sfn_sf = frameP << 7 | slotP; int TBS; int TBS_bytes; @@ -468,8 +464,8 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, LOG_D(MAC, "Scheduling UE specific search space DCI type 1\n"); int CC_id=0; - dl_req = &nr_mac->DL_req[CC_id].dl_config_request_body; - TX_req = &nr_mac->TX_req[CC_id].tx_request_body.tx_pdu_list[nr_mac->TX_req[CC_id].tx_request_body.number_of_pdus]; + dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body; + TX_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs]; //The --NOS1 use case currently schedules DLSCH transmissions only when there is IP traffic arriving //through the LTE stack @@ -481,7 +477,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, // Hardcode it for now TBS = 6784/8; //TBS in bytes - //TBS = dl_config_pdsch_pdu->pdsch_pdu.dlsch_pdu_rel15.transport_block_size; + //TBS = dl_tti_pdsch_pdu->pdsch_pdu.dlsch_pdu_rel15.transport_block_size; for (lcid = NB_RB_MAX - 1; lcid >= DTCH; lcid--) { // TODO: check if the lcid is active @@ -589,8 +585,9 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, nr_mac->UE_list.DLSCH_pdu[0][0].payload[0][offset + sdu_length_total + j] = 0; } - TBS_bytes = configure_fapi_dl_Tx(module_idP,dl_req, TX_req, - nr_mac->pdu_index[CC_id]); + TBS_bytes = configure_fapi_dl_Tx(module_idP, + dl_req, + TX_req); #if defined(ENABLE_MAC_PAYLOAD_DEBUG) LOG_I(MAC, "Printing first 10 payload bytes at the gNB side, Frame: %d, slot: %d, , TBS size: %d \n \n", frameP, slotP, TBS_bytes); @@ -599,23 +596,21 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, } #endif - //TX_req->segments[0].segment_length = 8; - TX_req->segments[0].segment_length = TBS_bytes +2; - TX_req->segments[0].segment_data = nr_mac->UE_list.DLSCH_pdu[0][0].payload[0]; + TX_req->num_TLV=1; + TX_req->TLVs[0].length = TBS_bytes +2; + memcpy((void*)&TX_req->TLVs[0].value.direct[0],(void*)&nr_mac->UE_list.DLSCH_pdu[0][0].payload[0],TBS_bytes);; - nr_mac->TX_req[CC_id].tx_request_body.number_of_pdus++; - nr_mac->TX_req[CC_id].sfn_sf = sfn_sf; - nr_mac->TX_req[CC_id].tx_request_body.tl.tag = NFAPI_TX_REQUEST_BODY_TAG; - nr_mac->TX_req[CC_id].header.message_id = NFAPI_TX_REQUEST; + nr_mac->TX_req[CC_id].Number_of_PDUs++; + nr_mac->TX_req[CC_id].SFN = frameP; + nr_mac->TX_req[CC_id].Slot = slotP; } //if (ta_len + sdu_length_total + header_length_total > 0) } //if (IS_SOFTMODEM_NOS1) //When the --NOS1 option is not enabled, DLSCH transmissions with random data //occur every time that the current function is called (dlsch phytest mode) else{ - TBS_bytes = configure_fapi_dl_Tx(module_idP,dl_req, TX_req, - nr_mac->pdu_index[CC_id]); + TBS_bytes = configure_fapi_dl_Tx(module_idP,dl_req, TX_req); // HOT FIX for all zero pdu problem // ------------------------------------------------------------------------------------------------ @@ -633,13 +628,15 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, #endif //TX_req->segments[0].segment_length = 8; - TX_req->segments[0].segment_length = TBS_bytes +2; - TX_req->segments[0].segment_data = nr_mac->UE_list.DLSCH_pdu[0][0].payload[0]; + TX_req->num_TLV=1; + TX_req->TLVs[0].length = TBS_bytes +2; + memcpy((void*)&TX_req->TLVs[0].value.direct[0], + (void*)&nr_mac->UE_list.DLSCH_pdu[0][0].payload[0], + TBS_bytes); - nr_mac->TX_req[CC_id].tx_request_body.number_of_pdus++; - nr_mac->TX_req[CC_id].sfn_sf = sfn_sf; - nr_mac->TX_req[CC_id].tx_request_body.tl.tag = NFAPI_TX_REQUEST_BODY_TAG; - nr_mac->TX_req[CC_id].header.message_id = NFAPI_TX_REQUEST; + nr_mac->TX_req[CC_id].Number_of_PDUs++; + nr_mac->TX_req[CC_id].SFN = frameP; + nr_mac->TX_req[CC_id].Slot = slotP; // ------------------------------------------------------------------------------------------------ } } @@ -655,8 +652,8 @@ void nr_schedule_uss_ulsch_phytest(nfapi_nr_ul_tti_request_t *UL_tti_req, for (uint8_t CC_id=0; CC_idUL_tti_req[CC_id]; - UL_tti_req->sfn = frameP; - UL_tti_req->slot = slotP; + UL_tti_req->SFN = frameP; + UL_tti_req->Slot = slotP; UL_tti_req->n_pdus = 1; UL_tti_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE; UL_tti_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index b071797c54..3fb64a528c 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -134,7 +134,7 @@ int is_nr_UL_slot(NR_COMMON_channels_t * ccP, int slot){ return (0); } -void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params, +void nr_configure_css_dci_initial(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, nr_scs_e scs_common, nr_scs_e pdcch_scs, nr_frequency_range_e freq_range, @@ -152,6 +152,8 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p uint8_t mu = scs_common; uint8_t O_scale=0, M_scale=0; // used to decide if the values of O and M need to be divided by 2 + AssertFatal(1==0,"todo\n"); + /* /// Coreset params switch(scs_common) { @@ -160,18 +162,18 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p switch(pdcch_scs) { case kHz15: AssertFatal(cset_idx<15,"Coreset index %d reserved for scs kHz15/kHz15\n", cset_idx); - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = (cset_idx < 6)? 24 : (cset_idx < 12)? 48 : 96; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_15_15[cset_idx]; - pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_15_15[cset_idx]; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = (cset_idx < 6)? 24 : (cset_idx < 12)? 48 : 96; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_15_15[cset_idx]; + pdcch_pdu->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_15_15[cset_idx]; break; case kHz30: AssertFatal(cset_idx<14,"Coreset index %d reserved for scs kHz15/kHz30\n", cset_idx); - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = (cset_idx < 8)? 24 : 48; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_15_30[cset_idx]; - pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_15_15[cset_idx]; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = (cset_idx < 8)? 24 : 48; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_15_30[cset_idx]; + pdcch_pdu->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_15_15[cset_idx]; break; default: @@ -186,17 +188,17 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p switch(pdcch_scs) { case kHz15: AssertFatal(cset_idx<9,"Coreset index %d reserved for scs kHz30/kHz15\n", cset_idx); - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = (cset_idx < 10)? 48 : 96; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_15_b40Mhz[cset_idx]; - pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_15_b40Mhz[cset_idx]; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = (cset_idx < 10)? 48 : 96; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_15_b40Mhz[cset_idx]; + pdcch_pdu->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_15_b40Mhz[cset_idx]; break; case kHz30: - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = (cset_idx < 6)? 24 : 48; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_30_b40Mhz[cset_idx]; - pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_30_b40Mhz[cset_idx]; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = (cset_idx < 6)? 24 : 48; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_30_b40Mhz[cset_idx]; + pdcch_pdu->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_30_b40Mhz[cset_idx]; break; default: @@ -208,18 +210,18 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p switch(pdcch_scs) { case kHz15: AssertFatal(cset_idx<9,"Coreset index %d reserved for scs kHz30/kHz15\n", cset_idx); - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = (cset_idx < 3)? 48 : 96; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_15_a40Mhz[cset_idx]; - pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_15_a40Mhz[cset_idx]; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = (cset_idx < 3)? 48 : 96; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_15_a40Mhz[cset_idx]; + pdcch_pdu->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_15_a40Mhz[cset_idx]; break; case kHz30: AssertFatal(cset_idx<10,"Coreset index %d reserved for scs kHz30/kHz30\n", cset_idx); - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = (cset_idx < 4)? 24 : 48; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_30_a40Mhz[cset_idx]; - pdcch_params->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_30_a40Mhz[cset_idx]; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = (cset_idx < 4)? 24 : 48; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_30_30_a40Mhz[cset_idx]; + pdcch_pdu->rb_offset = nr_coreset_rb_offset_pdcch_type_0_scs_30_30_a40Mhz[cset_idx]; break; default: @@ -232,19 +234,19 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p switch(pdcch_scs) { case kHz60: AssertFatal(cset_idx<12,"Coreset index %d reserved for scs kHz120/kHz60\n", cset_idx); - pdcch_params->mux_pattern = (cset_idx < 8)?NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2; - pdcch_params->n_rb = (cset_idx < 6)? 48 : (cset_idx < 8)? 96 : (cset_idx < 10)? 48 : 96; - pdcch_params->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_120_60[cset_idx]; - pdcch_params->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_120_60[cset_idx]>0)?nr_coreset_rb_offset_pdcch_type_0_scs_120_60[cset_idx] : + pdcch_pdu->mux_pattern = (cset_idx < 8)?NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2; + pdcch_pdu->n_rb = (cset_idx < 6)? 48 : (cset_idx < 8)? 96 : (cset_idx < 10)? 48 : 96; + pdcch_pdu->n_symb = nr_coreset_nsymb_pdcch_type_0_scs_120_60[cset_idx]; + pdcch_pdu->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_120_60[cset_idx]>0)?nr_coreset_rb_offset_pdcch_type_0_scs_120_60[cset_idx] : (k_ssb == 0)? -41 : -42; break; case kHz120: AssertFatal(cset_idx<8,"Coreset index %d reserved for scs kHz120/kHz120\n", cset_idx); - pdcch_params->mux_pattern = (cset_idx < 4)?NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE3; - pdcch_params->n_rb = (cset_idx < 2)? 24 : (cset_idx < 4)? 48 : (cset_idx < 6)? 24 : 48; - pdcch_params->n_symb = (cset_idx == 2)? 1 : 2; - pdcch_params->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_120_120[cset_idx]>0)? nr_coreset_rb_offset_pdcch_type_0_scs_120_120[cset_idx] : + pdcch_pdu->mux_pattern = (cset_idx < 4)?NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE3; + pdcch_pdu->n_rb = (cset_idx < 2)? 24 : (cset_idx < 4)? 48 : (cset_idx < 6)? 24 : 48; + pdcch_pdu->n_symb = (cset_idx == 2)? 1 : 2; + pdcch_pdu->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_120_120[cset_idx]>0)? nr_coreset_rb_offset_pdcch_type_0_scs_120_120[cset_idx] : (k_ssb == 0)? -20 : -21; break; @@ -257,18 +259,18 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p switch(pdcch_scs) { case kHz60: AssertFatal(cset_idx<4,"Coreset index %d reserved for scs kHz240/kHz60\n", cset_idx); - pdcch_params->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; - pdcch_params->n_rb = 96; - pdcch_params->n_symb = (cset_idx < 2)? 1 : 2; - pdcch_params->rb_offset = (cset_idx&1)? 16 : 0; + pdcch_pdu->mux_pattern = NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1; + pdcch_pdu->n_rb = 96; + pdcch_pdu->n_symb = (cset_idx < 2)? 1 : 2; + pdcch_pdu->rb_offset = (cset_idx&1)? 16 : 0; break; case kHz120: AssertFatal(cset_idx<8,"Coreset index %d reserved for scs kHz240/kHz120\n", cset_idx); - pdcch_params->mux_pattern = (cset_idx < 4)? NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2; - pdcch_params->n_rb = (cset_idx < 4)? 48 : (cset_idx < 6)? 24 : 48; - pdcch_params->n_symb = ((cset_idx==2)||(cset_idx==3))? 2 : 1; - pdcch_params->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_240_120[cset_idx]>0)? nr_coreset_rb_offset_pdcch_type_0_scs_240_120[cset_idx] : + pdcch_pdu->mux_pattern = (cset_idx < 4)? NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1 : NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2; + pdcch_pdu->n_rb = (cset_idx < 4)? 48 : (cset_idx < 6)? 24 : 48; + pdcch_pdu->n_symb = ((cset_idx==2)||(cset_idx==3))? 2 : 1; + pdcch_pdu->rb_offset = (nr_coreset_rb_offset_pdcch_type_0_scs_240_120[cset_idx]>0)? nr_coreset_rb_offset_pdcch_type_0_scs_240_120[cset_idx] : (k_ssb == 0)? -41 : -42; break; @@ -283,29 +285,29 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p } /// Search space params - switch(pdcch_params->mux_pattern) { + switch(pdcch_pdu->mux_pattern) { case NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1: if (freq_range == nr_FR1) { O = nr_ss_param_O_type_0_mux1_FR1[ss_idx]; - pdcch_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR1[ss_idx]; + pdcch_pdu->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR1[ss_idx]; M = nr_ss_param_M_type_0_mux1_FR1[ss_idx]; M_scale = nr_ss_scale_M_mux1_FR1[ss_idx]; - pdcch_params->first_symbol = (ss_idx < 8)? ( (ssb_idx&1)? pdcch_params->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ss_idx - 8]; + pdcch_pdu->first_symbol = (ss_idx < 8)? ( (ssb_idx&1)? pdcch_pdu->n_symb : 0 ) : nr_ss_first_symb_idx_type_0_mux1_FR1[ss_idx - 8]; } else { AssertFatal(ss_idx<14 ,"Invalid search space index for multiplexing type 1 and FR2 %d\n", ss_idx); O = nr_ss_param_O_type_0_mux1_FR2[ss_idx]; O_scale = nr_ss_scale_O_mux1_FR2[ss_idx]; - pdcch_params->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR2[ss_idx]; + pdcch_pdu->nb_ss_sets_per_slot = nr_ss_sets_per_slot_type_0_FR2[ss_idx]; M = nr_ss_param_M_type_0_mux1_FR2[ss_idx]; M_scale = nr_ss_scale_M_mux1_FR2[ss_idx]; - pdcch_params->first_symbol = (ss_idx < 12)? ( (ss_idx&1)? 7 : 0 ) : 0; + pdcch_pdu->first_symbol = (ss_idx < 12)? ( (ss_idx&1)? 7 : 0 ) : 0; } - pdcch_params->nb_slots = 2; - pdcch_params->sfn_mod2 = (CEILIDIV( (((O<>O_scale) + ((ssb_idx*M)>>M_scale)), nb_slots_per_frame ) & 1)? 1 : 0; - pdcch_params->first_slot = (((O<>O_scale) + ((ssb_idx*M)>>M_scale)) % nb_slots_per_frame; + pdcch_pdu->nb_slots = 2; + pdcch_pdu->sfn_mod2 = (CEILIDIV( (((O<>O_scale) + ((ssb_idx*M)>>M_scale)), nb_slots_per_frame ) & 1)? 1 : 0; + pdcch_pdu->first_slot = (((O<>O_scale) + ((ssb_idx*M)>>M_scale)) % nb_slots_per_frame; break; @@ -314,14 +316,14 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p "Invalid scs_common/pdcch_scs combination %d/%d for Mux type 2\n", scs_common, pdcch_scs ); AssertFatal(ss_idx==0, "Search space index %d reserved for scs_common/pdcch_scs combination %d/%d", ss_idx, scs_common, pdcch_scs); - pdcch_params->nb_slots = 1; + pdcch_pdu->nb_slots = 1; if ((scs_common==kHz120)&&(pdcch_scs==kHz60)) { - pdcch_params->first_symbol = nr_ss_first_symb_idx_scs_120_60_mux2[ssb_idx&3]; - // Missing in pdcch_params sfn_C and n_C here and in else case + pdcch_pdu->first_symbol = nr_ss_first_symb_idx_scs_120_60_mux2[ssb_idx&3]; + // Missing in pdcch_pdu sfn_C and n_C here and in else case } else { - pdcch_params->first_symbol = ((ssb_idx&7)==4)?12 : ((ssb_idx&7)==4)?13 : nr_ss_first_symb_idx_scs_240_120_set1_mux2[ssb_idx&7]; //??? + pdcch_pdu->first_symbol = ((ssb_idx&7)==4)?12 : ((ssb_idx&7)==4)?13 : nr_ss_first_symb_idx_scs_240_120_set1_mux2[ssb_idx&7]; //??? } break; @@ -331,25 +333,26 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p "Invalid scs_common/pdcch_scs combination %d/%d for Mux type 3\n", scs_common, pdcch_scs ); AssertFatal(ss_idx==0, "Search space index %d reserved for scs_common/pdcch_scs combination %d/%d", ss_idx, scs_common, pdcch_scs); - pdcch_params->first_symbol = nr_ss_first_symb_idx_scs_120_120_mux3[ssb_idx&3]; + pdcch_pdu->first_symbol = nr_ss_first_symb_idx_scs_120_120_mux3[ssb_idx&3]; break; default: - AssertFatal(1==0, "Invalid SSB and coreset multiplexing pattern %d\n", pdcch_params->mux_pattern); + AssertFatal(1==0, "Invalid SSB and coreset multiplexing pattern %d\n", pdcch_pdu->mux_pattern); } - pdcch_params->config_type = NFAPI_NR_CSET_CONFIG_MIB_SIB1; - pdcch_params->cr_mapping_type = NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED; - pdcch_params->precoder_granularity = NFAPI_NR_CSET_SAME_AS_REG_BUNDLE; - pdcch_params->reg_bundle_size = 6; - pdcch_params->interleaver_size = 2; + pdcch_pdu->config_type = NFAPI_NR_CSET_CONFIG_MIB_SIB1; + pdcch_pdu->cr_mapping_type = NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED; + pdcch_pdu->precoder_granularity = NFAPI_NR_CSET_SAME_AS_REG_BUNDLE; + pdcch_pdu->reg_bundle_size = 6; + pdcch_pdu->interleaver_size = 2; // set initial banwidth part to full bandwidth - pdcch_params->n_RB_BWP = N_RB; + pdcch_pdu->n_RB_BWP = N_RB; + */ } -void nr_configure_pdcch(nfapi_nr_dl_config_pdcch_pdu_rel15_t* pdcch_pdu, +void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, int ss_type, NR_ServingCellConfigCommon_t *scc, NR_BWP_Downlink_t *bwp) { @@ -487,7 +490,7 @@ void nr_configure_pdcch(nfapi_nr_dl_config_pdcch_pdu_rel15_t* pdcch_pdu, -void fill_dci_pdu_rel15(nfapi_nr_dl_config_pdcch_pdu_rel15_t *pdcch_pdu_rel15, +void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types @@ -501,8 +504,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_config_pdcch_pdu_rel15_t *pdcch_pdu_rel15, uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->Payload[d]; AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported"); /* - n_shift = (dci_alloc->pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)? - cfg->sch_config.physical_cell_id.value : dci_alloc->pdcch_params.shift_index; + n_shift = (dci_alloc->pdcch_pdu.config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)? + cfg->sch_config.physical_cell_id.value : dci_alloc->pdcch_pdu.shift_index; nr_fill_cce_list(dci_alloc, n_shift, cand_idx); */ int dci_size = pdcch_pdu_rel15->PayloadSizeBits[d]; diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index 907de53487..c5cf6eab79 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -66,21 +66,20 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP, sub_frame_t subframeP); int configure_fapi_dl_Tx(int Mod_id, - nfapi_nr_dl_config_request_body_t *dl_req, - nfapi_tx_request_pdu_t *TX_req, - int16_t pdu_index); + nfapi_nr_dl_tti_request_body_t *dl_req, + nfapi_nr_pdu_t *TX_req); void nr_schedule_uss_dlsch_phytest(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, - nfapi_nr_dl_config_pdsch_pdu_rel15_t *pdsch_config); + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_config); void nr_schedule_uss_ulsch_phytest(nfapi_nr_ul_tti_request_t *UL_tti_req, frame_t frameP, sub_frame_t slotP); -void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params, +void nr_configure_css_dci_initial(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, nr_scs_e scs_common, nr_scs_e pdcch_scs, nr_frequency_range_e freq_range, @@ -98,11 +97,11 @@ int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space, uint16_t slot, nfapi_nr_config_request_t cfg); */ -void nr_configure_pdcch(nfapi_nr_dl_config_pdcch_pdu_rel15_t* pdcch_pdu, +void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, int ss_type, NR_ServingCellConfigCommon_t *scc, NR_BWP_Downlink_t *bwp); -void fill_dci_pdu_rel15(nfapi_nr_dl_config_pdcch_pdu_rel15_t *pdcch_pdu_rel15, +void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types @@ -124,7 +123,7 @@ uint64_t from_nrarfcn(int nr_bandP, uint32_t dl_nrarfcn); uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint32_t bw); -void nr_get_tbs_dl(nfapi_nr_dl_config_pdsch_pdu *pdsch_pdu, +void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, int x_overhead); /** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */ uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx); diff --git a/openair2/LAYER2/NR_MAC_gNB/main.c b/openair2/LAYER2/NR_MAC_gNB/main.c index a34528afd1..1c2cf606a9 100644 --- a/openair2/LAYER2/NR_MAC_gNB/main.c +++ b/openair2/LAYER2/NR_MAC_gNB/main.c @@ -74,16 +74,6 @@ void mac_top_init_gNB(void) bzero(RC.nrmac[i], sizeof(gNB_MAC_INST)); RC.nrmac[i]->Mod_id = i; - - - for (j = 0; j < MAX_NUM_CCs; j++) { - RC.nrmac[i]->DL_req[j].dl_config_request_body.dl_config_pdu_list = RC.nrmac[i]->dl_config_pdu_list[j]; - RC.nrmac[i]->HI_DCI0_req[j].hi_dci0_request_body.hi_dci0_pdu_list = RC.nrmac[i]->hi_dci0_pdu_list[j]; - RC.nrmac[i]->TX_req[j].tx_request_body.tx_pdu_list = RC.nrmac[i]->tx_request_pdu[j]; - RC.nrmac[i]->ul_handle = 0; - - - } }//END for (i = 0; i < RC.nb_nr_macrlc_inst; i++) AssertFatal(rlc_module_init() == 0,"Could not initialize RLC layer\n"); diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.c b/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.c index 8e82631400..6b8abc7023 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.c +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.c @@ -182,12 +182,12 @@ int32_t get_nr_uldl_offset(int nr_bandP) } -void nr_get_tbs_dl(nfapi_nr_dl_config_pdsch_pdu *pdsch_pdu, +void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, int x_overhead) { LOG_D(MAC, "TBS calculation\n"); - nfapi_nr_dl_config_pdsch_pdu_rel15_t *pdsch_rel15 = &pdsch_pdu->pdsch_pdu_rel15; + nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_rel15 = &pdsch_pdu->pdsch_pdu_rel15; uint16_t N_PRB_oh = x_overhead; uint8_t N_PRB_DMRS = (pdsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1)?6:4; //This only works for antenna port 1000 uint8_t N_sh_symb = pdsch_rel15->NrOfSymbols; diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index e4f1cf07a3..dc3255d8aa 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -141,19 +141,13 @@ typedef struct gNB_MAC_INST_s { /// NFAPI Config Request Structure nfapi_nr_config_request_t config[NFAPI_CC_MAX]; /// NFAPI DL Config Request Structure - nfapi_nr_dl_config_request_t DL_req[NFAPI_CC_MAX]; + nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX]; /// NFAPI UL TTI Request Structure (this is from the new SCF specs) nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX]; - /// Preallocated DL pdu list - nfapi_nr_dl_config_request_pdu_t dl_config_pdu_list[NFAPI_CC_MAX][MAX_NUM_DL_PDU]; - /// Preallocated HI_DCI0 pdu list - nfapi_hi_dci0_request_pdu_t hi_dci0_pdu_list[NFAPI_CC_MAX][MAX_NUM_HI_DCI0_PDU]; /// NFAPI HI/DCI0 Config Request Structure - nfapi_hi_dci0_request_t HI_DCI0_req[NFAPI_CC_MAX]; - /// Prealocated TX pdu list - nfapi_tx_request_pdu_t tx_request_pdu[NFAPI_CC_MAX][MAX_NUM_TX_REQUEST_PDU]; + nfapi_nr_ul_dci_request_t ul_dci_req[NFAPI_CC_MAX]; /// NFAPI DL PDU structure - nfapi_tx_request_t TX_req[NFAPI_CC_MAX]; + nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX]; NR_UE_list_t UE_list; /// UL handle diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c index 7cd13a381e..c2f18eb57d 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c @@ -273,7 +273,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { handle_nr_cqi(UL_info); handle_nr_harq(UL_info); // clear HI prior to handling ULSCH - mac->HI_DCI0_req[CC_id].hi_dci0_request_body.number_of_hi = 0; + mac->ul_dci_req[CC_id].numPdus = 0; handle_nr_ulsch(UL_info); if (nfapi_mode != 1) { @@ -297,7 +297,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { sched_info->frame = (UL_info->frame + ((UL_info->slot>(spf-1-sf_ahead)) ? 1 : 0)) % 1024; sched_info->slot = (UL_info->slot+sf_ahead)%spf; sched_info->DL_req = &mac->DL_req[CC_id]; - sched_info->HI_DCI0_req = &mac->HI_DCI0_req[CC_id]; + sched_info->UL_dci_req = &mac->ul_dci_req[CC_id]; if ((mac->common_channels[CC_id].tdd_Config==NULL) || (is_nr_UL_slot(&mac->common_channels[CC_id],(sched_info->slot+sf_ahead)%spf)>0)) @@ -318,7 +318,10 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) { ifi->NR_Schedule_response(sched_info); } - LOG_D(PHY,"NR_Schedule_response: SFN_SF:%d%d dl_pdus:%d\n",sched_info->frame,sched_info->slot,sched_info->DL_req->dl_config_request_body.number_pdu); + LOG_D(PHY,"NR_Schedule_response: SFN_SF:%d%d dl_pdus:%d\n", + sched_info->frame, + sched_info->slot, + sched_info->DL_req->dl_tti_request_body.nPDUs); } } } diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.h b/openair2/NR_PHY_INTERFACE/NR_IF_Module.h index 898197cc30..182a858961 100644 --- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.h +++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.h @@ -100,13 +100,13 @@ typedef struct { /// slot slot_t slot; /// nFAPI DL Config Request - nfapi_nr_dl_config_request_t *DL_req; + nfapi_nr_dl_tti_request_t *DL_req; /// nFAPI UL Config Request nfapi_nr_ul_tti_request_t *UL_tti_req; - /// nFAPI HI_DCI Request - nfapi_hi_dci0_request_t *HI_DCI0_req; + /// nFAPI UL_DCI Request + nfapi_nr_ul_dci_request_t *UL_dci_req; /// Pointers to DL SDUs - nfapi_tx_request_t *TX_req; + nfapi_nr_tx_data_request_t *TX_req; } NR_Sched_Rsp_t; typedef struct {