adding option for CSI slot
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@@ -58,10 +58,15 @@ const int get_dl_tda(const gNB_MAC_INST *nrmac, const NR_ServingCellConfigCommon
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const NR_TDD_UL_DL_Pattern_t *tdd = scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
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const NR_TDD_UL_DL_Pattern_t *tdd = scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
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AssertFatal(tdd || nrmac->common_channels->frame_type == FDD, "Dynamic TDD not handled yet\n");
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AssertFatal(tdd || nrmac->common_channels->frame_type == FDD, "Dynamic TDD not handled yet\n");
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// Use special TDA in case of CSI-RS
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const NR_UE_info_t *UE_info = &nrmac->UE_info;
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if(UE_info->sched_csirs)
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return 1;
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if (tdd && tdd->nrofDownlinkSymbols > 1) { // if there is a mixed slot where we can transmit DL
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if (tdd && tdd->nrofDownlinkSymbols > 1) { // if there is a mixed slot where we can transmit DL
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const int nr_slots_period = tdd->nrofDownlinkSlots + tdd->nrofUplinkSlots + 1;
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const int nr_slots_period = tdd->nrofDownlinkSlots + tdd->nrofUplinkSlots + 1;
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if ((slot%nr_slots_period) == tdd->nrofDownlinkSlots)
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if ((slot%nr_slots_period) == tdd->nrofDownlinkSlots)
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return 1;
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return 2;
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}
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}
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return 0; // if FDD or not mixed slot in TDD, for now use default TDA (TODO handle CSI-RS slots)
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return 0; // if FDD or not mixed slot in TDD, for now use default TDA (TODO handle CSI-RS slots)
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}
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}
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@@ -2659,6 +2659,8 @@ void nr_csirs_scheduling(int Mod_idP,
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gNB_MAC_INST *gNB_mac = RC.nrmac[Mod_idP];
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gNB_MAC_INST *gNB_mac = RC.nrmac[Mod_idP];
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uint16_t *vrb_map = gNB_mac->common_channels[CC_id].vrb_map;
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uint16_t *vrb_map = gNB_mac->common_channels[CC_id].vrb_map;
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UE_info->sched_csirs = false;
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for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
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for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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@@ -2691,6 +2693,7 @@ void nr_csirs_scheduling(int Mod_idP,
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if((frame*n_slots_frame+slot-offset)%period == 0) {
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if((frame*n_slots_frame+slot-offset)%period == 0) {
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LOG_D(NR_MAC,"Scheduling CSI-RS in frame %d slot %d\n",frame,slot);
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LOG_D(NR_MAC,"Scheduling CSI-RS in frame %d slot %d\n",frame,slot);
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UE_info->sched_csirs = true;
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_csirs_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_csirs_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
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memset((void*)dl_tti_csirs_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
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memset((void*)dl_tti_csirs_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
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@@ -710,7 +710,8 @@ typedef struct {
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// UE selected beam index
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// UE selected beam index
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uint8_t UE_beam_index[MAX_MOBILES_PER_GNB];
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uint8_t UE_beam_index[MAX_MOBILES_PER_GNB];
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bool Msg4_ACKed[MAX_MOBILES_PER_GNB];
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bool Msg4_ACKed[MAX_MOBILES_PER_GNB];
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/// Sched CSI-RS: scheduling decisions
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bool sched_csirs;
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} NR_UE_info_t;
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} NR_UE_info_t;
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typedef void (*nr_pp_impl_dl)(module_id_t mod_id,
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typedef void (*nr_pp_impl_dl)(module_id_t mod_id,
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@@ -329,18 +329,20 @@ void nr_rrc_config_dl_tda(NR_ServingCellConfigCommon_t *scc,
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timedomainresourceallocation->mappingType = NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA;
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timedomainresourceallocation->mappingType = NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA;
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timedomainresourceallocation->startSymbolAndLength = get_SLIV(len_coreset,14-len_coreset); // basic slot configuration starting in symbol 1 til the end of the slot
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timedomainresourceallocation->startSymbolAndLength = get_SLIV(len_coreset,14-len_coreset); // basic slot configuration starting in symbol 1 til the end of the slot
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ASN_SEQUENCE_ADD(&pdsch_TimeDomainAllocationList->list, timedomainresourceallocation);
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ASN_SEQUENCE_ADD(&pdsch_TimeDomainAllocationList->list, timedomainresourceallocation);
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// setting TDA for CSI-RS symbol with index 1
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struct NR_PDSCH_TimeDomainResourceAllocation *timedomainresourceallocation1 = CALLOC(1,sizeof(NR_PDSCH_TimeDomainResourceAllocation_t));
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timedomainresourceallocation1->mappingType = NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA;
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timedomainresourceallocation1->startSymbolAndLength = get_SLIV(len_coreset,14-len_coreset-1); // 1 symbol CSI-RS
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ASN_SEQUENCE_ADD(&pdsch_TimeDomainAllocationList->list, timedomainresourceallocation1);
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if(frame_type==TDD) {
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if(frame_type==TDD) {
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if(scc->tdd_UL_DL_ConfigurationCommon) {
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if(scc->tdd_UL_DL_ConfigurationCommon) {
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int dl_symb = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols;
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int dl_symb = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols;
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if(dl_symb > 1) {
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if(dl_symb > 1) {
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// mixed slot TDA with TDA index 1
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// mixed slot TDA with TDA index 2
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timedomainresourceallocation = CALLOC(1,sizeof(NR_PDSCH_TimeDomainResourceAllocation_t));
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struct NR_PDSCH_TimeDomainResourceAllocation *timedomainresourceallocation2 = CALLOC(1,sizeof(NR_PDSCH_TimeDomainResourceAllocation_t));
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// k0: Slot offset between DCI and its scheduled PDSCH (see TS 38.214 clause 5.1.2.1) When the field is absent the UE applies the value 0.
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timedomainresourceallocation2->mappingType = NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA;
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//timedomainresourceallocation->k0 = calloc(1,sizeof(*timedomainresourceallocation->k0));
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timedomainresourceallocation2->startSymbolAndLength = get_SLIV(len_coreset,dl_symb-len_coreset); // mixed slot configuration starting in symbol 1 til the end of the dl allocation
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//*timedomainresourceallocation->k0 = 0;
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ASN_SEQUENCE_ADD(&pdsch_TimeDomainAllocationList->list, timedomainresourceallocation2);
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timedomainresourceallocation->mappingType = NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA;
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timedomainresourceallocation->startSymbolAndLength = get_SLIV(len_coreset,dl_symb-len_coreset); // mixed slot configuration starting in symbol 1 til the end of the dl allocation
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ASN_SEQUENCE_ADD(&pdsch_TimeDomainAllocationList->list, timedomainresourceallocation);
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}
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}
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}
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}
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}
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}
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