maki/openairinterface5g
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

* add RRH gateway module, IQ transports, and its gtkwave template (experimental)

Browse Source 
* update ethernet library and common lib 
* update runtime values of the lte-softmodem tx and rx threads based on an empirical model


git-svn-id: http://svn.eurecom.fr/openair4G/trunk@7709 818b1a75-f10b-46b9-bf7c-635c3b92a50f
This commit is contained in:
navid
2015-07-16 15:31:04 +00:00
parent 4ef9500af4
commit ff2f80989b
28 changed files with 2968 additions and 339 deletions
Download Patch File Download Diff File Expand all files Collapse all files
targets/RT/USER/rt_wrapper.c
+166 -3
View File
@@ -28,17 +28,51 @@
*******************************************************************************/
/*! \file rt_wrapper.h
* \brief provides a wrapper for the timing function for real-time opeartions depending on weather RTAI is used or not
* \author F. Kaltenberger
* \brief provides a wrapper for the timing function, runtime calculations for real-time opeartions depending on weather RTAI or LOWLATENCY kernels are used or not
* \author F. Kaltenberger and Navid Nikaein
* \date 2013
* \version 0.1
* \company Eurecom
* \email: florian.kaltenberger@eurecom.fr
* \email: florian.kaltenberger@eurecom.fr, navid.nikaein@eurecom.fr
* \note
* \warning
*/
#include "rt_wrapper.h"
static int latency_target_fd = -1;
static int32_t latency_target_value = 0;
/* Latency trick - taken from cyclictest.c
* if the file /dev/cpu_dma_latency exists,
* open it and write a zero into it. This will tell
* the power management system not to transition to
* a high cstate (in fact, the system acts like idle=poll)
* When the fd to /dev/cpu_dma_latency is closed, the behavior
* goes back to the system default.
*
* Documentation/power/pm_qos_interface.txt
*/
void set_latency_target(void) {
struct stat s;
int ret;
if (stat("/dev/cpu_dma_latency", &s) == 0) {
latency_target_fd = open("/dev/cpu_dma_latency", O_RDWR);
if (latency_target_fd == -1)
return;
ret = write(latency_target_fd, &latency_target_value, 4);
if (ret == 0) {
printf("# error setting cpu_dma_latency to %d!: %s\n", latency_target_value, strerror(errno));
close(latency_target_fd);
return;
}
printf("# /dev/cpu_dma_latency set to %dus\n", latency_target_value);
}
}
#ifndef RTAI
@@ -89,6 +123,135 @@ void check_clock(void)
}
}
uint16_t cell_processing_dl[6]={10,15,24,42,80,112};
uint16_t platform_processing_dl=20; // upperbound for GPP, LXC, DOCKER and KVM
uint16_t user_processing_dl_a[6]={2,4,5,7,10,12};
uint16_t user_processing_dl_b[6]={10, 15, 25, 70, 110, 150};
uint16_t user_processing_dl_err[6]={20, 40, 60, 90, 120, 160};
uint16_t protocol_processing_dl[6]={150, 250, 350, 450, 650, 800}; // assumption: max MCS 27 --> gives an upper bound for the transport block size : to be measured
uint16_t cell_processing_ul[6]={10,15,24,42,80,112};
uint16_t platform_processing_ul=30; // upperbound for GPP, LXC, DOCKER and KVM
uint16_t user_processing_ul_a[6]={5, 9, 12, 24, 33, 42};
uint16_t user_processing_ul_b[6]={20, 30, 40, 76, 140, 200};
uint16_t user_processing_ul_err[6]={15, 25, 32, 60, 80, 95};
uint16_t protocol_processing_ul[6]={100, 200, 300, 400, 550, 700}; // assumption: max MCS 16 --> gives an upper bound for the transport block size
int fill_modeled_runtime_table(uint16_t runtime_phy_rx[29][6],
uint16_t runtime_phy_tx[29][6]){
//double cpu_freq;
//cpu_freq = get_cpu_freq_GHz();
// target_dl_mcs
// target_ul_mcs
// frame_parms[0]->N_RB_DL
int i,j;
memset(runtime_phy_rx,0,sizeof(uint16_t)*29*6);
memset(runtime_phy_tx,0,sizeof(uint16_t)*29*6);
/* only the BBU/PHY procesing time */
for (i=0;i<29;i++){
for (j=0;j<6;j++){
runtime_phy_rx[i][j] = cell_processing_ul[j] + platform_processing_ul + user_processing_ul_err[j] + user_processing_ul_a[j]*i+ user_processing_ul_b[j];
runtime_phy_tx[i][j] = cell_processing_dl[j] + platform_processing_dl + user_processing_dl_err[j] + user_processing_dl_a[j]*i+ user_processing_dl_b[j];
}
}
}
// int runtime_upper_layers[6]; // values for different RBs
// int runtime_phy_rx[29][6]; // SISO [MCS 0-28][RBs 0-5 : 6, 15, 25, 50, 75, 100]
// int runtime_phy_tx[29][6]; // SISO [MCS 0-28][RBs 0-5 : 6, 15, 25, 50, 75, 100]
// target_dl_mcs
// target_ul_mcs
// frame_parms[0]->N_RB_DL
//runtime_upper_layers[6]; // values for different RBs
// int runtime_phy_rx[29][6]; // SISO [MCS 0-28][RBs 0-5 : 6, 15, 25, 50, 75, 100]
// int runtime_phy_tx[29][6]
double get_runtime_tx(int tx_subframe, uint16_t runtime_phy_tx[29][6], uint32_t mcs, int N_RB_DL,double cpuf,int nb_tx_antenna){
int i;
double runtime;
//printf("cpuf =%lf \n",cpuf);
switch(N_RB_DL){
case 6:
i = 0;
break;
case 15:
i = 1;
break;
case 25:
i = 2;
break;
case 50:
i = 3;
break;
case 75:
i = 4;
break;
case 100:
i = 5;
break;
default:
i = 3;
break;
}
runtime = ( (3.2/cpuf)*(double)runtime_phy_tx[mcs][i] + (3.2/cpuf)*(double)protocol_processing_dl[i])/1000 ;
printf("Setting tx %d runtime value (ms) = %lf\n",tx_subframe,runtime);
return runtime;
}
double get_runtime_rx(int rx_subframe, uint16_t runtime_phy_rx[29][6], uint32_t mcs, int N_RB_DL,double cpuf,int nb_rx_antenna){
int i;
double runtime;
//printf("N_RB_DL=%d cpuf =%lf \n",N_RB_DL, cpuf);
switch(N_RB_DL){
case 6:
i = 0;
break;
case 15:
i = 1;
break;
case 25:
i = 2;
break;
case 50:
i = 3;
break;
case 75:
i = 4;
break;
case 100:
i = 5;
break;
default:
i = 3;
break;
}
runtime = ((3.2/cpuf)*(double)runtime_phy_rx[mcs][i] + (3.2/cpuf)*(double)protocol_processing_ul[i])/1000 ;
printf("Setting rx %d runtime value (ms) = %lf \n",rx_subframe, runtime);
return runtime;
}
#ifdef LOWLATENCY
int sched_setattr(pid_t pid, const struct sched_attr *attr, unsigned int flags)
{
return syscall(__NR_sched_setattr, pid, attr, flags);
}
int sched_getattr(pid_t pid,struct sched_attr *attr,unsigned int size, unsigned int flags)
{
return syscall(__NR_sched_getattr, pid, attr, size, flags);
}
#endif
#else
int rt_sleep_ns(RTIME x)