Introduce SRS physical simulator and improvements
This MR consists of two parts:
- Introduces SRS physical simulator to test different configurations of
SRS
- Improvements in the SRS channel estimation (Addressing the comments
from old, unfinished MR !2875)
- rewrite nr_srs_channel_estimation() to loop over rx antennas and
antenna ports to be able to parallelize
- Improvements in timing_advance_offset and timing_advance_offset_nsec
computation
- Introduce SRS multi-symbol channel estimation
- The channel impulse response is estimated from the averaged
channel frequency response over multiple symbols
- The channel frequency estimates are left as they are to be able to
estimate doppler in the future
- Simplify SRS channel estimation to handle memory alignment in the
case of different SRS configurations (eg: comboffset)
To use multiple symbols when running gNB, the following parameters needs
to be edited in the function get_srs_resource()
- srs_res->resourceMapping.startPosition with a range from {0,1,..,5}
corresponds to the start symbol {13, 12, .. 8} with in a slot
- srs_res->resourceMapping.nrofSymbols indicates the number of symbols
{n1, n2, and n4}
Make sure the that start symbol + number of symbols is < 14
The timing results for SRS in develop and srs_phy_simulator are as follows:
Command used: sudo ./nr_ulsim -n1000 -s50 -S50 -R273 -W2 -y2 -z2 -E 1 -P
develop
|__ RX SRS time 124.94 us (1000 trials) (124.94 total [ms])
|__ Generate SRS sequence time 0.05 us (1000 trials) ( 0.05 total [ms])
|__ Get SRS signal time 19.41 us (1000 trials) ( 19.41 total [ms])
|__ SRS channel estimation time 89.11 us (1000 trials) ( 89.11 total [ms])
|__ SRS timing advance estimation time 13.10 us (1000 trials) ( 13.10 total [ms])
|__ SRS report TLV build time 2.80 us (1000 trials) ( 2.80 total [ms])
|__ SRS beam report build time 0.00 us ( 0 trials)
|__ SRS IQ matrix build time 2.73 us (1000 trials)
srs_phy_simulator
|__ RX SRS time 211.93 us (1000 trials) (211.93 total [ms])
|__ Generate SRS sequence time 0.04 us (1000 trials) ( 0.04 total [ms])
|__ Get SRS signal time 19.55 us (1000 trials) ( 19.55 total [ms])
|__ SRS channel estimation time 152.05 us (1000 trials) (152.05 total [ms])
|__ SRS timing advance estimation time 36.67 us (1000 trials) ( 36.67 total [ms])
|__ SRS report TLV build time 2.96 us (1000 trials) ( 2.96 total [ms])
|__ SRS beam report build time 0.00 us ( 0 trials)
|__ SRS IQ matrix build time 2.88 us (1000 trials)
Note that in srs_phy_simulator, to compute timing offset ns, an
oversampling factor of 2 is performed. Also, for peak detection, we
average the channel estimates for every port.
Remove schedule response and update L1 threading documentation
This merge requests removes the somewhat superfluous "schedule response"
mechanism. "schedule response" was run after running the scheduler
itself and copied various FAPI messages into a global msgDataTx
structure from which the various TX/RX jobs were triggered. It is not
necessary, though, given that the scheduler is run inside the tx_func()
(running the TX jobs of the L1), and so the scheduler output FAPI
messages can directly be read into a variable of the existing
NR_Sched_Rsp_t type. This allows to delete a couple of hundred lines of
code (while retaining functionality), and simplifies the msgDataTx type
(which is still there to trigger TX job (including the scheduler) from
the ru thread).
In short, prior, there was this call chain:
- tx_func() calls run_scheduler_monolithic() (through fptr
NR_slot_indication())
- get some memory through allocate_sched_response() which has enough
space for NR_Sched_Rsp_t type variable
- call the scheduler and fill the variable
- call nr_schedule_response() (through fptr NR_schedule_response())
which copies into L1: to msgDataTx for TX, to separate structures
for RX
this is changed to
- tx_func() runs one message at a time, hence we can use memory in the
data segment for NR_Sched_Rsp_t. It calls run_scheduler_monolithic()
through the fptr
- pointers into NR_Sched_Rsp_t are passed to the scheduler, which
fills as before
- we return, memory is in its right place and does not need an extra
copy.
Additionally, this merge request updates documentation on threading and
cleans up some unused code along the way.
- Add to common/utils/nr/nr_common remove from NR_MAC_UE/nr_ue_procedures.c
- Adopt in asn1_msg.c for MeasurementReport: this solves the following assert:
Assertion (enc_rval.encoded > 0) failed!
In do_nrMeasurementReport_SA() /oai-ran/openair2/RRC/NR/MESSAGES/asn1_msg.c:898
ASN1 message encoding failed (MeasResultServMOList, 18446744073709551615)!
Motivation: unify RSRP-to-index mapping across layers and fix NR RRC MeasurementReport
encoding failures due to out-of-range values by reusing the validated mapping.
Note NR_RSRP-Range.c constraint:
{ APC_CONSTRAINED, 7, 7, 0, 127 } /* (0..127) */
NR UE: consider the ratio of PUSCH EPRE to DMRS EPRE when calculating PUSCH
DMRS power scaling
When calculating DMRS scaling ratio, we should consider PUSCH EPRE to DMRS
EPRE according to TS 38.214 Table 6.2.2-1.
Close#929
Long PRACH extends beyond a slot. Changes necessary to mark future slots
that may contain prach in ru, phy and mac functions.
In RU, the PRACH IDFT is done only after receiving last slot and marks
for L1 to start processing. The L1 processes at the last prach slot and
reports to MAC with the first slot index.
In MAC scheduler, the VRB for future slots are also marked as used.
PRACH scheduler is called in advance one frame minus num prach slots.
Changes to support multiple TDD patterns
- Updated the configuration changes for 2 Patterns
- Update the TDD table configuration for NFAPI
- Added the tdd bitmap for the period
- Adapted the bitmap for UL/DL for the multi TDD pattern
- Updated the RACH procedure for multi TDD pattern
- Updated DL and UL scheduler for multi TDD pattern
* the function is returning the index of the first full UL slot in tdd_slot_bitmap
or the first UL slot (including mixed) if the "mixed" flag is provided
* set_tdd_bmap_period, config_tdd_patterns: to configure TDD period, including bitmap, in the frame structure
* get_tdd_periodicity: to retrieve the periodicity in milliseconds for the given TDD pattern
* get_tdd_period_idx: to get the TDD period index based on pattern periodicities
* get_ul_slots_per_period: get the number of UL slots (including mixed with UL symbols) in period
* get_full_ul_slots_per_period: get the number of full UL slots in period
* get_dl_slots_per_period: get the number of DL slots (including mixed with DL symbols) in period
* get_full_dl_slots_per_period: get the number of full DL slots in period
Co-authored-by: vijay chadachan <vijay.chadachan@firecell.io>
Pass consistently the NR_timer_t object through a pointer. Since we have
to modify all occurrences of is_nr_timer_active(), we use that occasion
and rename that function to nr_timer_is_active() to make it consistent
with all other functions, starting with nr_timer.
A new phy scope based on ImGui and ImPlot. This scope uses a different concurrency model than previous
scopes.
The PHY thread writing the data first checks if the data is ready to be written. If its not, nothing is copied.
The GUI thread reads data if available and marks it ready to write. This makes sure that the PHY threads are not
busy copying data that would never be displayed.
Some of the scopes also have a freeze functionality that further limit the amount of data that needs to be copied
from PHY threads. If a scope is "frozen" it still allows the user to explore the data using plots zoom/pan functions
but doesn't cause PHY threads to perform extra writes on the displayed data.
A compile option was added to enable/disable the scope. Use cmake -DENABLE_IMSCOPE=ON to enable the scope.
Update CXX standard to 17; it is required by some libraries (e.g., dear imgui). The oldest gcc version in
use by a distribution supported is Ubuntu 20, which has gcc 9.4 with c++17 support.
- MAX HARQ PROCESSES set to 32
- for PDSCH - default setting in OAI is 16, according to 3GPP rel17 38.331 these are the possible configs
- if no IES are defined then 8
- if nrofHARQ-ProcessesForPDSCH is defined then these values- {n2, n4, n6, n10, n12, n16}
- if nrofHARQ-ProcessesForPDSCH-v1700 is defined then 32
- for harq bits in DCI
- DCI 1_0 - 4 bits spec 38.212, section 7.3.1.2.1
- DCI 1_1 - 4/5 bits according to IE harq-ProcessNumberSizeDCI-1-1, spec 38.212, section 7.3.1.2.2
- for PUSCH - default setting in OAI is 16, according to 3GPP rel17 38.331 these are possible configs
- if no IES are defined then 16
- if nrofHARQ-ProcessesForPUSCH-v1700 is defined then 32
- for harq bits in DCI
- DCI 0_0 - 4 bits spec 38.212, section 7.3.1.1.1
- DCI 0_1 - 4/5 bits according to IE harq-ProcessNumberSizeDCI-0-1, spec 38.212, section 7.3.1.1.2
- FOR HARQ32 , DCI 1_1, DCI 0_1 should be configured in UE dedicated search space. In OAI it is set.
This assert and assumption is incorrect, according to 38.101-1 UE channel is defined only by the BWP size
and BWP size can be any value supported by the RRC parameters defining the BWP.
To determine the UE channel the smallest bandwidth supporting the BWP is selected. This is an assumption based
on references in the same document to UE channel bandwidth being equal to one of the values in set
{5, 10, 15, 20, 25, 30, 35, 40, 50, 60, 70, 80, 90, 100}.
Also:
- calculated P_CMIN during BWP setup since the parameter doesn't depend on DCI.
- initiialize uniqCfg structure in test_nr_ue_power_procedures main function which enables LOG prints during tests
Robert Schmidt