newly-generated files for innermost part of the parity bit
generation which, for AVX512, uses the mm512_permutex2var_epi8
instruction and for 128-bit (aarch64) the mm_alignr_epi8 (vextq_s8) in
the computation corresponding to each non-zero bit of the H matrix.
It is generated with ldpctest -n0 -g1. the changes for this are in a
future MR. I did these changes to compare with the GPU version
(ldpc_encoder_cuda), so that the CPU version is as fast as possible. The
generator will come when we merge the GPU encoder/decoder which also has
a generator for the CUDA version. it was difficult to extract the
changes in ldpctest/ldpc_encoder.c so I just took the generated file.
This allows for removing a very large memcpy and reduces the memory
demand for the parity matrix computation. For the moment this is limited
to largest case in BG1, namely Zc=384. This is the only format used when
the number of segments after codeblock segmentation is large (>8). This
improves the timing required for ldpc parity bits generation by more
than a factor 2 with AVX512. This significantly reduces the total time
to generate the DLSCH/PDSCH
1. nrLDPC_coding_segment_encoding: Clarifying encoder parameters
The way the encoder implementation params was used could be made clearer:
* `macro_num` was always used in order to calculate segment indexes.
It is clearer to pass directly the first segment index.
* The initialisation of a common implementation parameters structure can be made clearer.
2. nrLDPC_coding_segment_encoder: Remove multi segment dimension in encoder output
The output of `LDPCencoder` was a 2D unsigned char array.
But all the segments were actually packed in the first segment, 8 bits of different segments per byte of the first segment.
So the first dimension was useless. This commit removes this dimension.
3. nrLDPC_coding_segment_encoder: Rename `nrLDPC_prepare_TB_encoding` into `nrLDPC_launch_TB_encoding`
4. nrLDPC_coding_segment_encoder: Remove the useless second rate matching for E2, one rate matching with max(E, E2) does the job.
5. nr_interleaving_ldpc: cleanup
Rewrite code to use different SIMD sizes in a linear fashion.
This means cascading preprocessor directives are used to start from a high SIMD size an decrease it progressively.
6. ldpc_encoder_optim8segmulti: linear usage of SIMD
Use cascading preprocessor directives to include different SIMD sizes and types depending on which are available on the system.
The different loops use a common index that is progressively incremented.
Also add AVX512 version of bits distribution from 8 segments into one byte.
Co-authored-by: Laurent Thomas <laurent.thomas@open-cells.com>
1. 3GPP Rate-matching/interleaving on 8-segment blocks, deinterleaving at output of multi-segment processing.
2. Bit-packing done in nrLDPC_coding_segment_encoder.c now instead of nr_scrambling.
Interestingly, it improves performance significantly too.
Tested for AVX512 only for now.
Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators.
- Changes:
- use SIMDE consistently
- adaptations of LDPC decoder generator for ARMv8 performance
- SIMDe modifications of Intel CRC to allow for aarch64 build.
optimizations for 128-bit to improve performance of LDPC encode/decode
on aarch64 (Neoverse 1)
- added BG2 files for 128-bit ldpc encoder (aarch64)
- testing on Xeon
- testing on x86
- minor changes to build/run on x86
- change in crc.h after returning to aarch64
- removed some warning in ldpc decoder generator for x86_64
- char
- Delete irrelevant constants
- Correctly declare variables
- Define stdbool for all architectures
- Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE
- Remove commented code
- Fix CMakeLists.txt
- Include SIMDE avx2 functions in tools_defs.h
adding ldpctest encoder, decoder and ldpctest to CMakeLists.txt
activating the TCL LDPC decoder in the LDPC testbench but only works for largest blocksize 8448 for now.
Raymond Knopp