Most (but not all) physical simulators are defined under
openair1/SIMULATION/. Defining physical simulators below there seems to
be the more "obvious" directory anyway, as the physical simulators are
openair1/SIMULATION/tests
Phy(L1) Sim tests => PhySim (tests)
Ldpc encoder zc384 optimization
This is a modification for the ldpc encoder which improves performance for
high-throughput cases. It contains a newly-generated file for innermost part of
the parity bit generation which, for AVX512, uses the mm512_permutex2var_epi8
instruction and for 128-bit (aarch64) the mm_alignr_epi8 (vextq_s8) in the
computation corresponding to each non-zero bit of the H matrix. This allows for
removing a very large memcpy and reduces the memory demand for the parity matrix
computation. For the moment this is limited to largest case in BG1, namely
Zc=384. This is the only format used when the number of segments after codeblock
segmentation is large (>8). This improves the timing required for ldpc parity
bits generation by more than a factor 2 with AVX512. This significantly reduces
the total time to generate the DLSCH/PDSCH.
See the merge request description for numbers.
Speedup complex rotate for aarch64
This is a simple optimization for aarch64 for the "rotate_cpx_vector" used for
the phase_rotation in 5G NR. It provides a speedup of around 1.5 on high-end
aarch64 targets compared to the SIMDe translated version. It is implemented with
native NEON intrinsics and was largely inspired by suggestions from ChatGPT 5 :-)
newly-generated files for innermost part of the parity bit
generation which, for AVX512, uses the mm512_permutex2var_epi8
instruction and for 128-bit (aarch64) the mm_alignr_epi8 (vextq_s8) in
the computation corresponding to each non-zero bit of the H matrix.
It is generated with ldpctest -n0 -g1. the changes for this are in a
future MR. I did these changes to compare with the GPU version
(ldpc_encoder_cuda), so that the CPU version is as fast as possible. The
generator will come when we merge the GPU encoder/decoder which also has
a generator for the CUDA version. it was difficult to extract the
changes in ldpctest/ldpc_encoder.c so I just took the generated file.
This allows for removing a very large memcpy and reduces the memory
demand for the parity matrix computation. For the moment this is limited
to largest case in BG1, namely Zc=384. This is the only format used when
the number of segments after codeblock segmentation is large (>8). This
improves the timing required for ldpc parity bits generation by more
than a factor 2 with AVX512. This significantly reduces the total time
to generate the DLSCH/PDSCH
RFSim test for 10 UEs/process
This MR adds a testcase and changes required to run 10 UEs in a single
process with RFSim
- Added deregistration for all connected UEs
- Refactored MAC/RRC instance handling
- made map_current_symbol thread safe
- made opeanir0_cfg thread safe and local
- Added 10UE/process testcase
RF emulator and improvements of the timers
RF emulator:
Add an RF library emulating a real device without the need of a real
device. This is thought to enable using phy-test without requiring a
radio device or channel simulation. The library synchronizes on the
real time clock, drops TX and generate noise on RX. Noise generation
can be disabled and the noise level configured.
Timers improvements:
- Fix standard deviation for merged timers
- Add display of ULSCH decoding timers
- Add decoding timer in AAL
CI: speed up and simplify build, remove unnecessary Python code, remove --eNB* parameter list
This cleans up the CI framework for running end-to-end tests, and
improves the integration with OAI code. Specifically
- cleanup build_oai and helpers to output all text, which is captured
better by the CI
- build some images in the Cluster-Build in parallel to increase speed
- remove all --eNB{,1,2}{IPAddress,UserName,Password} variables. Those
were indexed through "instance" and "server ID" and are replaced with
the actual node name. I consider further cleanup to introduce a
"global" XML file node name so we don't need this in each step and
instead define this once.
- individual cleanup
Introduce support for Cat-B RU using Predefined-Beam BF with Aerial L1
This merge introduces the support for BeamID based Beamforming in OAI L2 using FAPI and leveraging Aerial L1. Support for OAI L1 is not in the scope of this MR.
Main changes:
- Introduced a third state for the analog_beamforming parameter.
0=disabled,1=analog_bf,2=oran_bf
- Correctly populated the FAPI BF PDUs (prg_size, num_prgs,
dig_bf_interfaces)
Cleanup documentation and interface of the LDPC segment coding libraries
Fix interface: The LDPC segment decoder interface had variables
'harq_pid', 'ulsch_id' and 'C' that are not useful to the segment
decoder. This MR removes these variables from the interface.
Fix documentation: libconfig log do not display anymore by default so we
may better not show them in the documentation to avoid any
misunderstanding.
Remove ldpc_cl library since the library does not work.
Workaround for handling 2 SS0 occasions per slot
Search Space 0 monitoring might depend on SSB. In !3332 this dependence
was removed by moving the configuration of SS0 earlier in a workaround
to avoid a segfault in handover. Now, a new workaround is needed to
handle 2 search space occasions per slot.
Variables 'harq_pid', 'ulsch_id' and 'C' of the segment decoder
interface were not used any more by the implementations and set to zero
by all the callers.
Then it is more relevant and compliant to remove them.
LDPC BBDEV/AAL rework
This branch aims to generalize the existing LDPC T2 implementation to support
other DPDK BBDEV accelerators, e.g., Intel ACC100/200.
Differences from the current T2 implementation include:
1. relax CMakeLists.txt checking for custom dpdk-t2 implementation,
technically, any DPDK BBDEV should work
2. BBDEV capability checks during init
3. llr_scaling to scale the input llr accordingly for better decoding
performance on the Intel ACC100/200
4. self-managed harq buffers for the ACC200, as internal harq memory is not
available
Tested BBDEV devices:
1. Intel ACC100
2. Intel ACC200/VRB1
Rename the library to reflect that it's more a generic AAL driver than
specifically for AAL. To this end, rename some documentation.
As of this commit, the options are still called nrLDPC_coding_t2. The
next commit will correct this.
Co-authored-by: Xin Zhe Khooi <khooixz@comp.nus.edu.sg>
simplify and make more local variables in nr_rx_pdcch() and fix small bugs...
simplify and make more local variables in nr_rx_pdcch() and fix small bugs
(size 9 RE instaed of 12 RE)
DC subcarrier has a significantly higher energy compared to other CSI IM
resource elements. This causes the average interference + noise
estimation to be higher than CSI-RS signal power making the CQI 0. With
a third-party gnb that schedules PDSCH based on CQI, the UE never
receives DL DCI once it starts sending CSI reports.
Robert Schmidt