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9a2e080f7775a099f0e8cbbd4cff1fa12b973d19
Commit Graph
725 Commits
Author SHA1 Message Date
Robert Schmidt 9a2e080f77 Apply clang-format 2024-04-13 08:54:15 +02:00
Raghavendra Dinavahi 94b23d1eb0 PSBCH RX TX and SLSS search procedures 
- RX/TX Phy processing accg to 38.211, 38.212 Rel16
	- PSBCH simulator used to validate TX/RX phy processing
	- PSBCH SLSS Search procedures
	- PSBCH SIM also tests SLSS SEARCH
 2024-04-12 16:07:00 +02:00
Laurent a0e7733035 Warning fix to RHEL generated message 
: error: '<unknown>' may be used uninitialized [-Werror=maybe-uninitialized]
  180 |   reverse_bits_u8(tmp, N/8, D2);
 2024-04-05 14:14:18 +02:00
mir b21552973c Remove old OAI implementation 2024-03-22 11:36:45 +01:00
mir a6ad11a20e Remove duplicated bit reverse table 2024-03-22 11:36:41 +01:00
mir 44e31bd845 Improved polar encoder 2024-03-22 11:35:34 +01:00
mir 573e7d3a4a Comments from MR 2024-03-07 11:00:57 +01:00
mir fc8d0c59c6 Scan build: Result of operation is garbage or undefined 2024-03-07 11:00:57 +01:00
Jaroslava Fiedlerova b166286a78 Use clang format 2024-01-25 17:21:32 +01:00
Jaroslava Fiedlerova bec8ebc311 Perform interleaving on the T2 card 
- UE and gNB encoder modification
- update T2 related doc
 2024-01-25 17:21:32 +01:00
Jaroslava Fiedlerova aa9cd6394a T2: Enable LDPC encoding offload for all MCS 
- Rate matching performed by card
- Due to rate matching on card, small TBs are encoded correctly, so the
  limitation of encoding small TBs in CPU can be lifted (all TBs encoded
  on T2), see a later commits
 2024-01-25 17:21:11 +01:00
Laurent THOMAS 18919576b7 rework PUCCH codec with c16_t type, rewrite large parts of functions to make readable code. Not fixed parts that are using SIMD. No change, the code is still same block by block (variable visibility narrowed, declaration can be shifted) 2024-01-04 10:21:15 +01:00
Robert Schmidt cbff849b82 Merge remote-tracking branch 'origin/t2-offload-mr2' into integration_2023_w51 2023-12-21 16:14:02 +01:00
Jaroslava Fiedlerova c66b09c8a3 T2: Fix buffer overflow and HARQ codeblock ID out of range 
- set size of buffers to max E
- change HARQ codeblock offset calculation for T2
- add constant for maximum code block size - max E
 2023-12-21 11:19:13 +01:00
Robert Schmidt 6c2194038a Merge remote-tracking branch 'origin/enhance-polar-perf' into integration_2023_w49 2023-12-11 14:56:15 +01:00
Laurent THOMAS 175e835d05 update the polar codec function that creates the internal LUTs 
to use faster code
- replaced hundreds mallocs by either local arrays or by the OAI multi-dimensionalarray (G_N_tab array)
- made in SIMD a one bit per byte packing function to packed (ordinary) bits in bytes
 2023-12-08 17:11:16 +01:00
Jaroslava Fiedlerova 7c5b945766 Set RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE based on harq_to_be_cleared value 2023-11-28 09:37:37 +01:00
laurent 7bb529dcdf fix redundant member in ldpc decoder struct 2023-11-28 09:37:37 +01:00
laurent 10d7fe9cc6 fix regressions in cuda ldpc 2023-11-28 09:37:37 +01:00
Jaroslava Fiedlerova cf97acb8c7 Add T2 LDPC encoding/decoding offload 2023-11-28 09:37:37 +01:00
Laurent THOMAS 99ca87a1c1 Refactor LDPC API to make common API with various implementations 2023-11-28 09:37:37 +01:00
Jaroslava Fiedlerova e945b260f8 Remove T1 decoding offload 2023-11-28 09:37:37 +01:00
Laurent THOMAS f50d5f5a9b make multiple config instead of one implicit global 2023-11-10 10:23:11 +01:00
Robert Schmidt 7420de8fc9 Merge remote-tracking branch 'origin/fix-doxygen' into integration_2023_w43 2023-10-30 10:23:45 +01:00
Robert Schmidt 803fcb59a9 Merge remote-tracking branch 'origin/assigned_value_is_garbage_or_undefined' into integration_2023_w43 2023-10-30 10:22:03 +01:00
Robert Schmidt a51c5299c6 Merge remote-tracking branch 'origin/polar-encoder-perf-improv' into integration_2023_w43 2023-10-27 14:21:23 +02:00
Laurent THOMAS bba9aac079 fix most of doxygen warnings and errors 2023-10-26 16:47:19 +02:00
rmagueta e14903cd96 Call __builtin_popcountll function to count the number of bits set in uint64_t variable for polar codes 2023-10-26 12:23:20 +02:00
mir 2ccc58f6d3 Assigned value is garbage or undefined reportedt by scan-build 2023-10-25 11:51:33 +02:00
Raphael Defosseux 80c2bc3fcb fix(arm-build): immintrin.h is not available 
Signed-off-by: Raphael Defosseux <raphael.defosseux@eurecom.fr>
 2023-10-20 11:36:39 +02:00
luis_pereira87 58f6cb2af9 Implement function for reversing bits with better performance 2023-09-27 08:30:06 +01:00
Tsung-Yu Chan 1f2098fcce feat / work with cross-compile 
can compile the target ldpc_generators and generate_T with cross-compiler
 2023-09-13 17:20:08 +02:00
Laurent THOMAS 5c7c51089b remove useless macro, the SIMD instruction is used in other places 2023-09-13 17:20:08 +02:00
Laurent THOMAS a62641f9f3 remove race condition on norm128 global 2023-09-13 17:20:04 +02:00
Raymond Knopp a7bc282302 First-level of support for new aarch64 machines 
Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators.

- Changes:
- use SIMDE consistently
- adaptations of LDPC decoder generator for ARMv8 performance
- SIMDe modifications of Intel CRC to allow for aarch64 build.
  optimizations for 128-bit to improve performance of LDPC encode/decode
  on aarch64 (Neoverse 1)
- added BG2 files for 128-bit ldpc encoder (aarch64)
- testing on Xeon
- testing on x86
- minor changes to build/run on x86
- change in crc.h after returning to aarch64
- removed some warning in ldpc decoder generator for x86_64
- char
- Delete irrelevant constants
- Correctly declare variables
- Define stdbool for all architectures
- Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE
- Remove commented code
- Fix CMakeLists.txt
- Include SIMDE avx2 functions in tools_defs.h
 2023-09-13 17:19:20 +02:00
Laurent THOMAS 206aa36a47 Make read-only globals const, additional fixes 
- Global variables that are never written to are marked const
- Remove some EXTERN declaration
- Remove unused `log_mem_multi` from logging module
 2023-08-18 14:20:37 +02:00
Robert Schmidt 92ba679bbf Merge remote-tracking branch 'origin/develop-PUCCH2' into integration_2023_w28 2023-07-13 18:47:46 +02:00
Robert Schmidt 97cf8a48a9 Merge remote-tracking branch 'origin/doc-env-var' into integration_2023_w27 2023-07-07 09:00:54 +02:00
rmagueta b722d92fa0 Extract the information bits from U 2023-07-03 11:40:35 +01:00
rmagueta fb7d4dc4df Compute parity_check_bit_pattern and implementation of function nr_polar_generate_u() and nr_polar_uxG() 2023-07-03 11:40:35 +01:00
rmagueta d6b7b6b918 Q_PC_N computation for n_pc_wm = 0 2023-07-03 11:40:35 +01:00
Roberto Louro Magueta 98ed514cab Implementation for de-interleaving of coded bits 2023-07-03 11:40:35 +01:00
Roberto Louro Magueta e5825139d7 Implementation for interleaving of coded bits 2023-07-03 11:40:35 +01:00
Melissa Elkadi a0a2248ea1 Introduce #defines for Sidelink Synchronization 
Implement the #define variables required for synchronization: These
variables include offset and payload size values that vary from the Uu
interface, in relation to the PSS, SSS and PBCH elements. We also
introduce the new sl_mode command line flag, which is used to switch
between the Uu interface and SL interface. This will allow us to modify
exisitng PSS and SSS functions, without copying complete 5G functions
and only changing a few lines to support sidelink mode.

Fixing formatting for softmodem-common.h
 2023-06-30 18:55:28 +02:00
Robert Schmidt 01d1a47adf Remove commented code that uses getenv(): it might be confusing if reactivated 2023-06-28 07:16:00 +02:00
Robert Schmidt 84f071449b Merge remote-tracking branch 'origin/workaround-clang-compilation-time' into integration_2023_w25 2023-06-22 18:13:44 +02:00
Laurent THOMAS a773d024e8 no sanitize on generated ldpc code 2023-06-19 09:48:17 +02:00
laurent 615324294b ldpc check based on crc 2023-06-12 10:24:57 +02:00
Laurent THOMAS 3645c96c09 remove generic thread pool abort 2023-06-12 10:24:37 +02:00
laurent 1b09f683f9 Fix compilation errors due to -Werror 2023-06-08 19:15:24 +02:00